/openbmc/openbmc/meta-nuvoton/conf/machine/include/ |
H A D | npcm8xx.inc | 2 #@NAME: Nuvoton NPCM8XX 3 #@DESCRIPTION: Common machine configuration for Nuvoton NPCM8XX Chip 31 SOC_FAMILY = "npcm8xx" 33 MACHINEOVERRIDES .= ":npcm8xx" 37 COMPATIBLE_MACHINE:npcm8xx = "npcm8xx"
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/openbmc/openbmc/meta-phosphor/classes/ |
H A D | image_types_phosphor_nuvoton_npcm8xx.bbclass | 25 do_make_ubi[depends] += "npcm8xx-bootloader:do_deploy" 26 do_generate_ubi_tar[depends] += "npcm8xx-bootloader:do_deploy" 27 do_generate_static_tar[depends] += "npcm8xx-bootloader:do_deploy" 29 npcm8xx-bootloader:do_deploy \ 32 do_generate_static_norootfs[depends] += "npcm8xx-bootloader:do_deploy" 33 do_generate_ext4_tar[depends] += "npcm8xx-bootloader:do_deploy"
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/openbmc/openbmc/meta-nuvoton/recipes-bsp/images/ |
H A D | npcm8xx-tip-fw.inc | 1 SUMMARY = "TIP FW for NPCM8XX (Arbel) devices" 2 DESCRIPTION = "TIP FW for NPCM8XX (Arbel) devices" 3 HOMEPAGE = "https://github.com/Nuvoton-Israel/npcm8xx-tip-fw" 11 SRC_URI = "git://github.com/Nuvoton-Israel/npcm8xx-tip-fw;branch=main;protocol=https"
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H A D | npcm8xx-bootloader_04.02.07.bb | 1 SUMMARY = "Nuvoton NPCM8XX bootloader" 2 DESCRIPTION = "This is front end recipe for NPCM8XX IGPS. It replace \ 7 HOMEPAGE = "https://github.com/Nuvoton-Israel/igps-npcm8xx" 13 git://github.com/Nuvoton-Israel/igps-npcm8xx;branch=${IGPS_BRANCH};protocol=https \ 60 npcm8xx-tip-fw:do_deploy npcm8xx-bootblock:do_deploy \
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H A D | npcm8xx-bootblock.inc | 1 SUMMARY = "Primary bootloader for NPCM8XX (Arbel) devices" 2 DESCRIPTION = "Primary bootloader for NPCM8XX (Arbel) devices" 3 HOMEPAGE = "https://github.com/Nuvoton-Israel/npcm8xx-bootblock" 13 git://github.com/Nuvoton-Israel/npcm8xx-bootblock;branch=${BB_BRANCH};protocol=https"
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H A D | npcm8xx-bootblock_0.5.4.bb | 3 require npcm8xx-bootblock.inc
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H A D | npcm8xx-tip-fw_0.7.6.0.6.5.bb | 5 require npcm8xx-tip-fw.inc
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | nuvoton,npcm845-clk.yaml | 7 title: Nuvoton NPCM8XX Clock Controller 13 Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which 27 See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full 28 list of NPCM8XX clock IDs.
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/openbmc/openbmc/meta-facebook/meta-yosemite4/meta-yosemite4n/conf/machine/ |
H A D | yosemite4n.conf | 12 ARCH_DEFAULT_KERNELIMAGETYPE:npcm8xx = "Image" 15 require conf/machine/include/npcm8xx.inc 17 UBOOT_MKIMAGE:append:npcm8xx = " -E -B 8"
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/openbmc/linux/Documentation/devicetree/bindings/spi/ |
H A D | nuvoton,npcm-fiu.txt | 9 The NPCM8XX supports four FIU modules, 15 "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC 38 In the NPCM8XX BMC:
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/openbmc/openbmc/meta-nuvoton/recipes-phosphor/ipmi/ |
H A D | phosphor-ipmi-flash_%.bbappend | 1 # NPCM8xx is using 0x0850 as PCI device-id. 3 EXTRA_OEMESON:append:npcm8xx = " -Dnuvoton-pci-did=${NUVOTON_PCI_DID}"
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/openbmc/openbmc/meta-nuvoton/dynamic-layers/arm-layer/recipes-security/optee/ |
H A D | optee-os_%.bbappend | 1 EXTRA_OEMAKE:append:npcm8xx = " \ 11 do_deploy:npcm8xx() {
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/openbmc/openbmc/meta-nuvoton/recipes-kernel/linux/ |
H A D | linux-nuvoton.inc | 12 SRC_URI:append:npcm8xx = " file://npcm8xx_defconfig" 18 UBOOT_MKIMAGE:append:npcm8xx = " -E -B 8"
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/openbmc/linux/drivers/pinctrl/nuvoton/ |
H A D | Kconfig | 37 tristate "Pinctrl and GPIO driver for Nuvoton NPCM8XX" 47 the Nuvoton NPCM8XX SoC. This is strongly recommended when
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H A D | Makefile | 6 obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
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/openbmc/linux/Documentation/devicetree/bindings/gpio/ |
H A D | nuvoton,sgpio.yaml | 13 This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC and detailed 19 NPCM7xx/NPCM8xx have two sgpio modules. Each module can support up
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/openbmc/linux/Documentation/devicetree/bindings/hwmon/ |
H A D | npcm750-pwm-fan.txt | 6 The Nuvoton BMC NPCM8XX supports 12 Pulse-width modulation (PWM) 13 : "nuvoton,npcm845-pwm-fan" for Arbel NPCM8XX.
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/openbmc/google-misc/subprojects/espi-control/ |
H A D | npcm7xx_espi_control.cpp | 18 * It could also be extended to support NPCM8xx, but it hasn't been tested with 121 * Note: This binary would probably work on NPCM8xx, as well, if we also in modifyESPIRegisters() 122 * allowed the NPCM8xx PDID, since the register addresses are the same. But in modifyESPIRegisters()
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/openbmc/linux/drivers/clk/ |
H A D | clk-npcm8xx.c | 3 * Nuvoton NPCM8xx Clock Generator 24 #include <soc/nuvoton/clock-npcm8xx.h> 26 /* npcm8xx clock registers*/ 415 .name = "reset_npcm.clk-npcm8xx", 427 MODULE_DESCRIPTION("Clock driver for Nuvoton NPCM8XX BMC SoC");
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/openbmc/openbmc/meta-nuvoton/recipes-bsp/u-boot/ |
H A D | u-boot-nuvoton_2023.10.bb | 1 DESCRIPTION = "U-boot for Nuvoton NPCM7xx/NPCM8xx Baseboard Management Controller"
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H A D | u-boot-nuvoton_2021.04.bb | 1 DESCRIPTION = "U-boot for Nuvoton NPCM7xx/NPCM8xx Baseboard Management Controller"
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/openbmc/openbmc/meta-nuvoton/conf/ |
H A D | layer.conf | 11 LAYERDEPENDS_nuvoton-layer:append:npcm8xx = " meta-arm"
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/openbmc/linux/arch/arm64/ |
H A D | Kconfig.platforms | 244 General support for NPCM8xx BMC (Arbel). 245 Nuvoton NPCM8xx BMC based on the Cortex A35.
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | nuvoton,npcm845-clk.h | 6 * Device Tree binding constants for NPCM8XX clock controller.
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/openbmc/linux/drivers/peci/controller/ |
H A D | Kconfig | 27 and NPCM8XX SoCs. It allows BMC to discover devices connected
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