1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2a1d1e0e3SJonathan Neuschäfer 3a1d1e0e3SJonathan Neuschäferconfig PINCTRL_WPCM450 4a1d1e0e3SJonathan Neuschäfer tristate "Pinctrl and GPIO driver for Nuvoton WPCM450" 5a1d1e0e3SJonathan Neuschäfer depends on ARCH_WPCM450 || COMPILE_TEST 644e445edSZheng Bin depends on OF 7a1d1e0e3SJonathan Neuschäfer select PINMUX 8a1d1e0e3SJonathan Neuschäfer select PINCONF 9a1d1e0e3SJonathan Neuschäfer select GENERIC_PINCONF 100bb85088SJonathan Neuschäfer select GENERIC_PINCTRL_GROUPS 11a1d1e0e3SJonathan Neuschäfer select GPIOLIB 12a1d1e0e3SJonathan Neuschäfer select GPIO_GENERIC 13a1d1e0e3SJonathan Neuschäfer select GPIOLIB_IRQCHIP 14f9a5502fSJonathan Neuschäfer select MFD_SYSCON 15a1d1e0e3SJonathan Neuschäfer help 16a1d1e0e3SJonathan Neuschäfer Say Y or M here to enable pin controller and GPIO support for 17a1d1e0e3SJonathan Neuschäfer the Nuvoton WPCM450 SoC. This is strongly recommended when 18a1d1e0e3SJonathan Neuschäfer building a kernel that will run on this chip. 19a1d1e0e3SJonathan Neuschäfer 20a1d1e0e3SJonathan Neuschäfer If this driver is compiled as a module, it will be named 21a1d1e0e3SJonathan Neuschäfer pinctrl-wpcm450. 22a1d1e0e3SJonathan Neuschäfer 233b588e43STomer Maimonconfig PINCTRL_NPCM7XX 243b588e43STomer Maimon bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" 253b588e43STomer Maimon depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF 263b588e43STomer Maimon select PINMUX 273b588e43STomer Maimon select PINCONF 283b588e43STomer Maimon select GENERIC_PINCONF 293b588e43STomer Maimon select GPIOLIB 303b588e43STomer Maimon select GPIO_GENERIC 313b588e43STomer Maimon select GPIOLIB_IRQCHIP 323b588e43STomer Maimon help 333b588e43STomer Maimon Say Y here to enable pin controller and GPIO support 343b588e43STomer Maimon for Nuvoton NPCM750/730/715/705 SoCs. 35bedbfcaeSTomer Maimon 36bedbfcaeSTomer Maimonconfig PINCTRL_NPCM8XX 37bedbfcaeSTomer Maimon tristate "Pinctrl and GPIO driver for Nuvoton NPCM8XX" 38bedbfcaeSTomer Maimon depends on ARCH_NPCM || COMPILE_TEST 39bedbfcaeSTomer Maimon select PINMUX 40bedbfcaeSTomer Maimon select PINCONF 41bedbfcaeSTomer Maimon select GENERIC_PINCONF 42bedbfcaeSTomer Maimon select GPIOLIB 43bedbfcaeSTomer Maimon select GPIO_GENERIC 44bedbfcaeSTomer Maimon select GPIOLIB_IRQCHIP 45bedbfcaeSTomer Maimon help 46bedbfcaeSTomer Maimon Say Y or M here to enable pin controller and GPIO support for 47bedbfcaeSTomer Maimon the Nuvoton NPCM8XX SoC. This is strongly recommended when 48bedbfcaeSTomer Maimon building a kernel that will run on this chip. 49