| /openbmc/u-boot/doc/device-tree-bindings/timer/ |
| H A D | atcpit100_timer.txt | 2 ------------------------------------------------------------------
6 This timer is a set of compact multi-function timers, which can be
10 multi-function timer and provide the following usage scenarios:
11 One 32-bit timer
12 Two 16-bit timers
13 Four 8-bit timers
14 One 16-bit PWM
15 One 16-bit timer and one 8-bit PWM
16 Two 8-bit timer and one 8-bit PWM
19 - compatible : Should be "andestech,atcpit100"
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| /openbmc/u-boot/drivers/adc/ |
| H A D | Kconfig | 5 by single and multi-channel methods for:
6 - start/stop/get data for conversion of a single-channel selected by
7 a number or multi-channels selected by a bitmask
8 - get data mask (ADC resolution)
10 - methods for get Vdd/Vss reference Voltage values with polarity
11 - support supply's phandle with auto-enable
12 - supply polarity setting in fdt
19 - 10 analog input channels
20 - 12-bit resolution
21 - 600 KSPS of sample rate
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| /openbmc/u-boot/drivers/mtd/spi/ |
| H A D | sf_internal.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
41 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
42 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
43 #define SST_WRITE BIT(2) /* use SST byte programming */
44 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
45 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
46 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
47 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
48 #define USE_FSR BIT(7) /* use flag status register */
49 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
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| /openbmc/u-boot/include/ |
| H A D | adc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
10 /* ADC_CHANNEL() - ADC channel bit mask, to select only required channels */
13 /* The last possible selected channel with 32-bit mask */
19 * - ADC_DATA_FORMAT_BIN - binary offset
20 * - ADC_DATA_FORMAT_2S - two's complement
31 * struct adc_channel - structure to hold channel conversion data.
32 * Useful to keep the result of a multi-channel conversion output.
34 * @id - channel id
35 * @data - channel conversion data
43 * struct adc_uclass_platdata - basic ADC info
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| /openbmc/qemu/tests/qemu-iotests/ |
| H A D | 307.out | 5 {"execute": "nbd-server-start", "arguments": {"addr": {"data": {"path": "SOCK_DIR/PID-socket"}, "ty…
7 {"execute": "query-block-exports", "arguments": {}}
10 === Create a read-only NBD export ===
11 {"execute": "block-export-add", "arguments": {"id": "export0", "node-name": "fmt", "type": "nbd"}}
13 {"execute": "query-block-exports", "arguments": {}}
14 {"return": [{"id": "export0", "node-name": "fmt", "shutting-down": false, "type": "nbd"}]}
18 flags: 0x158f ( readonly flush fua df multi cache block-status-payload )
22 transaction size: 64-bit
28 {"execute": "block-export-add", "arguments": {"id": "#invalid", "node-name": "fmt", "type": "nbd"}}
30 {"execute": "block-export-add", "arguments": {"id": "export0", "node-name": "fmt", "type": "nbd"}}
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| H A D | 223.out | 14 …croseconds": TIMESTAMP}, "event": "SHUTDOWN", "data": {"guest": false, "reason": "host-qmp-quit"}}
29 {"execute":"blockdev-add",
30 "arguments":{"driver":"IMGFMT", "node-name":"n",
33 {"execute":"block-dirty-bitmap-disable",
36 {"execute":"blockdev-add",
37 "arguments":{"driver":"null-co", "node-name":"null",
40 {"execute":"block-dirty-bitmap-add",
46 {"execute":"nbd-server-add",
49 {"execute":"nbd-server-start",
53 {"execute":"nbd-server-start",
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| /openbmc/libcper/examples/ |
| H A D | memory-validation-bits.json | 13 "timestamp": "9932-01-17T01:00:19+00:00",
15 "platformID": "00000000-0000-0000-0000-000000000000",
16 "creatorID": "00000000-0000-0000-0000-000000000000",
18 "guid": "00000000-0000-0000-0000-000000000000",
47 "data": "a5bc1114-6f64-4ede-b863-3e83ed7c83b1",
50 "fruID": "cc4f334a-c563-11eb-8f88-9f7ac76c6f0c",
59 … "message": "A Multi-bit ECC Memory Error occurred at address 0x0000000080000000 at node 0",
66 "name": "Multi-bit ECC"
|
| /openbmc/libcper/include/libcper/sections/ |
| H A D | cper-section-memory.h | 40 "Single-bit ECC", \
41 "Multi-bit ECC", \
42 "Single-symbol ChipKill ECC", \
43 "Multi-symbol ChipKill ECC", \
53 "Physical Memory Map-out Event" }
|
| /openbmc/u-boot/board/micronas/vct/ |
| H A D | dcgu.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
62 DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */
63 DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */
66 DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */
92 u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */
93 u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */
94 u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */
95 u32 en_clksmc:1; /* Enable bit for clksmc (#) */
96 u32 en_clkebi:1; /* Enable bit for clkebi (#) */
97 u32 en_usbpll:1; /* Enable bit for the USB PLL */
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/ |
| H A D | Cpu.interface.yaml | 4 - name: Socket
9 - name: Family
15 - name: EffectiveFamily
22 - name: EffectiveModel
28 - name: Id
31 This Processor ID field contains processor-specific information that
36 - name: MaxSpeedInMhz
40 - name: Characteristics
43 The set of boolean flags for processor's capability, such as 64-bit
44 Capable, Multi-Core, Hardware Thread, Execute Protection, Enhanced
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| /openbmc/u-boot/doc/ |
| H A D | README.bitbangMII | 1 This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to
4 buses are implemented via bit-banging mode.
9 CONFIG_BITBANGMII - Enable the miiphybb driver
10 CONFIG_BITBANGMII_MULTI - Enable the multi bus support
15 MII_INIT - Generic code to enable the MII bus (optional)
16 MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional)
17 MDIO_ACTIVE - Activate the MDIO pin as out pin
18 MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
19 MDIO_READ - Read the MDIO pin
20 MDIO(v) - Write v on the MDIO pin
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| H A D | README.blackfin | 1 Notes for the Blackfin architecture port of Das U-Boot
8 Blackfin Processors embody a new breed of 16/32-bit embedded processor, ideally
9 suited for products where a convergence of capabilities are necessary -
10 multi-format audio, video, voice and image processing; multi-mode baseband and
11 packet processing; control processing; and real-time security. The Blackfin's
26 In particular, bug reports, feature requests, help etc... for Das U-Boot are
27 handled in the Das U-Boot sub project:
28 http://blackfin.uclinux.org/gf/project/u-boot
38 the Blackfin processor. You can obtain such a cross-compiler here:
46 http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot
|
| /openbmc/u-boot/drivers/gpio/ |
| H A D | mvmfp.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
16 * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
22 * Multi-Function Pin registers.
23 * It supports - Alternate Function Selection programming.
27 * array consists of 32bit values as defined in MFP(xx,xx..) macro
51 * perform a read-back of any MFPR register to make sure the in mfp_config()
|
| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | macro.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * include/asm-arm/macro.h
5 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
18 * These macros provide a convenient way to write 8, 16 and 32 bit data
24 * caches are enabled or on a multi-core system.
81 * Branch if current processor is a Cortex-A57 core.
87 cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
92 * Branch if current processor is a Cortex-A53 core.
98 cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
108 /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/rsyslog/rsyslog/ |
| H A D | rsyslog.service | 4 Wants=network.target network-online.target
5 After=network.target network-online.target
11 ExecStart=@sbindir@/rsyslogd -n -iNONE
13 Restart=on-failure
15 # Increase the default a bit in order to allow many simultaneous
20 WantedBy=multi-user.target
|
| /openbmc/u-boot/arch/x86/ |
| H A D | Kconfig | 8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
23 bool "32-bit"
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | mmc_spi.c | 5 * Licensed under the GPL-2 or later.
13 #include <u-boot/crc.h>
25 /* R1 bit 7 is always zero, reuse this bit for error */
41 /* MMC SPI commands start with a start bit "0" and a transmit bit "1" */
55 struct spi_slave *spi = mmc->priv; in mmc_spi_sendcmd()
79 struct spi_slave *spi = mmc->priv; in mmc_spi_readdata()
84 while (bcnt--) { in mmc_spi_readdata()
96 debug("%s: CRC error\n", mmc->cfg->name); in mmc_spi_readdata()
112 u32 bcnt, u32 bsize, int multi) in mmc_spi_writedata() argument
114 struct spi_slave *spi = mmc->priv; in mmc_spi_writedata()
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| /openbmc/u-boot/board/Marvell/mvebu_armada-37xx/ |
| H A D | board.c | 1 // SPDX-License-Identifier: GPL-2.0+
28 /* SMI addresses for multi-chip mode */
32 /* Multi-chip mode */
41 /* Single-chip mode */
58 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
71 if (!of_machine_is_compatible("marvell,armada-3720-db")) in board_ahci_enable()
74 /* Configure IO exander PCA9555: 7bit address 0x22 */ in board_ahci_enable()
84 return -EIO; in board_ahci_enable()
89 * the corresponding bit to output mode to enable power for SATA in board_ahci_enable()
95 return -EIO; in board_ahci_enable()
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| /openbmc/u-boot/board/freescale/bsc9131rdb/ |
| H A D | README | 2 --------
3 - BSC9131 is integrated device that targets Femto base station market.
5 technologies with MAPLE-B2F baseband acceleration processing elements.
6 - It's MAPLE disabled personality is called 9231.
9 . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
12 . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
13 Processing (MAPLE-B2F)
14 . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
20 . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
[all …]
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| /openbmc/u-boot/board/alliedtelesis/SBx81LIFKW/ |
| H A D | sbx81lifkw.c | 1 // SPDX-License-Identifier: GPL-2.0+
24 * GPIO39 - INT(<) NC MUX_RST_N(>) NC POE_DIS_N(>) NC
27 #define SBX81LIFKW_OE_LOW ~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \
28 BIT(18) | BIT(17) | BIT(13) | BIT(12) | \
29 BIT(10))
30 #define SBX81LIFKW_OE_HIGH ~(BIT(0) | BIT(1) | BIT(7))
31 #define SBX81LIFKW_OE_VAL_LOW (BIT(31) | BIT(30) | BIT(28) | BIT(27))
32 #define SBX81LIFKW_OE_VAL_HIGH (BIT(0) | BIT(1))
46 BIT(10),
47 BIT(18) | BIT(10)
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| /openbmc/openbmc/meta-raspberrypi/docs/ |
| H A D | layer-contents.md | 7 * raspberrypi0-wifi
8 * raspberrypi0-2w-64
11 * raspberrypi3-64 (64 bit kernel & userspace)
13 * raspberrypi4-64 (64 bit kernel & userspace)
15 * raspberrypi-cm (dummy alias for raspberrypi)
16 * raspberrypi-cm3
20 ## Multi-board Machines
30 ### raspberrypi-armv7
32 This machine targets support for all the ARMv7-based Raspberry Pi boards. It
36 ### raspberrypi-armv8
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| /openbmc/openbmc/meta-facebook/meta-catalina/recipes-phosphor/state/phosphor-state-manager/catalina/ |
| H A D | power-cmd | 3 # shellcheck source=meta-facebook/recipes-fb/obmc_functions/files/fb-common-functions
4 source /usr/libexec/fb-common-functions
28 output=$(i2ctransfer -y -f 14 w1@0x1e 0x00 r16)
33 read -ra hex_array <<< "$output"
45 [[ $1 -eq 1 ]] && echo "deassert" || echo "assert"
51 # reg[3], bit 3, wCHASSIS0_LEAK_Q_N_PLD_db
53 # reg[3], bit 2, wCHASSIS1_LEAK_Q_N_PLD_db
55 # reg[3], bit 1, wCHASSIS2_LEAK_Q_N_PLD_db
57 # reg[3], bit 0, wCHASSIS3_LEAK_Q_N_PLD_db
62 # reg[11], bit 7, PWRGD_P3V3_AUX_PLD
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| /openbmc/qemu/docs/system/ |
| H A D | target-mips.rst | 1 .. _MIPS-System-emulator:
4 --------------------
6 Four executables cover simulation of 32 and 64-bit MIPS systems in both
7 endian options, ``qemu-system-mips``, ``qemu-system-mipsel``
8 ``qemu-system-mips64`` and ``qemu-system-mips64el``. Five different
11 - The MIPS Malta prototype board \"malta\"
13 - An ACER Pica \"pica61\". This machine needs the 64-bit emulator.
15 - MIPS emulator pseudo board \"mipssim\"
17 - A MIPS Magnum R4000 machine \"magnum\". This machine needs the
18 64-bit emulator.
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| /openbmc/u-boot/arch/x86/include/asm/ |
| H A D | tables.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #define ROM_TABLE_END (CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1)
16 /* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
20 * table_compute_checksum() - Compute a table checksum
22 * This computes an 8-bit checksum for the configuration table.
28 * @return: the 8-bit checksum
33 * table_fill_string() - Fill a string with pad in the configuration table
47 * write_tables() - Write x86 configuration tables
50 * Multi-Processor table and ACPI table. Whether a specific type of
56 * write_pirq_routing_table() - Write PIRQ routing table
|
| /openbmc/u-boot/board/LaCie/netspace_v2/ |
| H A D | netspace_v2.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
14 #include <asm/mach-types.h>
31 /* Multi-Purpose Pins Functionality configuration */ in board_early_init_f()
40 MPP7_GPO, /* Fan speed (bit 1) */ in board_early_init_f()
53 MPP22_GPIO, /* Fan speed (bit 0) */ in board_early_init_f()
57 MPP26_GPIO, /* USB vbus-in detection */ in board_early_init_f()
58 MPP28_GPIO, /* USB enable vbus-out */ in board_early_init_f()
63 MPP33_GPIO, /* Fan speed (bit 2) */ in board_early_init_f()
74 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; in board_init()
[all …]
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