1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 250752790SStefan Roese /* 350752790SStefan Roese * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering 450752790SStefan Roese * 550752790SStefan Roese * Copyright (C) 2006 Micronas GmbH 650752790SStefan Roese */ 750752790SStefan Roese 850752790SStefan Roese #ifndef _DCGU_H 950752790SStefan Roese #define _DCGU_H 1050752790SStefan Roese 1150752790SStefan Roese enum dcgu_switch { 1250752790SStefan Roese DCGU_SWITCH_OFF, /* Switch off */ 1350752790SStefan Roese DCGU_SWITCH_ON /* Switch on */ 1450752790SStefan Roese }; 1550752790SStefan Roese 1650752790SStefan Roese enum dcgu_hw_module { 1750752790SStefan Roese DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */ 1850752790SStefan Roese 1950752790SStefan Roese DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */ 2050752790SStefan Roese DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/ 2150752790SStefan Roese 2250752790SStefan Roese DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */ 2350752790SStefan Roese DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */ 2450752790SStefan Roese DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */ 2550752790SStefan Roese DCGU_HW_MODULE_DVP, /* Selects dig video processing module */ 2650752790SStefan Roese DCGU_HW_MODULE_CVE, /* Selects color video encoder module */ 2750752790SStefan Roese DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */ 2850752790SStefan Roese 2950752790SStefan Roese DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */ 3050752790SStefan Roese DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */ 3150752790SStefan Roese 3250752790SStefan Roese DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */ 3350752790SStefan Roese DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */ 3450752790SStefan Roese 3550752790SStefan Roese DCGU_HW_MODULE_UART_1, /* Selects first UART module */ 3650752790SStefan Roese DCGU_HW_MODULE_UART_2, /* Selects second UART module */ 3750752790SStefan Roese 3850752790SStefan Roese DCGU_HW_MODULE_AD, /* Selects audio decoder module */ 3950752790SStefan Roese DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */ 4050752790SStefan Roese DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/ 4150752790SStefan Roese DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */ 4250752790SStefan Roese 4350752790SStefan Roese DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/ 4450752790SStefan Roese DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */ 4550752790SStefan Roese DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */ 4650752790SStefan Roese 4750752790SStefan Roese DCGU_HW_MODULE_USBH, /* Selects USB hub module */ 4850752790SStefan Roese DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */ 4950752790SStefan Roese DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */ 5050752790SStefan Roese DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */ 5150752790SStefan Roese 5250752790SStefan Roese DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/ 5350752790SStefan Roese DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/ 5450752790SStefan Roese DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/ 5550752790SStefan Roese DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */ 5650752790SStefan Roese DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */ 5750752790SStefan Roese DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */ 5850752790SStefan Roese 5950752790SStefan Roese DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/ 6050752790SStefan Roese DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/ 6150752790SStefan Roese 6250752790SStefan Roese DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */ 6350752790SStefan Roese DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */ 6450752790SStefan Roese 6550752790SStefan Roese DCGU_HW_MODULE_COM, /* Selects COM unit module */ 6650752790SStefan Roese DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */ 6750752790SStefan Roese DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */ 6850752790SStefan Roese 6950752790SStefan Roese DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/ 7050752790SStefan Roese DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */ 7150752790SStefan Roese DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */ 7250752790SStefan Roese DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */ 7350752790SStefan Roese 7450752790SStefan Roese DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */ 7550752790SStefan Roese DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */ 7650752790SStefan Roese DCGU_HW_MODULE_SRAM, /* Selects SRAM module */ 7750752790SStefan Roese DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/ 7850752790SStefan Roese DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */ 7950752790SStefan Roese DCGU_HW_MODULE_SCC, /* Selects SCC module */ 8050752790SStefan Roese DCGU_HW_MODULE_MM, /* Selects Memory Manager module */ 8150752790SStefan Roese DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */ 8250752790SStefan Roese DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */ 8350752790SStefan Roese DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */ 8450752790SStefan Roese DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */ 8550752790SStefan Roese DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/ 8650752790SStefan Roese }; 8750752790SStefan Roese 8850752790SStefan Roese union dcgu_clk_en1 { 8950752790SStefan Roese u32 reg; 9050752790SStefan Roese struct { 9150752790SStefan Roese u32 res1:8; /* reserved */ 9250752790SStefan Roese u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */ 9350752790SStefan Roese u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */ 9450752790SStefan Roese u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */ 9550752790SStefan Roese u32 en_clksmc:1; /* Enable bit for clksmc (#) */ 9650752790SStefan Roese u32 en_clkebi:1; /* Enable bit for clkebi (#) */ 9750752790SStefan Roese u32 en_usbpll:1; /* Enable bit for the USB PLL */ 9850752790SStefan Roese u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */ 9950752790SStefan Roese u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */ 10050752790SStefan Roese u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */ 10150752790SStefan Roese u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */ 10250752790SStefan Roese u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */ 10350752790SStefan Roese u32 res2:3; /* reserved */ 10450752790SStefan Roese u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */ 10550752790SStefan Roese u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */ 10650752790SStefan Roese u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */ 10750752790SStefan Roese u32 en_clkad:1; /* Enable bit for clkad (#) */ 10850752790SStefan Roese u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */ 10950752790SStefan Roese u32 en_clktsd:1; /* Enable bit for clktsd (#) */ 11050752790SStefan Roese u32 en_clkga:1; /* Enable bit for clkga (#) */ 11150752790SStefan Roese u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */ 11250752790SStefan Roese u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */ 11350752790SStefan Roese u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */ 11450752790SStefan Roese } bits; 11550752790SStefan Roese }; 11650752790SStefan Roese 11750752790SStefan Roese union dcgu_clk_en2 { 11850752790SStefan Roese u32 reg; 11950752790SStefan Roese struct { 12050752790SStefan Roese u32 res1:31; /* reserved */ 12150752790SStefan Roese u32 en_clkcpu:1; /* Enable bit for clkcpu */ 12250752790SStefan Roese } bits; 12350752790SStefan Roese }; 12450752790SStefan Roese 12550752790SStefan Roese union dcgu_reset_unit1 { 12650752790SStefan Roese u32 reg; 12750752790SStefan Roese struct { 12850752790SStefan Roese u32 res1:1; 12950752790SStefan Roese u32 swreset_clkmsmc:1; 13050752790SStefan Roese u32 swreset_clkssi_s:1; 13150752790SStefan Roese u32 swreset_clkssi_m:1; 13250752790SStefan Roese u32 swreset_clksmc:1; 13350752790SStefan Roese u32 swreset_clkebi:1; 13450752790SStefan Roese u32 swreset_clkusb60:1; 13550752790SStefan Roese u32 swreset_clkusb24:1; 13650752790SStefan Roese u32 swreset_clkuart2:1; 13750752790SStefan Roese u32 swreset_clkuart1:1; 13850752790SStefan Roese u32 swreset_pwm:1; 13950752790SStefan Roese u32 swreset_gpt:1; 14050752790SStefan Roese u32 swreset_i2c2:1; 14150752790SStefan Roese u32 swreset_i2c1:1; 14250752790SStefan Roese u32 swreset_gpio2:1; 14350752790SStefan Roese u32 swreset_gpio1:1; 14450752790SStefan Roese u32 swreset_clkcpu:1; 14550752790SStefan Roese u32 res2:2; 14650752790SStefan Roese u32 swreset_clk_i2s_dly:1; 14750752790SStefan Roese u32 swreset_clk_scc_abp:1; 14850752790SStefan Roese u32 swreset_clk_dtv_spdo:1; 14950752790SStefan Roese u32 swreset_clkad:1; 15050752790SStefan Roese u32 swreset_clkmvd:1; 15150752790SStefan Roese u32 swreset_clktsd:1; 15250752790SStefan Roese u32 swreset_clktsio:1; 15350752790SStefan Roese u32 swreset_clkga:1; 15450752790SStefan Roese u32 swreset_clkmpc:1; 15550752790SStefan Roese u32 swreset_clkcve:1; 15650752790SStefan Roese u32 swreset_clkdvp:1; 15750752790SStefan Roese u32 swreset_clkmr2:1; 15850752790SStefan Roese u32 swreset_clkmr1:1; 15950752790SStefan Roese } bits; 16050752790SStefan Roese }; 16150752790SStefan Roese 16250752790SStefan Roese int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup); 16350752790SStefan Roese int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup); 16450752790SStefan Roese 16550752790SStefan Roese #endif /* _DCGU_H */ 166