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/openbmc/qemu/hw/xen/
H A Dxen_pt_msi.c5 * the COPYING file in the top-level directory.
14 #include "hw/i386/apic-msidef.h"
16 #include "hw/xen/xen-legacy-backend.h"
19 #define XEN_PT_AUTO_ASSIGN -1
69 static inline uint64_t msi_addr64(XenPTMSI *msi) in msi_addr64() argument
71 return (uint64_t)msi->addr_hi << 32 | msi->addr_lo; in msi_addr64()
83 return -1; in msi_msix_enable()
86 rc = xen_host_pci_get_word(&s->real_device, address, &val); in msi_msix_enable()
88 XEN_PT_ERR(&s->dev, "Failed to read MSI/MSI-X register (0x%x), rc:%d\n", in msi_msix_enable()
97 rc = xen_host_pci_set_word(&s->real_device, address, val); in msi_msix_enable()
[all …]
H A Dxen_pt_config_init.c6 * the COPYING file in the top-level directory.
20 #include "hw/xen/xen-legacy-backend.h"
53 if (d->vendor_id == PCI_VENDOR_ID_INTEL && in xen_pt_hide_dev_cap()
54 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) { in xen_pt_hide_dev_cap()
68 QLIST_FOREACH(entry, &s->reg_grps, entries) { in xen_pt_find_reg_grp()
70 if ((entry->base_offset <= address) in xen_pt_find_reg_grp()
71 && ((entry->base_offset + entry->size) > address)) { in xen_pt_find_reg_grp()
88 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) { in xen_pt_find_reg()
89 reg = reg_entry->reg; in xen_pt_find_reg()
90 real_offset = reg_grp->base_offset + reg->offset; in xen_pt_find_reg()
[all …]
/openbmc/linux/drivers/pci/msi/
H A Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
14 #include "msi.h"
17 * pci_enable_msi() - Enable MSI interrupt mode on device
20 * Legacy device driver API to enable MSI interrupts mode on device and
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
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H A Dirqdomain.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI) - irqdomain support
9 #include "msi.h"
15 domain = dev_get_msi_domain(&dev->dev); in pci_msi_setup_msi_irqs()
17 return msi_domain_alloc_irqs_all_locked(&dev->dev, MSI_DEFAULT_DOMAIN, nvec); in pci_msi_setup_msi_irqs()
26 domain = dev_get_msi_domain(&dev->dev); in pci_msi_teardown_msi_irqs()
28 msi_domain_free_irqs_all_locked(&dev->dev, MSI_DEFAULT_DOMAIN); in pci_msi_teardown_msi_irqs()
31 msi_free_msi_descs(&dev->dev); in pci_msi_teardown_msi_irqs()
36 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
37 * @irq_data: Pointer to interrupt data of the MSI interrupt
[all …]
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
14 #include "msi.h"
20 * pci_msi_supported - check whether MSI may be enabled on a device
21 * @dev: pointer to the pci_dev data structure of MSI device function
25 * to determine if MSI/-X are supported for the device. If MSI/-X is
32 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
36 if (!dev || dev->no_msi) in pci_msi_supported()
48 * Any bridge which does NOT route MSI transactions from its in pci_msi_supported()
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/openbmc/linux/Documentation/PCI/
H A Dmsi-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
5 The MSI Driver Guide HOWTO
16 the advantages of using MSI over traditional interrupt mechanisms, how
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
27 The MSI capability was first specified in PCI 2.2 and was later enhanced
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
30 per device than MSI and allows interrupts to be independently configured.
32 Devices may support both MSI and MSI-X, but only one can be enabled at
40 traditional pin-based interrupts.
42 Pin-based PCI interrupts are often shared amongst several devices.
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/openbmc/linux/drivers/pci/controller/
H A Dpci-xgene-msi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene MSI Driver
13 #include <linux/msi.h>
27 struct xgene_msi *msi; member
48 .name = "X-Gene1 MSI",
62 * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where
63 * n is group number (0..F), x is index of registers in each group (0..7)
85 * Each index register supports 16 MSI vectors (0..15) to generate interrupt.
86 * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination
89 * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate
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H A Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
15 #include <linux/msi.h>
18 #include <linux/pci-ecam.h>
23 /* Number of MSI IRQs */
163 /* PCIe Config space MSI capability structure */
197 #define PCIE_EVENT_CAUSE(x, s) \ argument
198 [EVENT_PCIE_ ## x] = { __stringify(x), s }
200 #define SEC_ERROR_CAUSE(x, s) \ argument
201 [EVENT_SEC_ ## x] = { __stringify(x), s }
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H A Dpcie-rcar-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
16 #include <linux/clk-provider.h>
24 #include <linux/msi.h>
33 #include "pcie-rcar.h"
49 struct rcar_msi msi; member
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
25 tristate "Altera PCIe MSI feature"
29 Say Y here if you want PCIe MSI support for the Altera FPGA.
30 This MSI driver supports Altera MSI to GIC controller IP.
45 system-on-chips, like the Apple M1. This is required for the USB
46 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
93 bool "Broadcom iProc PCIe MSI support"
98 Say Y here if you want to enable MSI support for Broadcom's iProc
102 bool "Cavium Thunder PCIe controller to off-chip devices"
110 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
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/openbmc/qemu/hw/pci-host/
H A Dpnv_phb3_msi.c4 * Copyright (c) 2014-2020, IBM Corporation.
7 * COPYING file in the top-level directory.
12 #include "hw/pci-host/pnv_phb3_regs.h"
13 #include "hw/pci-host/pnv_phb3.h"
15 #include "hw/pci/msi.h"
17 #include "hw/qdev-properties.h"
22 uint64_t ivtbar = phb->regs[PHB_IVT_BAR >> 3]; in phb3_msi_ive_addr()
23 uint64_t phbctl = phb->regs[PHB_CONTROL >> 3]; in phb3_msi_ive_addr()
31 qemu_log_mask(LOG_GUEST_ERROR, "MSI out of bounds (%d vs 0x%"PRIx64")", in phb3_msi_ive_addr()
56 qemu_log_mask(LOG_GUEST_ERROR, "Failed to read IVE at 0x%" PRIx64, in phb3_msi_read_ive()
[all …]
/openbmc/linux/include/linux/
H A Dmsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This header file contains MSI data structures and functions which are
8 * - Interrupt core code
9 * - PCI/MSI core code
10 * - MSI interrupt domain implementations
11 * - IOMMU, low level VFIO, NTB and other justified exceptions
12 * dealing with low level MSI details.
15 * especially storing MSI descriptor pointers in random code is considered
30 #include <asm/msi.h>
56 * msi_msg - Representation of a MSI message
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H A Dpci-epc.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pci-epf.h>
17 UNKNOWN_INTERFACE = -1,
43 * struct pci_epc_ops - set of function pointers for performing EPC operations
49 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
51 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
52 * the MSI capability register
53 * @set_msix: ops to set the requested number of MSI-X interrupts in the
54 * MSI-X capability register
55 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dpci_msi.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_msi.c: Sparc64 MSI support common layer.
18 struct pci_pbm_info *pbm = msiq_cookie->pbm; in sparc64_msiq_interrupt()
19 unsigned long msiqid = msiq_cookie->msiqid; in sparc64_msiq_interrupt()
24 ops = pbm->msi_ops; in sparc64_msiq_interrupt()
26 err = ops->get_head(pbm, msiqid, &head); in sparc64_msiq_interrupt()
32 unsigned long msi; in sparc64_msiq_interrupt() local
34 err = ops->dequeue_msi(pbm, msiqid, &head, &msi); in sparc64_msiq_interrupt()
38 irq = pbm->msi_irq_table[msi - pbm->msi_first]; in sparc64_msiq_interrupt()
49 err = ops->set_head(pbm, msiqid, head); in sparc64_msiq_interrupt()
[all …]
/openbmc/qemu/hw/pci/
H A Dmsi.c2 * msi.c
22 #include "hw/pci/msi.h"
42 * Flag for interrupt controllers to declare broken MSI/MSI-X support.
43 * values: false - broken; true - non-broken.
45 * Setting this flag to false will remove MSI/MSI-X capability from all devices.
47 * It is preferable for controllers to set this to true (non-broken) even if
48 * they do not actually support MSI/MSI-X: guests normally probe the controller
49 * type and do not attempt to enable MSI/MSI-X with interrupt controllers not
85 MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
95 return dev->msi_cap + PCI_MSI_FLAGS; in msi_flags_off()
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/openbmc/linux/arch/powerpc/platforms/cell/
H A Daxon_msi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/msi.h>
52 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
53 * 8-9 of the MSIC control reg.
55 #define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
59 * the bounds of the FIFO. Also they should always be 16-byte aligned.
61 #define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
88 pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); in msic_dcr_write()
90 dcr_write(msic->dcr_host, dcr_n, val); in msic_dcr_write()
97 u32 write_offset, msi; in axon_msi_cascade() local
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/openbmc/linux/Documentation/translations/zh_CN/PCI/
H A Dmsi-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/PCI/msi-howto.rst
26 本指南介绍了消息标记中断（MSI）的基本知识，使用MSI相对于传统中断机制的优势，如何
27 改变你的驱动程序以使用MSI或MSI-X，以及在设备不支持MSI时可以尝试的一些基本诊断方法。
36 MSI-X功能也随着PCI 3.0被引入。它比MSI支持每个设备更多的中断，并允许独立配置中断。
38 设备可以同时支持MSI和MSI-X，但一次只能启用一个。
50 之前，中断就已经到达了（这在PCI-PCI桥后面的设备中变得更有可能）。为了确保所有的数
65 PCI设备被初始化为使用基于引脚的中断。设备驱动程序必须将设备设置为使用MSI或MSI-X。
70 -------------------
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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/openbmc/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
45 | +-------------+ +-------------+ |
46 +---------------------------------------------------------------------+
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/openbmc/linux/arch/powerpc/sysdev/
H A Dmpic_u3msi.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
9 #include <linux/msi.h>
12 #include <asm/ppc-pci.h>
39 .name = "MPIC-U3MSI",
66 for (bus = pdev->bus; bus && bus->self; bus = bus->parent) { in find_ht_magic_addr()
67 pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING); in find_ht_magic_addr()
69 return read_ht_magic_addr(bus->self, pos); in find_ht_magic_addr()
77 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in find_u4_magic_addr()
82 * the MSI number and that triggers the right interrupt, but in find_u4_magic_addr()
[all …]
H A Dmsi_bitmap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2006-2008, Michael Ellerman, IBM Corporation.
20 spin_lock_irqsave(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
22 offset = bitmap_find_next_zero_area(bmp->bitmap, bmp->irq_count, 0, in msi_bitmap_alloc_hwirqs()
23 num, (1 << order) - 1); in msi_bitmap_alloc_hwirqs()
24 if (offset > bmp->irq_count) in msi_bitmap_alloc_hwirqs()
27 bitmap_set(bmp->bitmap, offset, num); in msi_bitmap_alloc_hwirqs()
28 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
30 pr_debug("msi_bitmap: allocated 0x%x at offset 0x%x\n", num, offset); in msi_bitmap_alloc_hwirqs()
34 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
[all …]
/openbmc/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil-host.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
19 #include <linux/msi.h>
25 #include "pcie-mobiveil.h"
37 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
44 * mobiveil_pcie_map_bus - routine to get the configuration base of either
50 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
51 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
59 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
67 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
[all …]
/openbmc/linux/arch/powerpc/platforms/pasemi/
H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
13 #include <linux/msi.h>
16 #include <asm/ppc-pci.h>
23 * needs more than 32 MSI's down the road we'll have to rethink this,
36 pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq); in mpic_pasemi_msi_mask_irq()
43 pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq); in mpic_pasemi_msi_unmask_irq()
55 .name = "PASEMI-MSI",
65 msi_for_each_desc(entry, &pdev->dev, MSI_DESC_ASSOCIATED) { in pasemi_msi_teardown_msi_irqs()
66 hwirq = virq_to_hw(entry->irq); in pasemi_msi_teardown_msi_irqs()
[all …]
/openbmc/linux/drivers/xen/xen-pciback/
H A Dpciback_ops.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Backend Operations - respond to PCI requests from Frontend
35 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) in xen_pcibk_control_isr()
39 dev_data->enable_intx = 0; in xen_pcibk_control_isr()
40 dev_data->ack_intr = 0; in xen_pcibk_control_isr()
42 enable = dev_data->enable_intx; in xen_pcibk_control_isr()
45 if (!enable && !dev_data->isr_on) in xen_pcibk_control_isr()
49 * b/c when device transitions to MSI, the dev->irq is in xen_pcibk_control_isr()
50 * overwritten with the MSI vector. in xen_pcibk_control_isr()
53 dev_data->irq = dev->irq; in xen_pcibk_control_isr()
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/openbmc/linux/Documentation/misc-devices/
H A Dpci-endpoint-test.rst1 .. SPDX-License-Identifier: GPL-2.0
17 #) raise MSI IRQ
18 #) raise MSI-X IRQ
23 This misc driver creates /dev/pci-endpoint-test.<num> for every
28 -----
36 Tests message signalled interrupts. The MSI number
39 Tests message signalled interrupts. The MSI-X number
43 should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
56 .. [1] Documentation/PCI/endpoint/function/binding/pci-test.rst

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