4  * Copyright (c) 2014-2020, IBM Corporation.
7  * COPYING file in the top-level directory.
12 #include "hw/pci-host/pnv_phb3_regs.h"
13 #include "hw/pci-host/pnv_phb3.h"
15 #include "hw/pci/msi.h"
17 #include "hw/qdev-properties.h"
22     uint64_t ivtbar = phb->regs[PHB_IVT_BAR >> 3];  in phb3_msi_ive_addr()
23     uint64_t phbctl = phb->regs[PHB_CONTROL >> 3];  in phb3_msi_ive_addr()
31         qemu_log_mask(LOG_GUEST_ERROR, "MSI out of bounds (%d vs  0x%"PRIx64")",  in phb3_msi_ive_addr()
56         qemu_log_mask(LOG_GUEST_ERROR, "Failed to read IVE at 0x%" PRIx64,  in phb3_msi_read_ive()
65 static void phb3_msi_set_p(Phb3MsiState *msi, int srcno, uint8_t gen)  in phb3_msi_set_p()  argument
70     ive_addr = phb3_msi_ive_addr(msi->phb, srcno);  in phb3_msi_set_p()
78                       "Failed to write IVE (set P) at 0x%" PRIx64, ive_addr);  in phb3_msi_set_p()
82 static void phb3_msi_set_q(Phb3MsiState *msi, int srcno)  in phb3_msi_set_q()  argument
87     ive_addr = phb3_msi_ive_addr(msi->phb, srcno);  in phb3_msi_set_q()
95                       "Failed to write IVE (set Q) at 0x%" PRIx64, ive_addr);  in phb3_msi_set_q()
99 static void phb3_msi_try_send(Phb3MsiState *msi, int srcno, bool force)  in phb3_msi_try_send()  argument
101     ICSState *ics = ICS(msi);  in phb3_msi_try_send()
105     if (!phb3_msi_read_ive(msi->phb, srcno, &ive)) {  in phb3_msi_try_send()
128             phb3_msi_set_q(msi, srcno);  in phb3_msi_try_send()
131             phb3_msi_set_p(msi, srcno, gen);  in phb3_msi_try_send()
132             icp_irq(ics, server, srcno + ics->offset, prio);  in phb3_msi_try_send()
137         phb3_msi_set_q(msi, srcno);  in phb3_msi_try_send()
149     Phb3MsiState *msi = PHB3_MSI(opaque);  in phb3_msi_set_irq()  local
152         phb3_msi_try_send(msi, srcno, false);  in phb3_msi_set_irq()
157 void pnv_phb3_msi_send(Phb3MsiState *msi, uint64_t addr, uint16_t data,  in pnv_phb3_msi_send()  argument
160     ICSState *ics = ICS(msi);  in pnv_phb3_msi_send()
165     if (src >= ics->nr_irqs) {  in pnv_phb3_msi_send()
166         qemu_log_mask(LOG_GUEST_ERROR, "MSI %d out of bounds", src);  in pnv_phb3_msi_send()
170         if (!phb3_msi_read_ive(msi->phb, src, &ive)) {  in pnv_phb3_msi_send()
176                           "MSI %d send by PE#%d but assigned to PE#%d",  in pnv_phb3_msi_send()
181     qemu_irq_pulse(msi->qirqs[src]);  in pnv_phb3_msi_send()
184 void pnv_phb3_msi_ffi(Phb3MsiState *msi, uint64_t val)  in pnv_phb3_msi_ffi()  argument
187     pnv_phb3_msi_send(msi, val, 0, -1);  in pnv_phb3_msi_ffi()
190     msi->phb->regs[PHB_FFI_LOCK >> 3] = 0;  in pnv_phb3_msi_ffi()
195     Phb3MsiState *msi = PHB3_MSI(ics);  in phb3_msi_reject()  local
196     unsigned int srcno = nr - ics->offset;  in phb3_msi_reject()
202     msi->rba[idx] |= bit;  in phb3_msi_reject()
203     msi->rba_sum |= (1u << idx);  in phb3_msi_reject()
208     Phb3MsiState *msi = PHB3_MSI(ics);  in phb3_msi_resend()  local
211     if (msi->rba_sum == 0) {  in phb3_msi_resend()
216         if ((msi->rba_sum & (1u << i)) == 0) {  in phb3_msi_resend()
219         msi->rba_sum &= ~(1u << i);  in phb3_msi_resend()
221             if ((msi->rba[i] & (1ull << j)) == 0) {  in phb3_msi_resend()
224             msi->rba[i] &= ~(1ull << j);  in phb3_msi_resend()
225             phb3_msi_try_send(msi, i * 64 + j, true);  in phb3_msi_resend()
232     Phb3MsiState *msi = PHB3_MSI(obj);  in phb3_msi_reset_hold()  local
235     if (icsc->parent_phases.hold) {  in phb3_msi_reset_hold()
236         icsc->parent_phases.hold(obj, type);  in phb3_msi_reset_hold()
239     memset(msi->rba, 0, sizeof(msi->rba));  in phb3_msi_reset_hold()
240     msi->rba_sum = 0;  in phb3_msi_reset_hold()
243 void pnv_phb3_msi_update_config(Phb3MsiState *msi, uint32_t base,  in pnv_phb3_msi_update_config()  argument
246     ICSState *ics = ICS(msi);  in pnv_phb3_msi_update_config()
251     ics->nr_irqs = count;  in pnv_phb3_msi_update_config()
252     ics->offset = base;  in pnv_phb3_msi_update_config()
257     Phb3MsiState *msi = PHB3_MSI(dev);  in phb3_msi_realize()  local
258     ICSState *ics = ICS(msi);  in phb3_msi_realize()
262     assert(msi->phb);  in phb3_msi_realize()
264     icsc->parent_realize(dev, &local_err);  in phb3_msi_realize()
270     msi->qirqs = qemu_allocate_irqs(phb3_msi_set_irq, msi, ics->nr_irqs);  in phb3_msi_realize()
275     Phb3MsiState *msi = PHB3_MSI(obj);  in phb3_msi_instance_init()  local
279                              (Object **)&msi->phb,  in phb3_msi_instance_init()
284     ics->offset = 0;  in phb3_msi_instance_init()
294                                     &isc->parent_realize);  in phb3_msi_class_init()
296                                        &isc->parent_phases);  in phb3_msi_class_init()
298     isc->reject = phb3_msi_reject;  in phb3_msi_class_init()
299     isc->resend = phb3_msi_resend;  in phb3_msi_class_init()
318 void pnv_phb3_msi_pic_print_info(Phb3MsiState *msi, GString *buf)  in pnv_phb3_msi_pic_print_info()  argument
320     ICSState *ics = ICS(msi);  in pnv_phb3_msi_pic_print_info()
323     g_string_append_printf(buf, "ICS %4x..%4x %p\n",  in pnv_phb3_msi_pic_print_info()
324                            ics->offset, ics->offset + ics->nr_irqs - 1, ics);  in pnv_phb3_msi_pic_print_info()
326     for (i = 0; i < ics->nr_irqs; i++) {  in pnv_phb3_msi_pic_print_info()
329         if (!phb3_msi_read_ive(msi->phb, i, &ive)) {  in pnv_phb3_msi_pic_print_info()
337         g_string_append_printf(buf, "  %4x %c%c server=%04x prio=%02x gen=%d\n",  in pnv_phb3_msi_pic_print_info()
338                                ics->offset + i,  in pnv_phb3_msi_pic_print_info()
339                                GETFIELD(IODA2_IVT_P, ive) ? 'P' : '-',  in pnv_phb3_msi_pic_print_info()
340                                GETFIELD(IODA2_IVT_Q, ive) ? 'Q' : '-',  in pnv_phb3_msi_pic_print_info()