| /openbmc/linux/drivers/firmware/xilinx/ |
| H A D | Kconfig | 4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
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| H A D | zynqmp-debug.h | 3 * Xilinx Zynq MPSoC Firmware layer
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| H A D | zynqmp-debug.c | 3 * Xilinx Zynq MPSoC Firmware layer for debugfs APIs
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| /openbmc/linux/Documentation/devicetree/bindings/reset/ |
| H A D | xlnx,zynqmp-reset.yaml | 7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
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| /openbmc/linux/drivers/soc/xilinx/ |
| H A D | Kconfig | 5 bool "Enable Xilinx Zynq MPSoC Power Management driver"
20 bool "Enable Zynq MPSoC generic PM domains"
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| /openbmc/linux/Documentation/devicetree/bindings/fpga/ |
| H A D | xlnx,zynqmp-pcap-fpga.yaml | 7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
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| /openbmc/linux/Documentation/devicetree/bindings/rtc/ |
| H A D | xlnx,zynqmp-rtc.yaml | 7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
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| /openbmc/linux/Documentation/driver-api/xilinx/ |
| H A D | eemi.rst | 2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
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| /openbmc/linux/drivers/clk/zynqmp/ |
| H A D | Makefile | 2 # Zynq Ultrascale+ MPSoC clock specific Makefile
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| H A D | clk-gate-zynqmp.c | 3 * Zynq UltraScale+ MPSoC clock controller
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| H A D | clk-mux-zynqmp.c | 3 * Zynq UltraScale+ MPSoC mux
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | cdns,macb.yaml | 24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-zynqmp-qspi.yaml | 7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
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| /openbmc/linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | xlnx,zynqmp-nvmem.txt | 2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
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| /openbmc/linux/Documentation/devicetree/bindings/serial/ |
| H A D | cdns,uart.yaml | 19 - description: UART controller for Zynq Ultrascale+ MPSoC
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| /openbmc/linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | xlnx,zynqmp-power.yaml | 7 title: Xilinx Zynq MPSoC Power Management
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | xlnx-zynqmp-clk.h | 3 * Xilinx Zynq MPSoC Firmware layer
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| /openbmc/linux/Documentation/devicetree/bindings/firmware/xilinx/ |
| H A D | xlnx,zynqmp-firmware.yaml | 23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
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| /openbmc/linux/drivers/rtc/ |
| H A D | rtc-zynqmp.c | 3 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
395 MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | xilinx.yaml | 13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
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| /openbmc/qemu/include/hw/arm/ |
| H A D | xlnx-zynqmp.h | 2 * Xilinx Zynq MPSoC emulation
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| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun50i_h6.h | 63 * - Zynq UltraScale+ MPSoC Register Reference (UG1087)
133 * MPSoC Register Reference, as it's the currently only known
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| /openbmc/linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | xlnx,zynqmp-ipi-mailbox.yaml | 11 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
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| /openbmc/qemu/hw/microblaze/ |
| H A D | xlnx-zynqmp-pmu.c | 2 * Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
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| /openbmc/linux/Documentation/devicetree/bindings/display/xlnx/ |
| H A D | xlnx,zynqmp-dpsub.yaml | 10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
|