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/openbmc/linux/arch/arm/mach-mv78xx0/
H A Dmpp.h3 * linux/arch/arm/mach-mv78xx0/mpp.h -- Multi Purpose Pins
11 #define MPP(_num, _sel, _in, _out, _78100_A0) (\ macro
12 /* MPP number */ ((_num) & 0xff) | \
13 /* MPP select value */ (((_sel) & 0xf) << 8) | \
20 #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
22 #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
23 #define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1)
24 #define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
25 #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1)
27 #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1)
[all …]
H A Dmpp.c3 * arch/arm/mach-mv78x00/mpp.c
5 * MPP functions for Marvell MV78x00 SoCs
11 #include <plat/mpp.h>
14 #include "mpp.h"
25 printk(KERN_ERR "MPP setup: unknown mv78x00 variant " in mv78xx0_variant()
/openbmc/linux/arch/arm/mach-dove/
H A Dmpp.h5 #define MPP(_num, _sel, _in, _out) ( \ macro
6 /* MPP number */ ((_num) & 0xff) | \
7 /* MPP select value */ (((_sel) & 0xf) << 8) | \
11 #define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
12 #define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
13 #define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
14 #define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
16 #define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
17 #define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
18 #define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
[all …]
H A Dmpp.c3 * arch/arm/mach-dove/mpp.c
5 * MPP functions for Marvell Dove SoCs
11 #include <plat/mpp.h>
14 #include "mpp.h"
55 /* Dump all the extra MPP registers. The platform code will dump the
129 pr_err("dove: invalid MPP GRP number (%u)\n", num); in dove_mpp_conf_grp()
143 /* Configure the various MPP pins on Dove */
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dmpp.h3 * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
11 #define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ macro
12 /* MPP number */ ((_num) & 0xff) | \
13 /* MPP select value */ (((_sel) & 0xf) << 8) | \
26 #define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 )
27 #define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 )
29 #define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 )
30 #define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 )
31 #define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 )
32 #define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 )
[all …]
/openbmc/linux/arch/arm/mach-orion5x/
H A Dmpp.h5 #define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \ macro
6 /* MPP number */ ((_num) & 0xff) | \
7 /* MPP select value */ (((_sel) & 0xf) << 8) | \
16 #define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0)
17 #define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0)
18 #define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1)
20 #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1)
21 #define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1, 1)
22 #define MPP0_PCIE_RST_OUTn MPP(0, 0x0, 0, 0, 1, 1, 1)
23 #define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1)
[all …]
H A Dmpp.c3 * arch/arm/mach-orion5x/mpp.c
5 * MPP functions for Marvell Orion 5x SoCs
11 #include <plat/mpp.h>
13 #include "mpp.h"
32 printk(KERN_ERR "MPP setup: unknown orion5x variant " in orion5x_variant()
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,pmic-mpp.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml#
7 title: Qualcomm PMIC Multi-Purpose Pin (MPP) block
13 This binding describes the MPP block(s) found in the 8xxx series of
21 - qcom,pm8019-mpp
22 - qcom,pm8226-mpp
23 - qcom,pm8841-mpp
24 - qcom,pm8916-mpp
25 - qcom,pm8941-mpp
26 - qcom,pm8950-mpp
27 - qcom,pmi8950-mpp
[all …]
H A Dmarvell,mvebu-pinctrl.txt1 * Marvell SoC pinctrl core driver for mpp
4 (mpp) to a specific function. For each SoC family there is a SoC specific
13 mpp pins or group of pins and a mpp function common to all pins.
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
H A Dmarvell,orion-pinctrl.txt1 * Marvell Orion SoC pinctrl driver for mpp
13 contiguous MPP registers, and the second one describing the single
14 final MPP register, separated from the previous one.
16 Available mpp pins/groups and functions:
17 Note: brackets (x) are not part of the mpp name for marvell,function and given
H A Dmarvell,dove-pinctrl.txt1 * Marvell Dove SoC pinctrl driver for mpp
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
12 Note: brackets (x) are not part of the mpp name for marvell,function and given
H A Dmarvell,armada-375-pinctrl.txt1 * Marvell Armada 375 SoC pinctrl driver for mpp
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
11 Note: brackets (x) are not part of the mpp name for marvell,function and given
H A Dmarvell,armada-xp-pinctrl.txt1 * Marvell Armada XP SoC pinctrl driver for mpp
9 - reg: register specifier of MPP registers
13 Available mpp pins/groups and functions:
14 Note: brackets (x) are not part of the mpp name for marvell,function and given
H A Dmarvell,armada-370-pinctrl.txt1 * Marvell Armada 370 SoC pinctrl driver for mpp
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
11 Note: brackets (x) are not part of the mpp name for marvell,function and given
/openbmc/linux/arch/arm/plat-orion/
H A Dmpp.c2 * arch/arm/plat-orion/mpp.c
4 * MPP functions for Marvell orion SoCs
17 #include <plat/mpp.h>
19 /* Address of the ith MPP control register */
34 printk(KERN_DEBUG "initial MPP regs:"); in orion_mpp_conf()
52 printk(KERN_ERR "orion_mpp_conf: invalid MPP " in orion_mpp_conf()
58 "orion_mpp_conf: requested MPP%u config " in orion_mpp_conf()
76 printk(KERN_DEBUG " final MPP regs:"); in orion_mpp_conf()
/openbmc/u-boot/arch/arm/mach-kirkwood/
H A Dmpp.c2 * arch/arm/mach-kirkwood/mpp.c
4 * MPP functions for Marvell Kirkwood SoCs
16 #include <asm/arch/mpp.h>
26 debug("MPP setup: unknown kirkwood variant\n"); in kirkwood_variant()
44 debug( "initial MPP regs:"); in kirkwood_mpp_conf()
59 debug("kirkwood_mpp_conf: invalid MPP " in kirkwood_mpp_conf()
64 debug("kirkwood_mpp_conf: requested MPP%u config " in kirkwood_mpp_conf()
83 debug(" final MPP regs:"); in kirkwood_mpp_conf()
/openbmc/linux/arch/arm/plat-orion/include/plat/
H A Dmpp.h2 * arch/arm/plat-orion/include/plat/mpp.h
4 * Marvell Orion SoC MPP handling.
17 /* This is the generic MPP macro, without any variant information.
19 bit fields indicating which MPP configurations are valid for a
23 /* MPP number */ ((_num) & 0xff) | \
24 /* MPP select value */ (((_sel) & 0xf) << 8) | \
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-spmi-mpp.c20 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
41 /* mpp peripheral type and subtype values */
106 * struct pmic_mpp_pad - keep current MPP settings
108 * @is_enabled: Set to false when MPP should be put in high Z state.
110 * @output_enabled: Set to true if MPP output logic is enabled.
111 * @input_enabled: Set to true if MPP input buffer logic is enabled.
114 * @num_sources: Number of power-sources supported by this MPP.
526 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); in pmic_mpp_config_dbg_show()
679 dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n", in pmic_mpp_populate()
730 dev_err(state->dev, "unknown MPP direction\n"); in pmic_mpp_populate()
[all …]
H A Dpinctrl-ssbi-mpp.c22 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
27 /* MPP registers */
31 /* MPP Type: type */
96 * @paired: mpp operates in paired mode
97 * @output_value: logical output value of the mpp
549 "1v25", "1v25_2", "0v625", "0v3125", "mpp", "abus1", "abus2", in pm8xxx_mpp_dbg_show_one()
558 seq_printf(s, " mpp%-2d:", offset + PM8XXX_MPP_PHYSICAL_OFFSET); in pm8xxx_mpp_dbg_show_one()
795 .name = "ssbi-mpp",
807 { .compatible = "qcom,pm8018-mpp", .data = (void *) 6 },
808 { .compatible = "qcom,pm8038-mpp", .data = (void *) 6 },
[all …]
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.h13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
33 * @mpp_get: (optional) special function to get mpp setting
34 * @mpp_set: (optional) special function to set mpp setting
40 * between two or more different settings, e.g. assign mpp pin 13 to
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
69 * A ctrl_setting describes a specific internal mux function that a mpp pin
71 * register for common mpp pin configuration registers on MVEBU. SoC specific
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dorion5x-rd88f5182-nas.dts130 * MPP[20] PCI Clock to MV88F5182
131 * MPP[21] PCI Clock to mini PCI CON11
132 * MPP[22] USB 0 over current indication
133 * MPP[23] USB 1 over current indication
134 * MPP[24] USB 1 over current enable
135 * MPP[25] USB 0 over current enable
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dmarvell,mvebu-pinctrl.txt2 pins (mpp) to a specific function.
5 mpp pins or group of pins and a mpp function common to all pins.
39 /* MPP Bus:
61 /* MPP Bus:
97 /* MPP Bus:
H A Dmarvell,armada-cp110-pinctrl.txt2 Function 0x0 for any MPP ID activates GPIO pin mode
3 Function 0xc for any MPP ID activates DEBUG_BUS pin mode
5 MPP# 0x1 0x2 0x3 0x4
72 MPP# 0x5 0x6 0x7
139 MPP# 0x8 0x9 0xA
206 MPP# 0xB 0xD 0xE
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_sys_env_lib.c67 /* Initialize MPP for GPIO (set MPP = 0x0) */ in mv_ddr_sys_env_suspend_wakeup_check()
69 /* reset MPP21 to 0x0, keep rest of MPP settings*/ in mv_ddr_sys_env_suspend_wakeup_check()
/openbmc/u-boot/board/Synology/ds109/
H A Dopenocd.cfg105 mww 0xD0010000 0x01111111 ;# MPP 0 to 7
106 mww 0xD0010004 0x11113322 ;# MPP 8 to 15
107 mww 0xD0010008 0x00001111 ;# MPP 16 to 23

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