1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 25af244fdSMike Rapoport #ifndef __ARCH_DOVE_MPP_CODED_H 35af244fdSMike Rapoport #define __ARCH_DOVE_MPP_CODED_H 45af244fdSMike Rapoport 53cff484dSAndrew Lunn #define MPP(_num, _sel, _in, _out) ( \ 63cff484dSAndrew Lunn /* MPP number */ ((_num) & 0xff) | \ 73cff484dSAndrew Lunn /* MPP select value */ (((_sel) & 0xf) << 8) | \ 83cff484dSAndrew Lunn /* may be input signal */ ((!!(_in)) << 12) | \ 93cff484dSAndrew Lunn /* may be output signal */ ((!!(_out)) << 13)) 105af244fdSMike Rapoport 113cff484dSAndrew Lunn #define MPP0_GPIO0 MPP(0, 0x0, 1, 1) 123cff484dSAndrew Lunn #define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0) 133cff484dSAndrew Lunn #define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0) 143cff484dSAndrew Lunn #define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0) 155af244fdSMike Rapoport 163cff484dSAndrew Lunn #define MPP1_GPIO1 MPP(1, 0x0, 1, 1) 173cff484dSAndrew Lunn #define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0) 183cff484dSAndrew Lunn #define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0) 193cff484dSAndrew Lunn #define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0) 205af244fdSMike Rapoport 213cff484dSAndrew Lunn #define MPP2_GPIO2 MPP(2, 0x0, 1, 1) 223cff484dSAndrew Lunn #define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0) 233cff484dSAndrew Lunn #define MPP2_UA2_TXD MPP(2, 0x2, 0, 0) 243cff484dSAndrew Lunn #define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0) 253cff484dSAndrew Lunn #define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0) 265af244fdSMike Rapoport 273cff484dSAndrew Lunn #define MPP3_GPIO3 MPP(3, 0x0, 1, 1) 283cff484dSAndrew Lunn #define MPP3_SATA_ACT MPP(3, 0x1, 0, 0) 293cff484dSAndrew Lunn #define MPP3_UA2_RXD MPP(3, 0x2, 0, 0) 303cff484dSAndrew Lunn #define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0) 313cff484dSAndrew Lunn #define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0) 323cff484dSAndrew Lunn #define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0) 335af244fdSMike Rapoport 343cff484dSAndrew Lunn #define MPP4_GPIO4 MPP(4, 0x0, 1, 1) 353cff484dSAndrew Lunn #define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0) 363cff484dSAndrew Lunn #define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0) 373cff484dSAndrew Lunn #define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0) 385af244fdSMike Rapoport 393cff484dSAndrew Lunn #define MPP5_GPIO5 MPP(5, 0x0, 1, 1) 403cff484dSAndrew Lunn #define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0) 413cff484dSAndrew Lunn #define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0) 423cff484dSAndrew Lunn #define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0) 435af244fdSMike Rapoport 443cff484dSAndrew Lunn #define MPP6_GPIO6 MPP(6, 0x0, 1, 1) 453cff484dSAndrew Lunn #define MPP6_UA3_TXD MPP(6, 0x2, 0, 0) 463cff484dSAndrew Lunn #define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0) 473cff484dSAndrew Lunn #define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0) 485af244fdSMike Rapoport 493cff484dSAndrew Lunn #define MPP7_GPIO7 MPP(7, 0x0, 1, 1) 503cff484dSAndrew Lunn #define MPP7_UA3_RXD MPP(7, 0x2, 0, 0) 513cff484dSAndrew Lunn #define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0) 523cff484dSAndrew Lunn #define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0) 535af244fdSMike Rapoport 543cff484dSAndrew Lunn #define MPP8_GPIO8 MPP(8, 0x0, 1, 1) 553cff484dSAndrew Lunn #define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0) 565af244fdSMike Rapoport 573cff484dSAndrew Lunn #define MPP9_GPIO9 MPP(9, 0x0, 1, 1) 583cff484dSAndrew Lunn #define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0) 595af244fdSMike Rapoport 603cff484dSAndrew Lunn #define MPP10_GPIO10 MPP(10, 0x0, 1, 1) 613cff484dSAndrew Lunn #define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0) 625af244fdSMike Rapoport 633cff484dSAndrew Lunn #define MPP11_GPIO11 MPP(11, 0x0, 1, 1) 643cff484dSAndrew Lunn #define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0) 653cff484dSAndrew Lunn #define MPP11_SATA_ACT MPP(11, 0x2, 0, 0) 663cff484dSAndrew Lunn #define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0) 673cff484dSAndrew Lunn #define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0) 683cff484dSAndrew Lunn #define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0) 695af244fdSMike Rapoport 703cff484dSAndrew Lunn #define MPP12_GPIO12 MPP(12, 0x0, 1, 1) 713cff484dSAndrew Lunn #define MPP12_SATA_ACT MPP(12, 0x1, 0, 0) 723cff484dSAndrew Lunn #define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0) 733cff484dSAndrew Lunn #define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0) 743cff484dSAndrew Lunn #define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0) 755af244fdSMike Rapoport 763cff484dSAndrew Lunn #define MPP13_GPIO13 MPP(13, 0x0, 1, 1) 773cff484dSAndrew Lunn #define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0) 783cff484dSAndrew Lunn #define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0) 793cff484dSAndrew Lunn #define MPP13_SDIO1WP MPP(13, 0x4, 0, 0) 803cff484dSAndrew Lunn #define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0) 815af244fdSMike Rapoport 823cff484dSAndrew Lunn #define MPP14_GPIO14 MPP(14, 0x0, 1, 1) 833cff484dSAndrew Lunn #define MPP14_UA2_TXD MPP(14, 0x2, 0, 0) 843cff484dSAndrew Lunn #define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0) 853cff484dSAndrew Lunn #define MPP14_SSP_RXD MPP(14, 0x5, 0, 0) 865af244fdSMike Rapoport 873cff484dSAndrew Lunn #define MPP15_GPIO15 MPP(15, 0x0, 1, 1) 883cff484dSAndrew Lunn #define MPP15_UA2_RXD MPP(15, 0x2, 0, 0) 893cff484dSAndrew Lunn #define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0) 903cff484dSAndrew Lunn #define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0) 915af244fdSMike Rapoport 923cff484dSAndrew Lunn #define MPP16_GPIO16 MPP(16, 0x0, 1, 1) 933cff484dSAndrew Lunn #define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0) 943cff484dSAndrew Lunn #define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0) 953cff484dSAndrew Lunn #define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0) 963cff484dSAndrew Lunn #define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0) 975af244fdSMike Rapoport 983cff484dSAndrew Lunn #define MPP17_GPIO17 MPP(17, 0x0, 1, 1) 993cff484dSAndrew Lunn #define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0) 1003cff484dSAndrew Lunn #define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0) 1013cff484dSAndrew Lunn #define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0) 1023cff484dSAndrew Lunn #define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0) 1033cff484dSAndrew Lunn #define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0) 1045af244fdSMike Rapoport 1053cff484dSAndrew Lunn #define MPP18_GPIO18 MPP(18, 0x0, 1, 1) 1063cff484dSAndrew Lunn #define MPP18_UA3_TXD MPP(18, 0x2, 0, 0) 1073cff484dSAndrew Lunn #define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0) 1083cff484dSAndrew Lunn #define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0) 1093cff484dSAndrew Lunn #define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0) 1105af244fdSMike Rapoport 1113cff484dSAndrew Lunn #define MPP19_GPIO19 MPP(19, 0x0, 1, 1) 1123cff484dSAndrew Lunn #define MPP19_UA3_RXD MPP(19, 0x2, 0, 0) 1133cff484dSAndrew Lunn #define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0) 1143cff484dSAndrew Lunn #define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0) 1155af244fdSMike Rapoport 1163cff484dSAndrew Lunn #define MPP20_GPIO20 MPP(20, 0x0, 1, 1) 1173cff484dSAndrew Lunn #define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0) 1183cff484dSAndrew Lunn #define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0) 1193cff484dSAndrew Lunn #define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0) 1203cff484dSAndrew Lunn #define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0) 1213cff484dSAndrew Lunn #define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0) 1225af244fdSMike Rapoport 1233cff484dSAndrew Lunn #define MPP21_GPIO21 MPP(21, 0x0, 1, 1) 1243cff484dSAndrew Lunn #define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0) 1253cff484dSAndrew Lunn #define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0) 1263cff484dSAndrew Lunn #define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0) 1273cff484dSAndrew Lunn #define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0) 1283cff484dSAndrew Lunn #define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0) 1293cff484dSAndrew Lunn #define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0) 1305af244fdSMike Rapoport 1313cff484dSAndrew Lunn #define MPP22_GPIO22 MPP(22, 0x0, 1, 1) 1323cff484dSAndrew Lunn #define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0) 1333cff484dSAndrew Lunn #define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0) 1343cff484dSAndrew Lunn #define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0) 1353cff484dSAndrew Lunn #define MPP22_SSP_TXD MPP(22, 0x4, 0, 0) 1363cff484dSAndrew Lunn #define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0) 1373cff484dSAndrew Lunn #define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0) 1385af244fdSMike Rapoport 1393cff484dSAndrew Lunn #define MPP23_GPIO23 MPP(23, 0x0, 1, 1) 1403cff484dSAndrew Lunn #define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0) 1413cff484dSAndrew Lunn #define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0) 1423cff484dSAndrew Lunn #define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0) 1433cff484dSAndrew Lunn #define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0) 1443cff484dSAndrew Lunn #define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0) 1455af244fdSMike Rapoport 1463cff484dSAndrew Lunn #define MPP_MAX 23 1475af244fdSMike Rapoport 1483cff484dSAndrew Lunn #define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0) 1495af244fdSMike Rapoport 1505af244fdSMike Rapoport /* for MPP groups _num is a group index */ 1515af244fdSMike Rapoport enum dove_mpp_grp_idx { 1525af244fdSMike Rapoport MPP_24_39 = 2, 1535af244fdSMike Rapoport MPP_40_45 = 0, 1545af244fdSMike Rapoport MPP_46_51 = 1, 1555af244fdSMike Rapoport MPP_58_61 = 5, 1565af244fdSMike Rapoport MPP_62_63 = 4, 1573cff484dSAndrew Lunn MPP_GRP_MAX = 5, 1585af244fdSMike Rapoport }; 1595af244fdSMike Rapoport 1603cff484dSAndrew Lunn #define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1) 1613cff484dSAndrew Lunn #define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0) 1625af244fdSMike Rapoport 1633cff484dSAndrew Lunn #define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1) 1643cff484dSAndrew Lunn #define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0) 1655af244fdSMike Rapoport 1663cff484dSAndrew Lunn #define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1) 1673cff484dSAndrew Lunn #define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0) 1685af244fdSMike Rapoport 1693cff484dSAndrew Lunn #define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1) 1703cff484dSAndrew Lunn #define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0) 1715af244fdSMike Rapoport 1723cff484dSAndrew Lunn #define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1) 1733cff484dSAndrew Lunn #define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0) 1745af244fdSMike Rapoport 1755af244fdSMike Rapoport /* The MPP[64:71] control differs from other groups */ 1763cff484dSAndrew Lunn #define MPP_GRP_NFC_64_71_GPO 0x1 1773cff484dSAndrew Lunn #define MPP_GRP_NFC_64_71_NFC 0x0 1785af244fdSMike Rapoport 1795af244fdSMike Rapoport /* 1805af244fdSMike Rapoport * The MPP[52:57] functionality is encoded by 4 bits in different 1815af244fdSMike Rapoport * registers. The _num field in this case encodes those bits in 1825af244fdSMike Rapoport * correspodence with Table 135 of 88AP510 Functional specification 1835af244fdSMike Rapoport */ 1843cff484dSAndrew Lunn #define MPP_GRP_AU1_52_57_AU1 0x0 1853cff484dSAndrew Lunn #define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2 1863cff484dSAndrew Lunn #define MPP_GRP_AU1_52_57_GPIO 0xa 1873cff484dSAndrew Lunn #define MPP_GRP_AU1_52_57_TW_GPIO 0xb 1883cff484dSAndrew Lunn #define MPP_GRP_AU1_52_57_AU1_SSP 0xc 1893cff484dSAndrew Lunn #define MPP_GRP_AU1_52_57_SSP_GPIO 0xe 1903cff484dSAndrew Lunn #define MPP_GRP_AU1_52_57_SSP_TW 0xf 1915af244fdSMike Rapoport 1923cff484dSAndrew Lunn void dove_mpp_conf(unsigned int *mpp_list, 1933cff484dSAndrew Lunn unsigned int *mpp_grp_list, 1943cff484dSAndrew Lunn unsigned int grp_au1_52_57, 1953cff484dSAndrew Lunn unsigned int grp_nfc_64_71); 1965af244fdSMike Rapoport 1975af244fdSMike Rapoport #endif /* __ARCH_DOVE_MPP_CODED_H */ 198