| /openbmc/linux/arch/arm64/kernel/ |
| H A D | sleep.S | 10 * Implementation of MPIDR_EL1 hash algorithm through shifting
18 * @mpidr: register containing MPIDR_EL1 value
79 mrs x7, mpidr_el1
123 mrs x1, mpidr_el1
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| H A D | setup.c | 137 * An index can be created from the MPIDR_EL1 by isolating the in smp_build_mpidr_hash()
141 * the MPIDR_EL1 through shifting and ORing. It is a collision free in smp_build_mpidr_hash()
144 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. in smp_build_mpidr_hash()
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | macro.h | 109 mrs \xreg, mpidr_el1
131 mrs \xreg1, mpidr_el1
253 mrs \tmp, mpidr_el1
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| H A D | system.h | 174 asm volatile("mrs %0, mpidr_el1" : "=r" (val)); in read_mpidr()
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | lowlevel.S | 453 * MPIDR_EL1 Fields:
464 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
470 mrs x0, mpidr_el1
541 mrs x0, mpidr_el1
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| H A D | mp.c | 50 * mpidr_el1 register value of core which needs to be released in wake_secondary_core_n()
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | cpus.yaml | 69 and matches the MPIDR_EL1 register affinity bits.
74 bits [39:32] of MPIDR_EL1.
77 bits [23:0] of MPIDR_EL1.
82 of MPIDR_EL1.
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| /openbmc/u-boot/arch/arm/cpu/armv8/ |
| H A D | psci.S | 192 mrs x9, MPIDR_EL1
199 mrs x10, MPIDR_EL1
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | kvm_host.h | 291 MPIDR_EL1, /* MultiProcessor Affinity Register */ enumerator
812 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but in __vcpu_read_sys_reg_from_cpu()
814 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's in __vcpu_read_sys_reg_from_cpu()
857 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but in __vcpu_write_sys_reg_to_cpu()
1048 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); in kvm_init_host_cpu_context()
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| H A D | cputype.h | 294 return read_cpuid(MPIDR_EL1); in read_cpuid_mpidr()
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| H A D | el2_setup.h | 140 mrs x1, mpidr_el1
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| H A D | kvm_emulate.h | 468 return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; in kvm_vcpu_get_mpidr_aff()
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| /openbmc/libcper/specification/json/sections/ |
| H A D | cper-arm-processor.json | 503 "mpidr_el1",
522 "mpidr_el1": { "type": "integer" }, object
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| /openbmc/libcper/include/libcper/sections/ |
| H A D | cper-section-arm.h | 117 "mair_el1", "midr_el1", "mpidr_el1", "sctlr_el1", \
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| /openbmc/qemu/tests/tcg/aarch64/ |
| H A D | sysregs.c | 148 get_cpu_reg_check_mask(mpidr_el1, _m(0000,0000,8000,0000)); in main()
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| /openbmc/qemu/hw/arm/ |
| H A D | sbsa-ref.c | 245 * and matches the MPIDR_EL1 register affinity bits. in create_fdt()
250 * bits [39:32] of MPIDR_EL1. in create_fdt()
253 * bits [23:0] of MPIDR_EL1. in create_fdt()
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| H A D | raspi.c | 157 { 0xd53800a6 }, /* mrs x6, mpidr_el1 */ in write_smpboot64()
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| /openbmc/libcper/sections/ |
| H A D | cper-section-arm.c | 79 //Processor ID (MPIDR_EL1) and chip ID (MIDR_EL1). in cper_section_arm_to_ir()
81 uint64_t mpidr_eli1 = record->MPIDR_EL1; in cper_section_arm_to_ir()
605 section_cper.MPIDR_EL1 = json_object_get_uint64(obj); in ir_section_arm_to_cper()
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| /openbmc/u-boot/arch/arm/lib/ |
| H A D | gic_64.S | 82 mrs x10, mpidr_el1
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| /openbmc/linux/arch/arm64/kvm/hyp/include/hyp/ |
| H A D | sysreg-sr.h | 102 write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2); in __sysreg_restore_el1_state()
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| /openbmc/linux/tools/arch/arm64/include/asm/ |
| H A D | cputype.h | 273 return read_cpuid(MPIDR_EL1); in read_cpuid_mpidr()
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| /openbmc/linux/drivers/perf/hisilicon/ |
| H A D | hisi_uncore_sllc_pmu.c | 293 * while SCCL_ID is from MPIDR_EL1 by CPU. in hisi_sllc_pmu_init_data()
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| H A D | hisi_uncore_pmu.c | 419 * determined from the MPIDR_EL1, but the encoding varies by CPU:
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| /openbmc/libcper/include/libcper/ |
| H A D | Cper.h | 1389 UINT64 MPIDR_EL1; member
1597 UINT64 Mpidr_El1; member
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| /openbmc/qemu/target/arm/ |
| H A D | cpregs.h | 374 FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1)
714 DO_BIT(HFGRTR, MPIDR_EL1),
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