164580903SHongbo Zhang /*
264580903SHongbo Zhang * ARM SBSA Reference Platform emulation
364580903SHongbo Zhang *
464580903SHongbo Zhang * Copyright (c) 2018 Linaro Limited
5d40ab068SLeif Lindholm * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
664580903SHongbo Zhang * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
764580903SHongbo Zhang *
864580903SHongbo Zhang * This program is free software; you can redistribute it and/or modify it
964580903SHongbo Zhang * under the terms and conditions of the GNU General Public License,
1064580903SHongbo Zhang * version 2 or later, as published by the Free Software Foundation.
1164580903SHongbo Zhang *
1264580903SHongbo Zhang * This program is distributed in the hope it will be useful, but WITHOUT
1364580903SHongbo Zhang * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1464580903SHongbo Zhang * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1564580903SHongbo Zhang * more details.
1664580903SHongbo Zhang *
1764580903SHongbo Zhang * You should have received a copy of the GNU General Public License along with
1864580903SHongbo Zhang * this program. If not, see <http://www.gnu.org/licenses/>.
1964580903SHongbo Zhang */
2064580903SHongbo Zhang
2164580903SHongbo Zhang #include "qemu/osdep.h"
222c65db5eSPaolo Bonzini #include "qemu/datadir.h"
2364580903SHongbo Zhang #include "qapi/error.h"
2464580903SHongbo Zhang #include "qemu/error-report.h"
2564580903SHongbo Zhang #include "qemu/units.h"
26e9fdf453SHongbo Zhang #include "sysemu/device_tree.h"
2794522562SPhilippe Mathieu-Daudé #include "sysemu/kvm.h"
2864580903SHongbo Zhang #include "sysemu/numa.h"
2954d31236SMarkus Armbruster #include "sysemu/runstate.h"
3064580903SHongbo Zhang #include "sysemu/sysemu.h"
3164580903SHongbo Zhang #include "exec/hwaddr.h"
3264580903SHongbo Zhang #include "kvm_arm.h"
3364580903SHongbo Zhang #include "hw/arm/boot.h"
34d40ab068SLeif Lindholm #include "hw/arm/bsa.h"
350c08d4f3SMarcin Juszkiewicz #include "hw/arm/fdt.h"
36a431ab0eSRichard Henderson #include "hw/arm/smmuv3.h"
37e9fdf453SHongbo Zhang #include "hw/block/flash.h"
3864580903SHongbo Zhang #include "hw/boards.h"
39c6ff8bdeSBALATON Zoltan #include "hw/ide/ide-bus.h"
40fbb5945eSPhilippe Mathieu-Daudé #include "hw/ide/ahci-sysbus.h"
4164580903SHongbo Zhang #include "hw/intc/arm_gicv3_common.h"
420c40daf0SPhilippe Mathieu-Daudé #include "hw/intc/arm_gicv3_its_common.h"
43e9fdf453SHongbo Zhang #include "hw/loader.h"
44e9fdf453SHongbo Zhang #include "hw/pci-host/gpex.h"
45a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h"
46e9fdf453SHongbo Zhang #include "hw/usb.h"
4762c2b876SYuquan Wang #include "hw/usb/xhci.h"
48d8f6d15fSGavin Shan #include "hw/char/pl011.h"
49baabe7d0SShashi Mallela #include "hw/watchdog/sbsa_gwdt.h"
50e9fdf453SHongbo Zhang #include "net/net.h"
51d210fa2fSKevin Wolf #include "qapi/qmp/qlist.h"
52db1015e9SEduardo Habkost #include "qom/object.h"
53d780d056SPhilippe Mathieu-Daudé #include "target/arm/cpu-qom.h"
54f4f318b4SPhilippe Mathieu-Daudé #include "target/arm/gtimer.h"
5564580903SHongbo Zhang
5664580903SHongbo Zhang #define RAMLIMIT_GB 8192
5764580903SHongbo Zhang #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
5864580903SHongbo Zhang
59e9fdf453SHongbo Zhang #define NUM_IRQS 256
60e9fdf453SHongbo Zhang #define NUM_SMMU_IRQS 4
61e9fdf453SHongbo Zhang #define NUM_SATA_PORTS 6
62e9fdf453SHongbo Zhang
63ee4336f9SPeter Maydell /*
64ee4336f9SPeter Maydell * Generic timer frequency in Hz (which drives both the CPU generic timers
657edca16eSMarcin Juszkiewicz * and the SBSA watchdog-timer). Older (<2.11) versions of the TF-A firmware
667edca16eSMarcin Juszkiewicz * assumed 62.5MHz here.
67ee4336f9SPeter Maydell *
687edca16eSMarcin Juszkiewicz * Starting with Armv8.6 CPU 1GHz timer frequency is mandated.
69ee4336f9SPeter Maydell */
707edca16eSMarcin Juszkiewicz #define SBSA_GTIMER_HZ 1000000000
71ee4336f9SPeter Maydell
7264580903SHongbo Zhang enum {
7364580903SHongbo Zhang SBSA_FLASH,
7464580903SHongbo Zhang SBSA_MEM,
7564580903SHongbo Zhang SBSA_CPUPERIPHS,
7664580903SHongbo Zhang SBSA_GIC_DIST,
7764580903SHongbo Zhang SBSA_GIC_REDIST,
789fe2b4a2SShashi Mallela SBSA_GIC_ITS,
793f462bf0SGraeme Gregory SBSA_SECURE_EC,
8080d60a6dSEduardo Habkost SBSA_GWDT_WS0,
81baabe7d0SShashi Mallela SBSA_GWDT_REFRESH,
82baabe7d0SShashi Mallela SBSA_GWDT_CONTROL,
8364580903SHongbo Zhang SBSA_SMMU,
8464580903SHongbo Zhang SBSA_UART,
8564580903SHongbo Zhang SBSA_RTC,
8664580903SHongbo Zhang SBSA_PCIE,
8764580903SHongbo Zhang SBSA_PCIE_MMIO,
8864580903SHongbo Zhang SBSA_PCIE_MMIO_HIGH,
8964580903SHongbo Zhang SBSA_PCIE_PIO,
9064580903SHongbo Zhang SBSA_PCIE_ECAM,
9164580903SHongbo Zhang SBSA_GPIO,
9264580903SHongbo Zhang SBSA_SECURE_UART,
9364580903SHongbo Zhang SBSA_SECURE_UART_MM,
9464580903SHongbo Zhang SBSA_SECURE_MEM,
9564580903SHongbo Zhang SBSA_AHCI,
9662c2b876SYuquan Wang SBSA_XHCI,
9764580903SHongbo Zhang };
9864580903SHongbo Zhang
99db1015e9SEduardo Habkost struct SBSAMachineState {
10064580903SHongbo Zhang MachineState parent;
10164580903SHongbo Zhang struct arm_boot_info bootinfo;
10264580903SHongbo Zhang int smp_cpus;
10364580903SHongbo Zhang void *fdt;
10464580903SHongbo Zhang int fdt_size;
10564580903SHongbo Zhang int psci_conduit;
10648ba18e6SPhilippe Mathieu-Daudé DeviceState *gic;
107e9fdf453SHongbo Zhang PFlashCFI01 *flash[2];
108db1015e9SEduardo Habkost };
10964580903SHongbo Zhang
11064580903SHongbo Zhang #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
1118063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE)
11264580903SHongbo Zhang
11364580903SHongbo Zhang static const MemMapEntry sbsa_ref_memmap[] = {
11464580903SHongbo Zhang /* 512M boot ROM */
11564580903SHongbo Zhang [SBSA_FLASH] = { 0, 0x20000000 },
11664580903SHongbo Zhang /* 512M secure memory */
11764580903SHongbo Zhang [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 },
11864580903SHongbo Zhang /* Space reserved for CPU peripheral devices */
11964580903SHongbo Zhang [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
12064580903SHongbo Zhang [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
12164580903SHongbo Zhang [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
1229fe2b4a2SShashi Mallela [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 },
1233f462bf0SGraeme Gregory [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
124baabe7d0SShashi Mallela [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
125baabe7d0SShashi Mallela [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
12664580903SHongbo Zhang [SBSA_UART] = { 0x60000000, 0x00001000 },
12764580903SHongbo Zhang [SBSA_RTC] = { 0x60010000, 0x00001000 },
12864580903SHongbo Zhang [SBSA_GPIO] = { 0x60020000, 0x00001000 },
12964580903SHongbo Zhang [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 },
13064580903SHongbo Zhang [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 },
13164580903SHongbo Zhang [SBSA_SMMU] = { 0x60050000, 0x00020000 },
13264580903SHongbo Zhang /* Space here reserved for more SMMUs */
13364580903SHongbo Zhang [SBSA_AHCI] = { 0x60100000, 0x00010000 },
13462c2b876SYuquan Wang [SBSA_XHCI] = { 0x60110000, 0x00010000 },
13564580903SHongbo Zhang /* Space here reserved for other devices */
13664580903SHongbo Zhang [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
13764580903SHongbo Zhang /* 32-bit address PCIE MMIO space */
13864580903SHongbo Zhang [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 },
13964580903SHongbo Zhang /* 256M PCIE ECAM space */
14064580903SHongbo Zhang [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 },
14164580903SHongbo Zhang /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
14264580903SHongbo Zhang [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL },
14364580903SHongbo Zhang [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
14464580903SHongbo Zhang };
14564580903SHongbo Zhang
146e9fdf453SHongbo Zhang static const int sbsa_ref_irqmap[] = {
147e9fdf453SHongbo Zhang [SBSA_UART] = 1,
148e9fdf453SHongbo Zhang [SBSA_RTC] = 2,
149e9fdf453SHongbo Zhang [SBSA_PCIE] = 3, /* ... to 6 */
150e9fdf453SHongbo Zhang [SBSA_GPIO] = 7,
151e9fdf453SHongbo Zhang [SBSA_SECURE_UART] = 8,
152e9fdf453SHongbo Zhang [SBSA_SECURE_UART_MM] = 9,
153e9fdf453SHongbo Zhang [SBSA_AHCI] = 10,
15462c2b876SYuquan Wang [SBSA_XHCI] = 11,
15504788fd5SGraeme Gregory [SBSA_SMMU] = 12, /* ... to 15 */
15680d60a6dSEduardo Habkost [SBSA_GWDT_WS0] = 16,
157e9fdf453SHongbo Zhang };
158e9fdf453SHongbo Zhang
sbsa_ref_cpu_mp_affinity(SBSAMachineState * sms,int idx)159999f6ebdSLeif Lindholm static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
160999f6ebdSLeif Lindholm {
161999f6ebdSLeif Lindholm uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
162750245edSRichard Henderson return arm_build_mp_affinity(idx, clustersz);
163999f6ebdSLeif Lindholm }
164999f6ebdSLeif Lindholm
sbsa_fdt_add_gic_node(SBSAMachineState * sms)1650c08d4f3SMarcin Juszkiewicz static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
1660c08d4f3SMarcin Juszkiewicz {
1670c08d4f3SMarcin Juszkiewicz char *nodename;
1680c08d4f3SMarcin Juszkiewicz
1690c08d4f3SMarcin Juszkiewicz nodename = g_strdup_printf("/intc");
1700c08d4f3SMarcin Juszkiewicz qemu_fdt_add_subnode(sms->fdt, nodename);
1710c08d4f3SMarcin Juszkiewicz qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
1720c08d4f3SMarcin Juszkiewicz 2, sbsa_ref_memmap[SBSA_GIC_DIST].base,
1730c08d4f3SMarcin Juszkiewicz 2, sbsa_ref_memmap[SBSA_GIC_DIST].size,
1740c08d4f3SMarcin Juszkiewicz 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
1750c08d4f3SMarcin Juszkiewicz 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
1760c08d4f3SMarcin Juszkiewicz
1779fe2b4a2SShashi Mallela nodename = g_strdup_printf("/intc/its");
1789fe2b4a2SShashi Mallela qemu_fdt_add_subnode(sms->fdt, nodename);
1799fe2b4a2SShashi Mallela qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
1809fe2b4a2SShashi Mallela 2, sbsa_ref_memmap[SBSA_GIC_ITS].base,
1819fe2b4a2SShashi Mallela 2, sbsa_ref_memmap[SBSA_GIC_ITS].size);
1829fe2b4a2SShashi Mallela
1830c08d4f3SMarcin Juszkiewicz g_free(nodename);
1840c08d4f3SMarcin Juszkiewicz }
1859fe2b4a2SShashi Mallela
186e9fdf453SHongbo Zhang /*
187e9fdf453SHongbo Zhang * Firmware on this machine only uses ACPI table to load OS, these limited
188e9fdf453SHongbo Zhang * device tree nodes are just to let firmware know the info which varies from
189e9fdf453SHongbo Zhang * command line parameters, so it is not necessary to be fully compatible
190e9fdf453SHongbo Zhang * with the kernel CPU and NUMA binding rules.
191e9fdf453SHongbo Zhang */
create_fdt(SBSAMachineState * sms)192e9fdf453SHongbo Zhang static void create_fdt(SBSAMachineState *sms)
193e9fdf453SHongbo Zhang {
194e9fdf453SHongbo Zhang void *fdt = create_device_tree(&sms->fdt_size);
195e9fdf453SHongbo Zhang const MachineState *ms = MACHINE(sms);
196aa570207STao Xu int nb_numa_nodes = ms->numa_state->num_nodes;
197e9fdf453SHongbo Zhang int cpu;
198e9fdf453SHongbo Zhang
199e9fdf453SHongbo Zhang if (!fdt) {
200e9fdf453SHongbo Zhang error_report("create_device_tree() failed");
201e9fdf453SHongbo Zhang exit(1);
202e9fdf453SHongbo Zhang }
203e9fdf453SHongbo Zhang
204e9fdf453SHongbo Zhang sms->fdt = fdt;
205e9fdf453SHongbo Zhang
206e9fdf453SHongbo Zhang qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref");
207e9fdf453SHongbo Zhang qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
208e9fdf453SHongbo Zhang qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
209e9fdf453SHongbo Zhang
21090ea2cceSLeif Lindholm /*
21190ea2cceSLeif Lindholm * This versioning scheme is for informing platform fw only. It is neither:
21290ea2cceSLeif Lindholm * - A QEMU versioned machine type; a given version of QEMU will emulate
21390ea2cceSLeif Lindholm * a given version of the platform.
21490ea2cceSLeif Lindholm * - A reflection of level of SBSA (now SystemReady SR) support provided.
21590ea2cceSLeif Lindholm *
21690ea2cceSLeif Lindholm * machine-version-major: updated when changes breaking fw compatibility
21790ea2cceSLeif Lindholm * are introduced.
21890ea2cceSLeif Lindholm * machine-version-minor: updated when features are added that don't break
21990ea2cceSLeif Lindholm * fw compatibility.
22090ea2cceSLeif Lindholm */
22190ea2cceSLeif Lindholm qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
222*3b36ceadSXiong Yining qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 4);
22390ea2cceSLeif Lindholm
224118154b7STao Xu if (ms->numa_state->have_numa_distance) {
225e9fdf453SHongbo Zhang int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
226e9fdf453SHongbo Zhang uint32_t *matrix = g_malloc0(size);
227e9fdf453SHongbo Zhang int idx, i, j;
228e9fdf453SHongbo Zhang
229e9fdf453SHongbo Zhang for (i = 0; i < nb_numa_nodes; i++) {
230e9fdf453SHongbo Zhang for (j = 0; j < nb_numa_nodes; j++) {
231e9fdf453SHongbo Zhang idx = (i * nb_numa_nodes + j) * 3;
232e9fdf453SHongbo Zhang matrix[idx + 0] = cpu_to_be32(i);
233e9fdf453SHongbo Zhang matrix[idx + 1] = cpu_to_be32(j);
2347e721e7bSTao Xu matrix[idx + 2] =
2357e721e7bSTao Xu cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
236e9fdf453SHongbo Zhang }
237e9fdf453SHongbo Zhang }
238e9fdf453SHongbo Zhang
239e9fdf453SHongbo Zhang qemu_fdt_add_subnode(fdt, "/distance-map");
240e9fdf453SHongbo Zhang qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
241e9fdf453SHongbo Zhang matrix, size);
242e9fdf453SHongbo Zhang g_free(matrix);
243e9fdf453SHongbo Zhang }
244e9fdf453SHongbo Zhang
245999f6ebdSLeif Lindholm /*
246999f6ebdSLeif Lindholm * From Documentation/devicetree/bindings/arm/cpus.yaml
247999f6ebdSLeif Lindholm * On ARM v8 64-bit systems this property is required
248999f6ebdSLeif Lindholm * and matches the MPIDR_EL1 register affinity bits.
249999f6ebdSLeif Lindholm *
250999f6ebdSLeif Lindholm * * If cpus node's #address-cells property is set to 2
251999f6ebdSLeif Lindholm *
252999f6ebdSLeif Lindholm * The first reg cell bits [7:0] must be set to
253999f6ebdSLeif Lindholm * bits [39:32] of MPIDR_EL1.
254999f6ebdSLeif Lindholm *
255999f6ebdSLeif Lindholm * The second reg cell bits [23:0] must be set to
256999f6ebdSLeif Lindholm * bits [23:0] of MPIDR_EL1.
257999f6ebdSLeif Lindholm */
258e9fdf453SHongbo Zhang qemu_fdt_add_subnode(sms->fdt, "/cpus");
259999f6ebdSLeif Lindholm qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2);
260999f6ebdSLeif Lindholm qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0);
261e9fdf453SHongbo Zhang
262e9fdf453SHongbo Zhang for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
263e9fdf453SHongbo Zhang char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
264e9fdf453SHongbo Zhang ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
265e9fdf453SHongbo Zhang CPUState *cs = CPU(armcpu);
266999f6ebdSLeif Lindholm uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
267e9fdf453SHongbo Zhang
268e9fdf453SHongbo Zhang qemu_fdt_add_subnode(sms->fdt, nodename);
269999f6ebdSLeif Lindholm qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr);
270e9fdf453SHongbo Zhang
271e9fdf453SHongbo Zhang if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
272e9fdf453SHongbo Zhang qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id",
273e9fdf453SHongbo Zhang ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
274e9fdf453SHongbo Zhang }
275e9fdf453SHongbo Zhang
276e9fdf453SHongbo Zhang g_free(nodename);
277e9fdf453SHongbo Zhang }
2780c08d4f3SMarcin Juszkiewicz
279*3b36ceadSXiong Yining /* Add CPU topology description through fdt node topology. */
280*3b36ceadSXiong Yining qemu_fdt_add_subnode(sms->fdt, "/cpus/topology");
281*3b36ceadSXiong Yining
282*3b36ceadSXiong Yining qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "sockets", ms->smp.sockets);
283*3b36ceadSXiong Yining qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "clusters", ms->smp.clusters);
284*3b36ceadSXiong Yining qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "cores", ms->smp.cores);
285*3b36ceadSXiong Yining qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "threads", ms->smp.threads);
286*3b36ceadSXiong Yining
2870c08d4f3SMarcin Juszkiewicz sbsa_fdt_add_gic_node(sms);
288e9fdf453SHongbo Zhang }
289e9fdf453SHongbo Zhang
290e9fdf453SHongbo Zhang #define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
291e9fdf453SHongbo Zhang
sbsa_flash_create1(SBSAMachineState * sms,const char * name,const char * alias_prop_name)292e9fdf453SHongbo Zhang static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
293e9fdf453SHongbo Zhang const char *name,
294e9fdf453SHongbo Zhang const char *alias_prop_name)
295e9fdf453SHongbo Zhang {
296e9fdf453SHongbo Zhang /*
297e9fdf453SHongbo Zhang * Create a single flash device. We use the same parameters as
298e9fdf453SHongbo Zhang * the flash devices on the Versatile Express board.
299e9fdf453SHongbo Zhang */
300df707969SMarkus Armbruster DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
301e9fdf453SHongbo Zhang
302e9fdf453SHongbo Zhang qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
303e9fdf453SHongbo Zhang qdev_prop_set_uint8(dev, "width", 4);
304e9fdf453SHongbo Zhang qdev_prop_set_uint8(dev, "device-width", 2);
305e9fdf453SHongbo Zhang qdev_prop_set_bit(dev, "big-endian", false);
306e9fdf453SHongbo Zhang qdev_prop_set_uint16(dev, "id0", 0x89);
307e9fdf453SHongbo Zhang qdev_prop_set_uint16(dev, "id1", 0x18);
308e9fdf453SHongbo Zhang qdev_prop_set_uint16(dev, "id2", 0x00);
309e9fdf453SHongbo Zhang qdev_prop_set_uint16(dev, "id3", 0x00);
310e9fdf453SHongbo Zhang qdev_prop_set_string(dev, "name", name);
311d2623129SMarkus Armbruster object_property_add_child(OBJECT(sms), name, OBJECT(dev));
312e9fdf453SHongbo Zhang object_property_add_alias(OBJECT(sms), alias_prop_name,
313d2623129SMarkus Armbruster OBJECT(dev), "drive");
314e9fdf453SHongbo Zhang return PFLASH_CFI01(dev);
315e9fdf453SHongbo Zhang }
316e9fdf453SHongbo Zhang
sbsa_flash_create(SBSAMachineState * sms)317e9fdf453SHongbo Zhang static void sbsa_flash_create(SBSAMachineState *sms)
318e9fdf453SHongbo Zhang {
319e9fdf453SHongbo Zhang sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0");
320e9fdf453SHongbo Zhang sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1");
321e9fdf453SHongbo Zhang }
322e9fdf453SHongbo Zhang
sbsa_flash_map1(PFlashCFI01 * flash,hwaddr base,hwaddr size,MemoryRegion * sysmem)323e9fdf453SHongbo Zhang static void sbsa_flash_map1(PFlashCFI01 *flash,
324e9fdf453SHongbo Zhang hwaddr base, hwaddr size,
325e9fdf453SHongbo Zhang MemoryRegion *sysmem)
326e9fdf453SHongbo Zhang {
327e9fdf453SHongbo Zhang DeviceState *dev = DEVICE(flash);
328e9fdf453SHongbo Zhang
3294cdd0a77SPhilippe Mathieu-Daudé assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE));
330e9fdf453SHongbo Zhang assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
331e9fdf453SHongbo Zhang qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
3323c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
333e9fdf453SHongbo Zhang
334e9fdf453SHongbo Zhang memory_region_add_subregion(sysmem, base,
335e9fdf453SHongbo Zhang sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
336e9fdf453SHongbo Zhang 0));
337e9fdf453SHongbo Zhang }
338e9fdf453SHongbo Zhang
sbsa_flash_map(SBSAMachineState * sms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)339e9fdf453SHongbo Zhang static void sbsa_flash_map(SBSAMachineState *sms,
340e9fdf453SHongbo Zhang MemoryRegion *sysmem,
341e9fdf453SHongbo Zhang MemoryRegion *secure_sysmem)
342e9fdf453SHongbo Zhang {
343e9fdf453SHongbo Zhang /*
344e9fdf453SHongbo Zhang * Map two flash devices to fill the SBSA_FLASH space in the memmap.
345e9fdf453SHongbo Zhang * sysmem is the system memory space. secure_sysmem is the secure view
346e9fdf453SHongbo Zhang * of the system, and the first flash device should be made visible only
347e9fdf453SHongbo Zhang * there. The second flash device is visible to both secure and nonsecure.
348e9fdf453SHongbo Zhang */
349e9fdf453SHongbo Zhang hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
350e9fdf453SHongbo Zhang hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
351e9fdf453SHongbo Zhang
352e9fdf453SHongbo Zhang sbsa_flash_map1(sms->flash[0], flashbase, flashsize,
353e9fdf453SHongbo Zhang secure_sysmem);
354e9fdf453SHongbo Zhang sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize,
355e9fdf453SHongbo Zhang sysmem);
356e9fdf453SHongbo Zhang }
357e9fdf453SHongbo Zhang
sbsa_firmware_init(SBSAMachineState * sms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)358e9fdf453SHongbo Zhang static bool sbsa_firmware_init(SBSAMachineState *sms,
359e9fdf453SHongbo Zhang MemoryRegion *sysmem,
360e9fdf453SHongbo Zhang MemoryRegion *secure_sysmem)
361e9fdf453SHongbo Zhang {
3620ad3b5d3SPaolo Bonzini const char *bios_name;
363e9fdf453SHongbo Zhang int i;
364e9fdf453SHongbo Zhang BlockBackend *pflash_blk0;
365e9fdf453SHongbo Zhang
366e9fdf453SHongbo Zhang /* Map legacy -drive if=pflash to machine properties */
367e9fdf453SHongbo Zhang for (i = 0; i < ARRAY_SIZE(sms->flash); i++) {
368e9fdf453SHongbo Zhang pflash_cfi01_legacy_drive(sms->flash[i],
369e9fdf453SHongbo Zhang drive_get(IF_PFLASH, 0, i));
370e9fdf453SHongbo Zhang }
371e9fdf453SHongbo Zhang
372e9fdf453SHongbo Zhang sbsa_flash_map(sms, sysmem, secure_sysmem);
373e9fdf453SHongbo Zhang
374e9fdf453SHongbo Zhang pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
375e9fdf453SHongbo Zhang
3760ad3b5d3SPaolo Bonzini bios_name = MACHINE(sms)->firmware;
377e9fdf453SHongbo Zhang if (bios_name) {
378e9fdf453SHongbo Zhang char *fname;
379e9fdf453SHongbo Zhang MemoryRegion *mr;
380e9fdf453SHongbo Zhang int image_size;
381e9fdf453SHongbo Zhang
382e9fdf453SHongbo Zhang if (pflash_blk0) {
383e9fdf453SHongbo Zhang error_report("The contents of the first flash device may be "
384e9fdf453SHongbo Zhang "specified with -bios or with -drive if=pflash... "
385e9fdf453SHongbo Zhang "but you cannot use both options at once");
386e9fdf453SHongbo Zhang exit(1);
387e9fdf453SHongbo Zhang }
388e9fdf453SHongbo Zhang
389e9fdf453SHongbo Zhang /* Fall back to -bios */
390e9fdf453SHongbo Zhang
391e9fdf453SHongbo Zhang fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
392e9fdf453SHongbo Zhang if (!fname) {
393e9fdf453SHongbo Zhang error_report("Could not find ROM image '%s'", bios_name);
394e9fdf453SHongbo Zhang exit(1);
395e9fdf453SHongbo Zhang }
396e9fdf453SHongbo Zhang mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0);
397e9fdf453SHongbo Zhang image_size = load_image_mr(fname, mr);
398e9fdf453SHongbo Zhang g_free(fname);
399e9fdf453SHongbo Zhang if (image_size < 0) {
400e9fdf453SHongbo Zhang error_report("Could not load ROM image '%s'", bios_name);
401e9fdf453SHongbo Zhang exit(1);
402e9fdf453SHongbo Zhang }
403e9fdf453SHongbo Zhang }
404e9fdf453SHongbo Zhang
405e9fdf453SHongbo Zhang return pflash_blk0 || bios_name;
406e9fdf453SHongbo Zhang }
407e9fdf453SHongbo Zhang
create_secure_ram(SBSAMachineState * sms,MemoryRegion * secure_sysmem)408e9fdf453SHongbo Zhang static void create_secure_ram(SBSAMachineState *sms,
409e9fdf453SHongbo Zhang MemoryRegion *secure_sysmem)
410e9fdf453SHongbo Zhang {
411e9fdf453SHongbo Zhang MemoryRegion *secram = g_new(MemoryRegion, 1);
412e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base;
413e9fdf453SHongbo Zhang hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size;
414e9fdf453SHongbo Zhang
415e9fdf453SHongbo Zhang memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size,
416e9fdf453SHongbo Zhang &error_fatal);
417e9fdf453SHongbo Zhang memory_region_add_subregion(secure_sysmem, base, secram);
418e9fdf453SHongbo Zhang }
419e9fdf453SHongbo Zhang
create_its(SBSAMachineState * sms)4209fe2b4a2SShashi Mallela static void create_its(SBSAMachineState *sms)
4219fe2b4a2SShashi Mallela {
4229fe2b4a2SShashi Mallela const char *itsclass = its_class_name();
4239fe2b4a2SShashi Mallela DeviceState *dev;
4249fe2b4a2SShashi Mallela
4259fe2b4a2SShashi Mallela dev = qdev_new(itsclass);
4269fe2b4a2SShashi Mallela
4279fe2b4a2SShashi Mallela object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
4289fe2b4a2SShashi Mallela &error_abort);
4299fe2b4a2SShashi Mallela sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
4309fe2b4a2SShashi Mallela sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
4319fe2b4a2SShashi Mallela }
4329fe2b4a2SShashi Mallela
create_gic(SBSAMachineState * sms,MemoryRegion * mem)4339fe2b4a2SShashi Mallela static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
434e9fdf453SHongbo Zhang {
435cc7d44c2SLike Xu unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
436e9fdf453SHongbo Zhang SysBusDevice *gicbusdev;
437e9fdf453SHongbo Zhang const char *gictype;
438e9fdf453SHongbo Zhang uint32_t redist0_capacity, redist0_count;
439d210fa2fSKevin Wolf QList *redist_region_count;
440e9fdf453SHongbo Zhang int i;
441e9fdf453SHongbo Zhang
442e9fdf453SHongbo Zhang gictype = gicv3_class_name();
443e9fdf453SHongbo Zhang
4443e80f690SMarkus Armbruster sms->gic = qdev_new(gictype);
44548ba18e6SPhilippe Mathieu-Daudé qdev_prop_set_uint32(sms->gic, "revision", 3);
44648ba18e6SPhilippe Mathieu-Daudé qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
447e9fdf453SHongbo Zhang /*
448e9fdf453SHongbo Zhang * Note that the num-irq property counts both internal and external
449e9fdf453SHongbo Zhang * interrupts; there are always 32 of the former (mandated by GIC spec).
450e9fdf453SHongbo Zhang */
45148ba18e6SPhilippe Mathieu-Daudé qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32);
45248ba18e6SPhilippe Mathieu-Daudé qdev_prop_set_bit(sms->gic, "has-security-extensions", true);
453e9fdf453SHongbo Zhang
454e9fdf453SHongbo Zhang redist0_capacity =
455e9fdf453SHongbo Zhang sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
456e9fdf453SHongbo Zhang redist0_count = MIN(smp_cpus, redist0_capacity);
457e9fdf453SHongbo Zhang
458d210fa2fSKevin Wolf redist_region_count = qlist_new();
459d210fa2fSKevin Wolf qlist_append_int(redist_region_count, redist0_count);
460d210fa2fSKevin Wolf qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count);
461e9fdf453SHongbo Zhang
4629fe2b4a2SShashi Mallela object_property_set_link(OBJECT(sms->gic), "sysmem",
4639fe2b4a2SShashi Mallela OBJECT(mem), &error_fatal);
4649fe2b4a2SShashi Mallela qdev_prop_set_bit(sms->gic, "has-lpi", true);
4659fe2b4a2SShashi Mallela
46648ba18e6SPhilippe Mathieu-Daudé gicbusdev = SYS_BUS_DEVICE(sms->gic);
4673c6ef471SMarkus Armbruster sysbus_realize_and_unref(gicbusdev, &error_fatal);
468e9fdf453SHongbo Zhang sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
469e9fdf453SHongbo Zhang sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
470e9fdf453SHongbo Zhang
471e9fdf453SHongbo Zhang /*
472e9fdf453SHongbo Zhang * Wire the outputs from each CPU's generic timer and the GICv3
473e9fdf453SHongbo Zhang * maintenance interrupt signal to the appropriate GIC PPI inputs,
474e9fdf453SHongbo Zhang * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
475e9fdf453SHongbo Zhang */
476e9fdf453SHongbo Zhang for (i = 0; i < smp_cpus; i++) {
477e9fdf453SHongbo Zhang DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
478d40ab068SLeif Lindholm int intidbase = NUM_IRQS + i * GIC_INTERNAL;
479e9fdf453SHongbo Zhang int irq;
480e9fdf453SHongbo Zhang /*
481e9fdf453SHongbo Zhang * Mapping from the output timer irq lines from the CPU to the
482e9fdf453SHongbo Zhang * GIC PPI inputs used for this board.
483e9fdf453SHongbo Zhang */
484e9fdf453SHongbo Zhang const int timer_irq[] = {
485e9fdf453SHongbo Zhang [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
486e9fdf453SHongbo Zhang [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
487e9fdf453SHongbo Zhang [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
488e9fdf453SHongbo Zhang [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
489058262e0SMarcin Juszkiewicz [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
490e9fdf453SHongbo Zhang };
491e9fdf453SHongbo Zhang
492e9fdf453SHongbo Zhang for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
493e9fdf453SHongbo Zhang qdev_connect_gpio_out(cpudev, irq,
49448ba18e6SPhilippe Mathieu-Daudé qdev_get_gpio_in(sms->gic,
495d40ab068SLeif Lindholm intidbase + timer_irq[irq]));
496e9fdf453SHongbo Zhang }
497e9fdf453SHongbo Zhang
498e9fdf453SHongbo Zhang qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
499d40ab068SLeif Lindholm qdev_get_gpio_in(sms->gic,
500d40ab068SLeif Lindholm intidbase
501e9fdf453SHongbo Zhang + ARCH_GIC_MAINT_IRQ));
502d40ab068SLeif Lindholm
503e9fdf453SHongbo Zhang qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
504d40ab068SLeif Lindholm qdev_get_gpio_in(sms->gic,
505d40ab068SLeif Lindholm intidbase
506e9fdf453SHongbo Zhang + VIRTUAL_PMU_IRQ));
507e9fdf453SHongbo Zhang
508e9fdf453SHongbo Zhang sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
509e9fdf453SHongbo Zhang sysbus_connect_irq(gicbusdev, i + smp_cpus,
510e9fdf453SHongbo Zhang qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
511e9fdf453SHongbo Zhang sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
512e9fdf453SHongbo Zhang qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
513e9fdf453SHongbo Zhang sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
514e9fdf453SHongbo Zhang qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
515e9fdf453SHongbo Zhang }
5169fe2b4a2SShashi Mallela create_its(sms);
517e9fdf453SHongbo Zhang }
518e9fdf453SHongbo Zhang
create_uart(const SBSAMachineState * sms,int uart,MemoryRegion * mem,Chardev * chr)51948ba18e6SPhilippe Mathieu-Daudé static void create_uart(const SBSAMachineState *sms, int uart,
520e9fdf453SHongbo Zhang MemoryRegion *mem, Chardev *chr)
521e9fdf453SHongbo Zhang {
522e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[uart].base;
523e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[uart];
5243e80f690SMarkus Armbruster DeviceState *dev = qdev_new(TYPE_PL011);
525e9fdf453SHongbo Zhang SysBusDevice *s = SYS_BUS_DEVICE(dev);
526e9fdf453SHongbo Zhang
527e9fdf453SHongbo Zhang qdev_prop_set_chr(dev, "chardev", chr);
5283c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
529e9fdf453SHongbo Zhang memory_region_add_subregion(mem, base,
530e9fdf453SHongbo Zhang sysbus_mmio_get_region(s, 0));
53148ba18e6SPhilippe Mathieu-Daudé sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
532e9fdf453SHongbo Zhang }
533e9fdf453SHongbo Zhang
create_rtc(const SBSAMachineState * sms)53448ba18e6SPhilippe Mathieu-Daudé static void create_rtc(const SBSAMachineState *sms)
535e9fdf453SHongbo Zhang {
536e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
537e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[SBSA_RTC];
538e9fdf453SHongbo Zhang
53948ba18e6SPhilippe Mathieu-Daudé sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
540e9fdf453SHongbo Zhang }
541e9fdf453SHongbo Zhang
create_wdt(const SBSAMachineState * sms)542baabe7d0SShashi Mallela static void create_wdt(const SBSAMachineState *sms)
543baabe7d0SShashi Mallela {
544baabe7d0SShashi Mallela hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base;
545baabe7d0SShashi Mallela hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base;
546baabe7d0SShashi Mallela DeviceState *dev = qdev_new(TYPE_WDT_SBSA);
547baabe7d0SShashi Mallela SysBusDevice *s = SYS_BUS_DEVICE(dev);
54880d60a6dSEduardo Habkost int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
549baabe7d0SShashi Mallela
55088c756bcSPeter Maydell qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ);
551baabe7d0SShashi Mallela sysbus_realize_and_unref(s, &error_fatal);
552baabe7d0SShashi Mallela sysbus_mmio_map(s, 0, rbase);
553baabe7d0SShashi Mallela sysbus_mmio_map(s, 1, cbase);
554baabe7d0SShashi Mallela sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
555baabe7d0SShashi Mallela }
556baabe7d0SShashi Mallela
557e9fdf453SHongbo Zhang static DeviceState *gpio_key_dev;
sbsa_ref_powerdown_req(Notifier * n,void * opaque)558e9fdf453SHongbo Zhang static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
559e9fdf453SHongbo Zhang {
560e9fdf453SHongbo Zhang /* use gpio Pin 3 for power button event */
561e9fdf453SHongbo Zhang qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
562e9fdf453SHongbo Zhang }
563e9fdf453SHongbo Zhang
564e9fdf453SHongbo Zhang static Notifier sbsa_ref_powerdown_notifier = {
565e9fdf453SHongbo Zhang .notify = sbsa_ref_powerdown_req
566e9fdf453SHongbo Zhang };
567e9fdf453SHongbo Zhang
create_gpio(const SBSAMachineState * sms)56848ba18e6SPhilippe Mathieu-Daudé static void create_gpio(const SBSAMachineState *sms)
569e9fdf453SHongbo Zhang {
570e9fdf453SHongbo Zhang DeviceState *pl061_dev;
571e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
572e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[SBSA_GPIO];
573e9fdf453SHongbo Zhang
57448ba18e6SPhilippe Mathieu-Daudé pl061_dev = sysbus_create_simple("pl061", base,
57548ba18e6SPhilippe Mathieu-Daudé qdev_get_gpio_in(sms->gic, irq));
576e9fdf453SHongbo Zhang
577e9fdf453SHongbo Zhang gpio_key_dev = sysbus_create_simple("gpio-key", -1,
578e9fdf453SHongbo Zhang qdev_get_gpio_in(pl061_dev, 3));
579e9fdf453SHongbo Zhang
580e9fdf453SHongbo Zhang /* connect powerdown request */
581e9fdf453SHongbo Zhang qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
582e9fdf453SHongbo Zhang }
583e9fdf453SHongbo Zhang
create_ahci(const SBSAMachineState * sms)58448ba18e6SPhilippe Mathieu-Daudé static void create_ahci(const SBSAMachineState *sms)
585e9fdf453SHongbo Zhang {
586e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
587e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[SBSA_AHCI];
588e9fdf453SHongbo Zhang DeviceState *dev;
589e9fdf453SHongbo Zhang DriveInfo *hd[NUM_SATA_PORTS];
590e9fdf453SHongbo Zhang SysbusAHCIState *sysahci;
591e9fdf453SHongbo Zhang
5923e80f690SMarkus Armbruster dev = qdev_new("sysbus-ahci");
593e9fdf453SHongbo Zhang qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
5943c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
595e9fdf453SHongbo Zhang sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
59648ba18e6SPhilippe Mathieu-Daudé sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
597e9fdf453SHongbo Zhang
598e9fdf453SHongbo Zhang sysahci = SYSBUS_AHCI(dev);
599e9fdf453SHongbo Zhang ide_drive_get(hd, ARRAY_SIZE(hd));
60072c9d945SPhilippe Mathieu-Daudé ahci_ide_create_devs(&sysahci->ahci, hd);
601e9fdf453SHongbo Zhang }
602e9fdf453SHongbo Zhang
create_xhci(const SBSAMachineState * sms)60362c2b876SYuquan Wang static void create_xhci(const SBSAMachineState *sms)
604e9fdf453SHongbo Zhang {
60562c2b876SYuquan Wang hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
60662c2b876SYuquan Wang int irq = sbsa_ref_irqmap[SBSA_XHCI];
60762c2b876SYuquan Wang DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
608e65ecb66SYuquan Wang qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
609e9fdf453SHongbo Zhang
61062c2b876SYuquan Wang sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
61162c2b876SYuquan Wang sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
61262c2b876SYuquan Wang sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
613e9fdf453SHongbo Zhang }
614e9fdf453SHongbo Zhang
create_smmu(const SBSAMachineState * sms,PCIBus * bus)61548ba18e6SPhilippe Mathieu-Daudé static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
616e9fdf453SHongbo Zhang {
617e9fdf453SHongbo Zhang hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
618e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[SBSA_SMMU];
619e9fdf453SHongbo Zhang DeviceState *dev;
620e9fdf453SHongbo Zhang int i;
621e9fdf453SHongbo Zhang
622a431ab0eSRichard Henderson dev = qdev_new(TYPE_ARM_SMMUV3);
623e9fdf453SHongbo Zhang
6245325cc34SMarkus Armbruster object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
625e9fdf453SHongbo Zhang &error_abort);
6263c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
627e9fdf453SHongbo Zhang sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
628e9fdf453SHongbo Zhang for (i = 0; i < NUM_SMMU_IRQS; i++) {
62948ba18e6SPhilippe Mathieu-Daudé sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
630b8bf3472SGraeme Gregory qdev_get_gpio_in(sms->gic, irq + i));
631e9fdf453SHongbo Zhang }
632e9fdf453SHongbo Zhang }
633e9fdf453SHongbo Zhang
create_pcie(SBSAMachineState * sms)63448ba18e6SPhilippe Mathieu-Daudé static void create_pcie(SBSAMachineState *sms)
635e9fdf453SHongbo Zhang {
636e9fdf453SHongbo Zhang hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
637e9fdf453SHongbo Zhang hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
638e9fdf453SHongbo Zhang hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
639e9fdf453SHongbo Zhang hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
640e9fdf453SHongbo Zhang hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
641e9fdf453SHongbo Zhang hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
642e9fdf453SHongbo Zhang hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
643e9fdf453SHongbo Zhang int irq = sbsa_ref_irqmap[SBSA_PCIE];
644611eda59SThomas Huth MachineClass *mc = MACHINE_GET_CLASS(sms);
645e9fdf453SHongbo Zhang MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
646e9fdf453SHongbo Zhang MemoryRegion *ecam_alias, *ecam_reg;
647e9fdf453SHongbo Zhang DeviceState *dev;
648e9fdf453SHongbo Zhang PCIHostState *pci;
649e9fdf453SHongbo Zhang int i;
650e9fdf453SHongbo Zhang
6513e80f690SMarkus Armbruster dev = qdev_new(TYPE_GPEX_HOST);
6523c6ef471SMarkus Armbruster sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
653e9fdf453SHongbo Zhang
654e9fdf453SHongbo Zhang /* Map ECAM space */
655e9fdf453SHongbo Zhang ecam_alias = g_new0(MemoryRegion, 1);
656e9fdf453SHongbo Zhang ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
657e9fdf453SHongbo Zhang memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
658e9fdf453SHongbo Zhang ecam_reg, 0, size_ecam);
659e9fdf453SHongbo Zhang memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
660e9fdf453SHongbo Zhang
661e9fdf453SHongbo Zhang /* Map the MMIO space */
662e9fdf453SHongbo Zhang mmio_alias = g_new0(MemoryRegion, 1);
663e9fdf453SHongbo Zhang mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
664e9fdf453SHongbo Zhang memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
665e9fdf453SHongbo Zhang mmio_reg, base_mmio, size_mmio);
666e9fdf453SHongbo Zhang memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
667e9fdf453SHongbo Zhang
668e9fdf453SHongbo Zhang /* Map the MMIO_HIGH space */
669e9fdf453SHongbo Zhang mmio_alias_high = g_new0(MemoryRegion, 1);
670e9fdf453SHongbo Zhang memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
671e9fdf453SHongbo Zhang mmio_reg, base_mmio_high, size_mmio_high);
672e9fdf453SHongbo Zhang memory_region_add_subregion(get_system_memory(), base_mmio_high,
673e9fdf453SHongbo Zhang mmio_alias_high);
674e9fdf453SHongbo Zhang
675e9fdf453SHongbo Zhang /* Map IO port space */
676e9fdf453SHongbo Zhang sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
677e9fdf453SHongbo Zhang
678e9fdf453SHongbo Zhang for (i = 0; i < GPEX_NUM_IRQS; i++) {
67948ba18e6SPhilippe Mathieu-Daudé sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
680870f0051SGraeme Gregory qdev_get_gpio_in(sms->gic, irq + i));
681e9fdf453SHongbo Zhang gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
682e9fdf453SHongbo Zhang }
683e9fdf453SHongbo Zhang
684e9fdf453SHongbo Zhang pci = PCI_HOST_BRIDGE(dev);
6855306ff73SMarcin Juszkiewicz
6860e45d0ebSDavid Woodhouse pci_init_nic_devices(pci->bus, mc->default_nic);
687e9fdf453SHongbo Zhang
6889162ac6bSMarcin Juszkiewicz pci_create_simple(pci->bus, -1, "bochs-display");
689e9fdf453SHongbo Zhang
69048ba18e6SPhilippe Mathieu-Daudé create_smmu(sms, pci->bus);
691e9fdf453SHongbo Zhang }
692e9fdf453SHongbo Zhang
sbsa_ref_dtb(const struct arm_boot_info * binfo,int * fdt_size)693e9fdf453SHongbo Zhang static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
694e9fdf453SHongbo Zhang {
695e9fdf453SHongbo Zhang const SBSAMachineState *board = container_of(binfo, SBSAMachineState,
696e9fdf453SHongbo Zhang bootinfo);
697e9fdf453SHongbo Zhang
698e9fdf453SHongbo Zhang *fdt_size = board->fdt_size;
699e9fdf453SHongbo Zhang return board->fdt;
700e9fdf453SHongbo Zhang }
701e9fdf453SHongbo Zhang
create_secure_ec(MemoryRegion * mem)7023f462bf0SGraeme Gregory static void create_secure_ec(MemoryRegion *mem)
7033f462bf0SGraeme Gregory {
7043f462bf0SGraeme Gregory hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base;
7053f462bf0SGraeme Gregory DeviceState *dev = qdev_new("sbsa-ec");
7063f462bf0SGraeme Gregory SysBusDevice *s = SYS_BUS_DEVICE(dev);
7073f462bf0SGraeme Gregory
7083f462bf0SGraeme Gregory memory_region_add_subregion(mem, base,
7093f462bf0SGraeme Gregory sysbus_mmio_get_region(s, 0));
7103f462bf0SGraeme Gregory }
7113f462bf0SGraeme Gregory
sbsa_ref_init(MachineState * machine)71264580903SHongbo Zhang static void sbsa_ref_init(MachineState *machine)
71364580903SHongbo Zhang {
714cc7d44c2SLike Xu unsigned int smp_cpus = machine->smp.cpus;
715cc7d44c2SLike Xu unsigned int max_cpus = machine->smp.max_cpus;
71664580903SHongbo Zhang SBSAMachineState *sms = SBSA_MACHINE(machine);
71764580903SHongbo Zhang MachineClass *mc = MACHINE_GET_CLASS(machine);
71864580903SHongbo Zhang MemoryRegion *sysmem = get_system_memory();
719c8ead571SPeter Maydell MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1);
720e9fdf453SHongbo Zhang bool firmware_loaded;
72164580903SHongbo Zhang const CPUArchIdList *possible_cpus;
72264580903SHongbo Zhang int n, sbsa_max_cpus;
72364580903SHongbo Zhang
72464580903SHongbo Zhang if (kvm_enabled()) {
72564580903SHongbo Zhang error_report("sbsa-ref: KVM is not supported for this machine");
72664580903SHongbo Zhang exit(1);
72764580903SHongbo Zhang }
72864580903SHongbo Zhang
72964580903SHongbo Zhang /*
730e9fdf453SHongbo Zhang * The Secure view of the world is the same as the NonSecure,
731e9fdf453SHongbo Zhang * but with a few extra devices. Create it as a container region
732e9fdf453SHongbo Zhang * containing the system memory at low priority; any secure-only
733e9fdf453SHongbo Zhang * devices go in at higher priority and take precedence.
734e9fdf453SHongbo Zhang */
735e9fdf453SHongbo Zhang memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
736e9fdf453SHongbo Zhang UINT64_MAX);
737e9fdf453SHongbo Zhang memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
738e9fdf453SHongbo Zhang
739c8ead571SPeter Maydell firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem);
740e9fdf453SHongbo Zhang
741e9fdf453SHongbo Zhang /*
74264580903SHongbo Zhang * This machine has EL3 enabled, external firmware should supply PSCI
74364580903SHongbo Zhang * implementation, so the QEMU's internal PSCI is disabled.
74464580903SHongbo Zhang */
74564580903SHongbo Zhang sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
74664580903SHongbo Zhang
74764580903SHongbo Zhang sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
74864580903SHongbo Zhang
74964580903SHongbo Zhang if (max_cpus > sbsa_max_cpus) {
75064580903SHongbo Zhang error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
75164580903SHongbo Zhang "supported by machine 'sbsa-ref' (%d)",
75264580903SHongbo Zhang max_cpus, sbsa_max_cpus);
75364580903SHongbo Zhang exit(1);
75464580903SHongbo Zhang }
75564580903SHongbo Zhang
75664580903SHongbo Zhang sms->smp_cpus = smp_cpus;
75764580903SHongbo Zhang
75864580903SHongbo Zhang if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
75964580903SHongbo Zhang error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
76064580903SHongbo Zhang exit(1);
76164580903SHongbo Zhang }
76264580903SHongbo Zhang
76364580903SHongbo Zhang possible_cpus = mc->possible_cpu_arch_ids(machine);
76464580903SHongbo Zhang for (n = 0; n < possible_cpus->len; n++) {
76564580903SHongbo Zhang Object *cpuobj;
76664580903SHongbo Zhang CPUState *cs;
76764580903SHongbo Zhang
76864580903SHongbo Zhang if (n >= smp_cpus) {
76964580903SHongbo Zhang break;
77064580903SHongbo Zhang }
77164580903SHongbo Zhang
77264580903SHongbo Zhang cpuobj = object_new(possible_cpus->cpus[n].type);
7735325cc34SMarkus Armbruster object_property_set_int(cpuobj, "mp-affinity",
7745325cc34SMarkus Armbruster possible_cpus->cpus[n].arch_id, NULL);
77564580903SHongbo Zhang
77664580903SHongbo Zhang cs = CPU(cpuobj);
77764580903SHongbo Zhang cs->cpu_index = n;
77864580903SHongbo Zhang
77964580903SHongbo Zhang numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
78064580903SHongbo Zhang &error_fatal);
78164580903SHongbo Zhang
782efba1595SDaniel P. Berrangé if (object_property_find(cpuobj, "reset-cbar")) {
7835325cc34SMarkus Armbruster object_property_set_int(cpuobj, "reset-cbar",
78464580903SHongbo Zhang sbsa_ref_memmap[SBSA_CPUPERIPHS].base,
7855325cc34SMarkus Armbruster &error_abort);
78664580903SHongbo Zhang }
78764580903SHongbo Zhang
788ee4336f9SPeter Maydell object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort);
789ee4336f9SPeter Maydell
7905325cc34SMarkus Armbruster object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
79164580903SHongbo Zhang &error_abort);
79264580903SHongbo Zhang
7935325cc34SMarkus Armbruster object_property_set_link(cpuobj, "secure-memory",
7945325cc34SMarkus Armbruster OBJECT(secure_sysmem), &error_abort);
79564580903SHongbo Zhang
796ce189ab2SMarkus Armbruster qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
79764580903SHongbo Zhang object_unref(cpuobj);
79864580903SHongbo Zhang }
79964580903SHongbo Zhang
8003818ed92SIgor Mammedov memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base,
8013818ed92SIgor Mammedov machine->ram);
80264580903SHongbo Zhang
803e9fdf453SHongbo Zhang create_fdt(sms);
804e9fdf453SHongbo Zhang
805e9fdf453SHongbo Zhang create_secure_ram(sms, secure_sysmem);
806e9fdf453SHongbo Zhang
8079fe2b4a2SShashi Mallela create_gic(sms, sysmem);
808e9fdf453SHongbo Zhang
80948ba18e6SPhilippe Mathieu-Daudé create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
81048ba18e6SPhilippe Mathieu-Daudé create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
811e9fdf453SHongbo Zhang /* Second secure UART for RAS and MM from EL0 */
81248ba18e6SPhilippe Mathieu-Daudé create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
813e9fdf453SHongbo Zhang
81448ba18e6SPhilippe Mathieu-Daudé create_rtc(sms);
815e9fdf453SHongbo Zhang
816baabe7d0SShashi Mallela create_wdt(sms);
817baabe7d0SShashi Mallela
81848ba18e6SPhilippe Mathieu-Daudé create_gpio(sms);
819e9fdf453SHongbo Zhang
82048ba18e6SPhilippe Mathieu-Daudé create_ahci(sms);
821e9fdf453SHongbo Zhang
82262c2b876SYuquan Wang create_xhci(sms);
823e9fdf453SHongbo Zhang
82448ba18e6SPhilippe Mathieu-Daudé create_pcie(sms);
825e9fdf453SHongbo Zhang
8263f462bf0SGraeme Gregory create_secure_ec(secure_sysmem);
8273f462bf0SGraeme Gregory
82864580903SHongbo Zhang sms->bootinfo.ram_size = machine->ram_size;
82964580903SHongbo Zhang sms->bootinfo.board_id = -1;
83064580903SHongbo Zhang sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
831e9fdf453SHongbo Zhang sms->bootinfo.get_dtb = sbsa_ref_dtb;
832e9fdf453SHongbo Zhang sms->bootinfo.firmware_loaded = firmware_loaded;
8332744ece8STao Xu arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo);
83464580903SHongbo Zhang }
83564580903SHongbo Zhang
sbsa_ref_possible_cpu_arch_ids(MachineState * ms)83664580903SHongbo Zhang static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
83764580903SHongbo Zhang {
838cc7d44c2SLike Xu unsigned int max_cpus = ms->smp.max_cpus;
83964580903SHongbo Zhang SBSAMachineState *sms = SBSA_MACHINE(ms);
84064580903SHongbo Zhang int n;
84164580903SHongbo Zhang
84264580903SHongbo Zhang if (ms->possible_cpus) {
84364580903SHongbo Zhang assert(ms->possible_cpus->len == max_cpus);
84464580903SHongbo Zhang return ms->possible_cpus;
84564580903SHongbo Zhang }
84664580903SHongbo Zhang
84764580903SHongbo Zhang ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
84864580903SHongbo Zhang sizeof(CPUArchId) * max_cpus);
84964580903SHongbo Zhang ms->possible_cpus->len = max_cpus;
85064580903SHongbo Zhang for (n = 0; n < ms->possible_cpus->len; n++) {
85164580903SHongbo Zhang ms->possible_cpus->cpus[n].type = ms->cpu_type;
85264580903SHongbo Zhang ms->possible_cpus->cpus[n].arch_id =
85364580903SHongbo Zhang sbsa_ref_cpu_mp_affinity(sms, n);
85464580903SHongbo Zhang ms->possible_cpus->cpus[n].props.has_thread_id = true;
85564580903SHongbo Zhang ms->possible_cpus->cpus[n].props.thread_id = n;
85664580903SHongbo Zhang }
85764580903SHongbo Zhang return ms->possible_cpus;
85864580903SHongbo Zhang }
85964580903SHongbo Zhang
86064580903SHongbo Zhang static CpuInstanceProperties
sbsa_ref_cpu_index_to_props(MachineState * ms,unsigned cpu_index)86164580903SHongbo Zhang sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
86264580903SHongbo Zhang {
86364580903SHongbo Zhang MachineClass *mc = MACHINE_GET_CLASS(ms);
86464580903SHongbo Zhang const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
86564580903SHongbo Zhang
86664580903SHongbo Zhang assert(cpu_index < possible_cpus->len);
86764580903SHongbo Zhang return possible_cpus->cpus[cpu_index].props;
86864580903SHongbo Zhang }
86964580903SHongbo Zhang
87064580903SHongbo Zhang static int64_t
sbsa_ref_get_default_cpu_node_id(const MachineState * ms,int idx)87164580903SHongbo Zhang sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
87264580903SHongbo Zhang {
873aa570207STao Xu return idx % ms->numa_state->num_nodes;
87464580903SHongbo Zhang }
87564580903SHongbo Zhang
sbsa_ref_instance_init(Object * obj)876e9fdf453SHongbo Zhang static void sbsa_ref_instance_init(Object *obj)
877e9fdf453SHongbo Zhang {
878e9fdf453SHongbo Zhang SBSAMachineState *sms = SBSA_MACHINE(obj);
879e9fdf453SHongbo Zhang
880e9fdf453SHongbo Zhang sbsa_flash_create(sms);
881e9fdf453SHongbo Zhang }
882e9fdf453SHongbo Zhang
sbsa_ref_class_init(ObjectClass * oc,void * data)88364580903SHongbo Zhang static void sbsa_ref_class_init(ObjectClass *oc, void *data)
88464580903SHongbo Zhang {
88564580903SHongbo Zhang MachineClass *mc = MACHINE_CLASS(oc);
886dbf8e8c4SGavin Shan static const char * const valid_cpu_types[] = {
887dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("cortex-a57"),
888dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("cortex-a72"),
889dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("neoverse-n1"),
890dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("neoverse-v1"),
891dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("neoverse-n2"),
892dbf8e8c4SGavin Shan ARM_CPU_TYPE_NAME("max"),
893dbf8e8c4SGavin Shan NULL,
894dbf8e8c4SGavin Shan };
89564580903SHongbo Zhang
89664580903SHongbo Zhang mc->init = sbsa_ref_init;
89764580903SHongbo Zhang mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
898b1d592e7SMarcin Juszkiewicz mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n2");
899dbf8e8c4SGavin Shan mc->valid_cpu_types = valid_cpu_types;
90064580903SHongbo Zhang mc->max_cpus = 512;
90164580903SHongbo Zhang mc->pci_allow_0_address = true;
90264580903SHongbo Zhang mc->minimum_page_bits = 12;
90364580903SHongbo Zhang mc->block_default_type = IF_IDE;
90464580903SHongbo Zhang mc->no_cdrom = 1;
905611eda59SThomas Huth mc->default_nic = "e1000e";
90664580903SHongbo Zhang mc->default_ram_size = 1 * GiB;
9073818ed92SIgor Mammedov mc->default_ram_id = "sbsa-ref.ram";
90864580903SHongbo Zhang mc->default_cpus = 4;
909*3b36ceadSXiong Yining mc->smp_props.clusters_supported = true;
91064580903SHongbo Zhang mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
91164580903SHongbo Zhang mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
91264580903SHongbo Zhang mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
913fecff672SGavin Shan /* platform instead of architectural choice */
914fecff672SGavin Shan mc->cpu_cluster_has_numa_boundary = true;
91564580903SHongbo Zhang }
91664580903SHongbo Zhang
91764580903SHongbo Zhang static const TypeInfo sbsa_ref_info = {
91864580903SHongbo Zhang .name = TYPE_SBSA_MACHINE,
91964580903SHongbo Zhang .parent = TYPE_MACHINE,
920e9fdf453SHongbo Zhang .instance_init = sbsa_ref_instance_init,
92164580903SHongbo Zhang .class_init = sbsa_ref_class_init,
92264580903SHongbo Zhang .instance_size = sizeof(SBSAMachineState),
92364580903SHongbo Zhang };
92464580903SHongbo Zhang
sbsa_ref_machine_init(void)92564580903SHongbo Zhang static void sbsa_ref_machine_init(void)
92664580903SHongbo Zhang {
92764580903SHongbo Zhang type_register_static(&sbsa_ref_info);
92864580903SHongbo Zhang }
92964580903SHongbo Zhang
93064580903SHongbo Zhang type_init(sbsa_ref_machine_init);
931