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/openbmc/u-boot/include/dt-bindings/memory/
H A Dmpc83xx-sdram.h63 #define CASLAT_20 0x3 /* CAS latency = 2.0 */
64 #define CASLAT_25 0x4 /* CAS latency = 2.5 */
65 #define CASLAT_30 0x5 /* CAS latency = 3.0 */
66 #define CASLAT_35 0x6 /* CAS latency = 3.5 */
67 #define CASLAT_40 0x7 /* CAS latency = 4.0 */
68 #define CASLAT_45 0x8 /* CAS latency = 4.5 */
69 #define CASLAT_50 0x9 /* CAS latency = 5.0 */
70 #define CASLAT_55 0xa /* CAS latency = 5.5 */
71 #define CASLAT_60 0xb /* CAS latency = 6.0 */
72 #define CASLAT_65 0xc /* CAS latency = 6.5 */
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/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsys_proto.h20 * Data RAM write latency: 2 cycles in configure_l2ctlr()
21 * Data RAM read latency: 2 cycles in configure_l2ctlr()
22 * Data RAM setup latency: 1 cycle in configure_l2ctlr()
23 * Tag RAM write latency: 1 cycle in configure_l2ctlr()
24 * Tag RAM read latency: 1 cycle in configure_l2ctlr()
25 * Tag RAM setup latency: 1 cycle in configure_l2ctlr()
/openbmc/u-boot/drivers/ddr/fsl/
H A Dlc_common_dimm_params.c31 /* compute the common CAS latency supported between slots */ in compute_cas_latency()
50 /* determine the acutal cas latency */ in compute_cas_latency()
52 /* check if the dimms support the CAS latency */ in compute_cas_latency()
58 * we must verify that this CAS latency value does not in compute_cas_latency()
63 printf("The chosen cas latency %d is too large\n", in compute_cas_latency()
91 * Compute a CAS latency suitable for all DIMMs in compute_cas_latency()
94 * CAS latency defined by all DIMMs. in compute_cas_latency()
98 * Step 1: find CAS latency common to all DIMMs using bitwise in compute_cas_latency()
124 * Step 2: check each common CAS latency against tCK of each in compute_cas_latency()
134 /* Check if this CAS latency will work on all DIMMs at tCK. */ in compute_cas_latency()
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H A Dddr2_dimm_params.c143 * CAS latency given the DRAM clock period. The SPD only
145 * frequency the DIMM runs at, the shorter its CAS latency can.
147 * it may be able to run at a CAS latency shorter than the
148 * shortest SPD-defined CAS latency.
150 * If a CAS latency is not found, 0 is returned.
160 * CAS latency de-rating based upon values JEDEC Standard No. 79-2C
/openbmc/qemu/tests/qemu-iotests/
H A D136114 latency = 0
116 latency += self.total_wr_ops * op_latency
118 latency += self.failed_wr_ops * op_latency
120 latency += self.total_rd_ops * op_latency
122 latency += self.failed_rd_ops * op_latency
124 latency += self.total_flush_ops * op_latency
125 return latency
164 # min read latency <= avg read latency <= max read latency
184 # min write latency <= avg write latency <= max write latency
202 # min flush latency <= avg flush latency <= max flush latency
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-imx8-ca53.dtsi27 entry-latency-us = <700>;
28 exit-latency-us = <250>;
36 entry-latency-us = <1000>;
37 exit-latency-us = <700>;
39 wakeup-latency-us = <1500>;
H A Duniphier-pro5.dtsi44 clock-latency-ns = <300>;
48 clock-latency-ns = <300>;
52 clock-latency-ns = <300>;
56 clock-latency-ns = <300>;
60 clock-latency-ns = <300>;
64 clock-latency-ns = <300>;
68 clock-latency-ns = <300>;
72 clock-latency-ns = <300>;
76 clock-latency-ns = <300>;
80 clock-latency-ns = <300>;
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H A Dsun8i-a33.dtsi56 clock-latency-ns = <244144>; /* 8 32k periods */
62 clock-latency-ns = <244144>; /* 8 32k periods */
68 clock-latency-ns = <244144>; /* 8 32k periods */
74 clock-latency-ns = <244144>; /* 8 32k periods */
80 clock-latency-ns = <244144>; /* 8 32k periods */
86 clock-latency-ns = <244144>; /* 8 32k periods */
92 clock-latency-ns = <244144>; /* 8 32k periods */
98 clock-latency-ns = <244144>; /* 8 32k periods */
104 clock-latency-ns = <244144>; /* 8 32k periods */
110 clock-latency-ns = <244144>; /* 8 32k periods */
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H A Duniphier-ld20.dtsi91 clock-latency-ns = <300>;
95 clock-latency-ns = <300>;
99 clock-latency-ns = <300>;
103 clock-latency-ns = <300>;
107 clock-latency-ns = <300>;
111 clock-latency-ns = <300>;
115 clock-latency-ns = <300>;
119 clock-latency-ns = <300>;
129 clock-latency-ns = <300>;
133 clock-latency-ns = <300>;
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H A Dsun8i-a83t.dtsi202 clock-latency-ns = <244144>; /* 8 32k periods */
208 clock-latency-ns = <244144>; /* 8 32k periods */
214 clock-latency-ns = <244144>; /* 8 32k periods */
220 clock-latency-ns = <244144>; /* 8 32k periods */
226 clock-latency-ns = <244144>; /* 8 32k periods */
232 clock-latency-ns = <244144>; /* 8 32k periods */
238 clock-latency-ns = <244144>; /* 8 32k periods */
244 clock-latency-ns = <244144>; /* 8 32k periods */
255 clock-latency-ns = <244144>; /* 8 32k periods */
261 clock-latency-ns = <244144>; /* 8 32k periods */
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/openbmc/u-boot/drivers/tpm/
H A Dtpm_tis_st33zp24_spi.c60 * Between command and response, there are latency byte (up to 15
66 * some latency byte before the answer is available (max 15).
73 int latency; member
132 memset(tx_buf + total_length, TPM_DUMMY_BYTE, phy->latency); in st33zp24_spi_write()
134 total_length += phy->latency; in st33zp24_spi_write()
178 phy->latency + tpm_size); in st33zp24_spi_read8_reg()
179 total_length += phy->latency + tpm_size; in st33zp24_spi_read8_reg()
222 int latency = 1, status = 0; in st33zp24_spi_evaluate_latency() local
226 while (!status && latency < MAX_SPI_LATENCY) { in st33zp24_spi_evaluate_latency()
227 phy->latency = latency; in st33zp24_spi_evaluate_latency()
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/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dumc-pxs2.c413 int latency; in umc_set_system_latency() local
416 latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT; in umc_set_system_latency()
417 latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >> in umc_set_system_latency()
421 * The LSB of latency is ignored in umc_set_system_latency()
423 latency += phy_latency & ~1; in umc_set_system_latency()
426 if (latency > 0xf) { in umc_set_system_latency()
428 val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT; in umc_set_system_latency()
430 val |= latency << UMC_RDATACTL_RADLTY_SHIFT; in umc_set_system_latency()
468 int latency; in umc_dc_init() local
495 latency = 12; in umc_dc_init()
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/openbmc/qemu/qapi/
H A Daudio.json142 # @latency: play buffer size (in microseconds)
151 '*latency': 'uint32'} }
193 # @latency: add extra latency to playback in microseconds (default
202 '*latency': 'uint32' } }
292 # where smaller number means smaller latency but higher CPU usage)
319 # @latency: latency you want PulseAudio to achieve in microseconds
329 '*latency': 'uint32' } }
363 # @latency: latency you want PipeWire to achieve in microseconds
373 '*latency': 'uint32' } }
H A Dblock.json514 # @block-latency-histogram-set:
516 # Manage read, write and flush latency histograms for the device.
518 # If only @id parameter is specified, remove all present latency
520 # latency histograms.
526 # latency histograms are removed, and empty ones created for all
531 # @boundaries-read: list of interval boundary values for read latency
532 # histogram. If specified, old read latency histogram is removed,
538 # latency histogram.
541 # write latency histogram.
544 # latency histogram.
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/openbmc/u-boot/arch/x86/include/asm/
H A Dsfi.h87 u32 latency; /* latency in ms */ member
96 u32 latency; /* transition latency in ms */ member
/openbmc/qemu/tests/functional/acpi-bits/bits-tests/
H A Dsmilatency.py231 """SMI latency test."""
41 # testsuite.add_test("SMI latency test", smi_latency);
42 # testsuite.add_test("SMI latency test with USB disabled via BIOS handoff", test_with_usb_disabl…
70 …testsuite.test("SMI latency < 150us to minimize risk of OS timeouts", max_latency / tsc_per_usec <…
84 …testsuite.print_detail("Summary of impact: observed maximum latency = {}".format(bits.format_tsc(m…
/openbmc/qemu/tests/qtest/
H A Dnuma-test.c398 " 'hierarchy': \"memory\", 'data-type': \"access-latency\" } }"))); in pc_hmat_build_cfg()
403 " 'hierarchy': \"memory\", 'data-type': \"access-latency\" } }"))); in pc_hmat_build_cfg()
408 " 'hierarchy': \"memory\", 'data-type': \"access-latency\" } }"))); in pc_hmat_build_cfg()
413 " 'hierarchy': \"memory\", 'data-type': \"write-latency\"," in pc_hmat_build_cfg()
418 " 'latency': 5 } }"))); in pc_hmat_build_cfg()
426 /* Configuring HMAT bandwidth and latency details */ in pc_hmat_build_cfg()
429 " 'hierarchy': \"memory\", 'data-type': \"access-latency\"," in pc_hmat_build_cfg()
430 " 'latency': 1 } }"))); /* 1 ns */ in pc_hmat_build_cfg()
433 " 'hierarchy': \"memory\", 'data-type': \"access-latency\"," in pc_hmat_build_cfg()
434 " 'latency': 5 } }"))); /* Fail: Duplicate configuration */ in pc_hmat_build_cfg()
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H A Dbios-tables-test.c1895 "data-type=access-latency,latency=1" in test_acpi_tcg_acpi_hmat()
1899 "data-type=access-latency,latency=65534" in test_acpi_tcg_acpi_hmat()
1950 "data-type=access-latency,latency=10" in test_acpi_aarch64_virt_tcg_acpi_hmat()
1954 "data-type=access-latency,latency=20" in test_acpi_aarch64_virt_tcg_acpi_hmat()
1958 "data-type=access-latency,latency=30" in test_acpi_aarch64_virt_tcg_acpi_hmat()
1962 "data-type=access-latency,latency=20" in test_acpi_aarch64_virt_tcg_acpi_hmat()
1966 "data-type=access-latency,latency=10" in test_acpi_aarch64_virt_tcg_acpi_hmat()
1970 "data-type=access-latency,latency=30" in test_acpi_aarch64_virt_tcg_acpi_hmat()
1999 "data-type=access-latency,latency=10" in test_acpi_q35_tcg_acpi_hmat_noinitiator()
2003 "data-type=access-latency,latency=20" in test_acpi_q35_tcg_acpi_hmat_noinitiator()
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/openbmc/u-boot/board/freescale/mx6memcal/
H A DKconfig181 int "Read additional latency"
185 Enter a latency in number of cycles. This will be added to
191 int "Write additional latency"
195 Enter a latency in number of cycles. This will be added to
/openbmc/openbmc/poky/meta-yocto-bsp/recipes-kernel/linux/files/
H A D0001-Revert-serial-8250_omap-Drop-pm_runtime_irq_safe.patch33 u32 latency;
42 - priv->latency = priv->calc_latency;
100 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
122 priv->latency = priv->calc_latency;
/openbmc/openbmc/poky/meta/recipes-rt/rt-tests/
H A Dhwlatdetect_git.bb1 SUMMARY = "Hardware latency detector"
2 DESCRIPTION = "Python utility for controlling the kernel hardware latency detection module (hwlat_d…
/openbmc/libpldm/tests/transport/
H A Dsend_recv_wrong_pldm_type.cpp24 .latency = in TEST()
41 .latency = in TEST()
H A Dsend_recv_unwanted.cpp24 .latency = in TEST()
41 .latency = in TEST()
H A Dsend_recv_wrong_command_code.cpp24 .latency = in TEST()
41 .latency = in TEST()
/openbmc/qemu/hw/core/
H A Dnuma.c253 /* Input latency data */ in parse_numa_hmat_lb()
256 error_setg(errp, "Missing 'latency' option"); in parse_numa_hmat_lb()
261 "the data type is latency"); in parse_numa_hmat_lb()
271 error_setg(errp, "Duplicate configuration of the latency for " in parse_numa_hmat_lb()
280 if (node->latency) { in parse_numa_hmat_lb()
281 /* Calculate the temporary base and compressed latency */ in parse_numa_hmat_lb()
282 max_entry = node->latency; in parse_numa_hmat_lb()
289 /* Calculate the max compressed latency */ in parse_numa_hmat_lb()
291 max_entry = node->latency / hmat_lb->base; in parse_numa_hmat_lb()
295 * For latency hmat_lb->range_bitmap record the max compressed in parse_numa_hmat_lb()
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