Searched +full:ls +full:- +full:bits (Results 1 – 25 of 40) sorted by relevance
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1 // SPDX-License-Identifier: GPL-2.0+13 * This defines the order of the pin mux control bits in the registers. For151 MUXCTL_NONE = -1,253 PUCTL_NONE = -1269 /* A normal pin group where the mux name and pull-up name match */273 /* A pin group where the pull-up name doesn't have a 1-1 mapping */389 PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),390 PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),391 PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),392 PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),[all …]
1 // SPDX-License-Identifier: GPL-2.0+14 #include <u-boot/rsa-mod-exp.h>34 /* This array contains DER value for SHA-256 */43 /* New Barker Code for LS ESBC Header */66 if (img->hdr.ie_flag & IE_FLAG_MASK) in check_ie()82 u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); in get_csf_base_addr()99 return -1; in get_csf_base_addr()113 u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); in get_csf_base_addr()117 return -1; in get_csf_base_addr()129 /* For LS-CH3, the address of IE Table is in get_ie_info_addr()[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */8 /* Place-holder for FDs, we represent it via the simplest form that we need for11 * routines (lots of read-modify-writes) would be worst-case performance whether20 /* offset in the MS 16 bits, BPID in the LS 16 bits */40 return (u64)((((uint64_t)fd->simple.addr_hi) << 32) in ldpaa_fd_get_addr()41 + fd->simple.addr_lo); in ldpaa_fd_get_addr()46 fd->simple.addr_hi = upper_32_bits(addr); in ldpaa_fd_set_addr()47 fd->simple.addr_lo = lower_32_bits(addr); in ldpaa_fd_set_addr()52 return fd->simple.len; in ldpaa_fd_get_len()57 fd->simple.len = len; in ldpaa_fd_set_len()[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */10 * control this QBMan instance, these values may simply be place-holders. The16 int irq_nrerr; /* Non-recoverable error interrupt line */20 * the user context. Ie. on MC, this information is likely to be true-physical,21 * and instantiated statically at compile-time. On GPP, this information is27 void *cena_bar; /* Cache-enabled portal register map */28 void *cinh_bar; /* Cache-inhibited portal register map */34 /* Place-holder for FDs, we represent it via the simplest form that we need for37 * routines (lots of read-modify-writes) would be worst-case performance whether40 * Note, as with all data-structures exchanged between software and hardware (be[all …]
1 // SPDX-License-Identifier: GPL-2.0+4 * Copyright 2014-2015 Freescale Semiconductor, Inc.27 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) in ls_pcie_next_lut_index()28 return pcie->next_lut_index++; in ls_pcie_next_lut_index()30 return -ENOSPC; /* LUT is full */ in ls_pcie_next_lut_index()33 /* returns the next available streamid for pcie, -errno if failed */39 return -EINVAL; in ls_pcie_next_streamid()47 if (pcie->big_endian) in lut_writel()48 out_be32(pcie->lut + offset, value); in lut_writel()50 out_le32(pcie->lut + offset, value); in lut_writel()[all …]
3 # SPDX-License-Identifier: GPL-2.0-only35 pager.communicate(hlp.encode('utf-8'))67 Dispatch to subcommand handler borrowed from combo-layer.94 usage: wic [--version] | [--help] | [COMMAND [ARGS]]102 overview wic overview - General overview of wic103 plugins wic plugins - Overview and API104 kickstart wic kickstart - wic kickstart reference118 usage: wic create <wks file or image name> [-o <DIRNAME> | --outdir <DIRNAME>]119 [-e | --image-name] [-s, --skip-build-check] [-D, --debug]120 [-r, --rootfs-dir] [-b, --bootimg-dir][all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */14 #include <fsl-mc/fsl_qbman_base.h>28 do {if (!(loopvar--)) BUG_ON(NULL == "DBG_POLL_CHECK"); } while (0)30 /* For CCSR or portal-CINH registers that contain fields at arbitrary offsets31 * and widths, these macro-generated encode/decode/isolate/remove inlines can34 * Eg. to "d"ecode a 14-bit field out of a register (into a "uint16_t" type),35 * where the field is located 3 bits "up" from the least-significant bit of the36 * register (ie. the field location within the 32-bit register corresponds to a40 * Or to "e"ncode a 1-bit boolean value (input type is "int", zero is FALSE,41 * non-zero is TRUE, so must convert all non-zero inputs to 1, hence the "!!"[all …]
8 // http://www.apache.org/licenses/LICENSE-2.078 // error = eventData2 bits [3:0] in biosMessageHook()81 // mode = eventData3 bits [3:0] in biosMessageHook()140 // post LSB = eventData2 bits [7:0] in biosMessageHook()142 // post MSB = eventData3 bits [7:0] in biosMessageHook()176 // Node ID = eventData2 bits [7:0] in biosMessageHook()208 // prior mode = eventData2 bits [3:0] in biosMessageHook()211 // selected mode = eventData3 bits [3:0] in biosMessageHook()348 // pair = eventData2 bits [7:4] in biosSMIMessageHook()350 // rank = eventData2 bits [1:0] in biosSMIMessageHook()[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */16 /* Minimum and maximum size of RSA signature length in bits */27 /* No-error return values */33 /* Different Header Struct for LS-CH3 */278 * This function is used to validate the main U-boot binary from280 * Architecture header (appended to U-boot image).
1 /* SPDX-License-Identifier: GPL-2.0 */3 * Copyright 2008-2014 Freescale Semiconductor, Inc.10 * Format from "JEDEC Standard No. 21-C,37 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */39 Clk @ CL=X-0.5 (tAC) */40 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */41 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */51 unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */59 unsigned char res_48_61[14]; /* 48-61 Reserved */61 unsigned char cksum; /* 63 Checksum for bytes 0-62 */[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright 2008-2014 Freescale Semiconductor, Inc.18 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))34 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))41 u32 ctpr_ms = sec_in32(&sec->ctpr_ms); in start_jr0()42 u32 scfgr = sec_in32(&sec->scfgr); in start_jr0()50 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); in start_jr0()54 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); in start_jr0()61 sec_out32(&sec->jrliodnr[0].ls, 0); in jr_reset_liodn()67 uint32_t jrcfg = sec_in32(®s->jrcfg1); in jr_disable_irq()[all …]
... -state >ls.file-type ! load-state >ls.file-size @ -1
... _ Yh Yh _(0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ 0123456789abcdefghijklmnopqrstuvwxyz load-state >ls.param @ load-state > ...
3 (c) Rebel.com, 1998-199935 fpa11->fType[Fn] = typeSingle; in loadSingle()36 /* FIXME - handle failure of get_user() */ in loadSingle()37 get_user_u32(float32_val(fpa11->fpreg[Fn].fSingle), addr); in loadSingle()45 p = (unsigned int*)&fpa11->fpreg[Fn].fDouble; in loadDouble()46 fpa11->fType[Fn] = typeDouble; in loadDouble()48 /* FIXME - handle failure of get_user() */ in loadDouble()52 /* FIXME - handle failure of get_user() */ in loadDouble()63 p = (unsigned int*)&fpa11->fpreg[Fn].fExtended; in loadExtended()64 fpa11->fType[Fn] = typeExtended; in loadExtended()[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */5 * Based on xHCI host controller driver in linux-kernel29 /* Max number of USB devices for any host controller - limit in section 6.1 */31 /* Section 5.3.3 - MaxPorts */40 * These bits are Read Only (RO) and should be saved and written to the42 * connect status, over-current status, port speed, and device removable.43 * connect status and port speed are also sticky - meaning they're in48 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:49 * bits 5:8, 9, 14:15, 25:2754 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:[all …]
163 return len(line) - len(line.lstrip(" "))186 … with the given example, if arg_num is -2 the 2nd parm to the left of the187 … "=" ("rc" in this case) should be returned. If arg_num is -1, the 1st189 … If arg_num is less than -2, an entire dictionary is returned. The keys190 to the dictionary for this example would be -2 and -1.235 'Programmer error - Variable "stack_frame_ix" has an'268 "Programmer error - The caller has asked for"296 line_ix = cur_line_no - source_line_num - 1299 line_ix = cur_line_no - source_line_num319 # work-around below for this deficiency.[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */3 * (C) Copyright 2014-2015 Freescale Semiconductor12 #include <asm/arch-fsl-layerscape/soc.h>17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>19 #include <asm/u-boot.h>88 /* Set Wuo bit for RN-I 20 */95 * Set forced-order mode in RNI-6, RNI-2097 * LS2080A family does not support setting forced-order mode,115 /* Add fully-coherent masters to DVM domain */121 /* Set all RN-I ports to QoS of 15 */[all …]
27 #include "hw/qdev-properties.h"43 /* OPB Master LS registers */70 #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */105 const char compat[] = "ibm,power8-lpc\0ibm,lpc"; in pnv_lpc_dt_xscom()120 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); in pnv_lpc_dt_xscom()121 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); in pnv_lpc_dt_xscom()130 const char compat[] = "ibm,power9-lpcm-opb\0simple-bus"; in pnv_dt_lpc()131 const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc"; in pnv_dt_lpc()163 name = g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr); in pnv_dt_lpc()169 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1))); in pnv_dt_lpc()[all …]
1 /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.6 University of Utah (pa-gdb-bugs@cs.utah.edu).22 #include "disas/dis-asm.h"24 /* HP PA-RISC SOM object file format: definitions internal to BFD.29 University of Utah (pa-gdb-bugs@cs.utah.edu).55 /* HP PA-RISC relocation types */159 relocation bits. These bits describe exactly where the caller has167 The high order 10 bits contain parameter relocation information,168 the low order 22 bits contain the constant offset. */173 ((((bfd_signed_vma)(a)) << (BFD_ARCH_SIZE-22)) >> (BFD_ARCH_SIZE-22))[all …]
4 * Copyright (c) 2004-2005 Jocelyn Mayer9 * SPDX-License-Identifier: LGPL-2.1-or-later15 * 1. MIPS Architecture for Programmers Volume II-B:20 * 2. MIPS Architecture For Programmers Volume II-A:126 /* PCREL Instructions perform PC-Relative address calculation. bits 20..16 */152 * These opcodes are distinguished only by bits 9..6; those bits are191 /* The following can be distinguished by their lower 6 bits. */204 * 1. MIPS Architecture for Programmers Volume II-B:209 * 2. MIPS Architecture for Programmers VolumeIV-e:210 * The MIPS DSP Application-Specific Extension[all …]
4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)12 - board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init13 - board/freescale/m54455evb/flash.c Atmel and INTEL flash support14 - board/freescale/m54455evb/Makefile Makefile15 - board/freescale/m54455evb/config.mk config make16 - board/freescale/m54455evb/u-boot.lds Linker description18 - common/cmd_bdinfo.c Clock frequencies output19 - common/cmd_mii.c mii support21 - arch/m68k/cpu/mcf5445x/cpu.c cpu specific code22 - arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs[all …]
4 * Copyright (c) 2003-2007 Jocelyn Mayer25 #include "cpu-models.h"43 pcc->pvr = _pvr; \44 pcc->svr = _svr; \45 dc->desc = _desc; \51 .parent = stringify(_type) "-family-" TYPE_POWERPC_CPU, \107 /* PowerPC 401/403/405 based set-top-box microcontrollers */125 POWERPC_DEF("440-xilinx", CPU_POWERPC_440_XILINX, 440x5,128 POWERPC_DEF("440-xilinx-w-dfpu", CPU_POWERPC_440_XILINX, 440x5wDFPU,194 /* MPC82xx family (aka PowerQUICC-II) */[all …]
1 drwxr-xr-x root root 4096 ./bin2 lrwxrwxrwx root root 19 ./bin/ash -> /bin/busybox.nosuid3 lrwxrwxrwx root root 25 ./bin/base64 -> /usr/bin/base64.coreutils4 -rwxr-xr-x root root 1190872 ./bin/bash.bash5 lrwxrwxrwx root root 14 ./bin/bash -> /bin/bash.bash6 lrwxrwxrwx root root 14 ./bin/busybox -> busybox.nosuid7 -rwxr-xr-x root root 613008 ./bin/busybox.nosuid8 -rwsr-xr-x root root 59440 ./bin/busybox.suid9 lrwxrwxrwx root root 18 ./bin/cat -> /bin/cat.coreutils10 -rwxr-xr-x root root 47336 ./bin/cat.coreutils[all …]
4 * Copyright (c) 2017-2018, IBM Corporation.6 * SPDX-License-Identifier: GPL-2.0-or-later17 #include "hw/qdev-properties.h"34 if (!(tctx->regs[cur_ring + TM_WORD2] & 0x80)) { in xive_ring_valid()87 return tctx->os_output; in xive_tctx_output()90 return tctx->hv_output; in xive_tctx_output()102 uint8_t *sig_regs = &tctx->regs[sig_ring]; in xive_tctx_accept()107 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0); in xive_tctx_accept()108 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); in xive_tctx_accept()109 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); in xive_tctx_accept()[all …]