1ed85a6e6SPeter Ujfalusi /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2ed85a6e6SPeter Ujfalusi /* 3ed85a6e6SPeter Ujfalusi * This file is provided under a dual BSD/GPLv2 license. When using or 4ed85a6e6SPeter Ujfalusi * redistributing this file, you may do so under either license. 5ed85a6e6SPeter Ujfalusi * 6ed85a6e6SPeter Ujfalusi * Copyright(c) 2022 Intel Corporation. All rights reserved. 7ed85a6e6SPeter Ujfalusi */ 8ed85a6e6SPeter Ujfalusi 9ed85a6e6SPeter Ujfalusi #ifndef __INCLUDE_SOUND_SOF_IPC4_HEADER_H__ 10ed85a6e6SPeter Ujfalusi #define __INCLUDE_SOUND_SOF_IPC4_HEADER_H__ 11ed85a6e6SPeter Ujfalusi 12ed85a6e6SPeter Ujfalusi #include <linux/types.h> 13ed85a6e6SPeter Ujfalusi #include <uapi/sound/sof/abi.h> 14ed85a6e6SPeter Ujfalusi 15ed85a6e6SPeter Ujfalusi /* maximum message size for mailbox Tx/Rx */ 16ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_MAX_SIZE 4096 17ed85a6e6SPeter Ujfalusi 18ed85a6e6SPeter Ujfalusi /** \addtogroup sof_uapi uAPI 19ed85a6e6SPeter Ujfalusi * SOF uAPI specification. 20ed85a6e6SPeter Ujfalusi * @{ 21ed85a6e6SPeter Ujfalusi */ 22ed85a6e6SPeter Ujfalusi 23ed85a6e6SPeter Ujfalusi /** 24ed85a6e6SPeter Ujfalusi * struct sof_ipc4_msg - Placeholder of an IPC4 message 25ed85a6e6SPeter Ujfalusi * @header_u64: IPC4 header as single u64 number 26ed85a6e6SPeter Ujfalusi * @primary: Primary, mandatory part of the header 27ed85a6e6SPeter Ujfalusi * @extension: Extended part of the header, if not used it should be 28ed85a6e6SPeter Ujfalusi * set to 0 29ed85a6e6SPeter Ujfalusi * @data_size: Size of data in bytes pointed by @data_ptr 30ed85a6e6SPeter Ujfalusi * @data_ptr: Pointer to the optional payload of a message 31ed85a6e6SPeter Ujfalusi */ 32ed85a6e6SPeter Ujfalusi struct sof_ipc4_msg { 33ed85a6e6SPeter Ujfalusi union { 34ed85a6e6SPeter Ujfalusi u64 header_u64; 35ed85a6e6SPeter Ujfalusi struct { 36ed85a6e6SPeter Ujfalusi u32 primary; 37ed85a6e6SPeter Ujfalusi u32 extension; 38ed85a6e6SPeter Ujfalusi }; 39ed85a6e6SPeter Ujfalusi }; 40ed85a6e6SPeter Ujfalusi 41ed85a6e6SPeter Ujfalusi size_t data_size; 42ed85a6e6SPeter Ujfalusi void *data_ptr; 43ed85a6e6SPeter Ujfalusi }; 44ed85a6e6SPeter Ujfalusi 45ed85a6e6SPeter Ujfalusi /** 46ed85a6e6SPeter Ujfalusi * struct sof_ipc4_tuple - Generic type/ID and parameter tuple 47ed85a6e6SPeter Ujfalusi * @type: type/ID 48ed85a6e6SPeter Ujfalusi * @size: size of the @value array in bytes 49ed85a6e6SPeter Ujfalusi * @value: value for the given type 50ed85a6e6SPeter Ujfalusi */ 51ed85a6e6SPeter Ujfalusi struct sof_ipc4_tuple { 52ed85a6e6SPeter Ujfalusi uint32_t type; 53ed85a6e6SPeter Ujfalusi uint32_t size; 54ed85a6e6SPeter Ujfalusi uint32_t value[]; 55ed85a6e6SPeter Ujfalusi } __packed; 56ed85a6e6SPeter Ujfalusi 57ed85a6e6SPeter Ujfalusi /* 58ed85a6e6SPeter Ujfalusi * IPC4 messages have two 32 bit identifier made up as follows :- 59ed85a6e6SPeter Ujfalusi * 60ed85a6e6SPeter Ujfalusi * header - msg type, msg id, msg direction ... 61ed85a6e6SPeter Ujfalusi * extension - extra params such as msg data size in mailbox 62ed85a6e6SPeter Ujfalusi * 63ed85a6e6SPeter Ujfalusi * These are sent at the start of the IPC message in the mailbox. Messages 64ed85a6e6SPeter Ujfalusi * should not be sent in the doorbell (special exceptions for firmware). 65ed85a6e6SPeter Ujfalusi */ 66ed85a6e6SPeter Ujfalusi 67ed85a6e6SPeter Ujfalusi /* 68ed85a6e6SPeter Ujfalusi * IPC4 primary header bit allocation for messages 69ed85a6e6SPeter Ujfalusi * bit 0-23: message type specific 70ed85a6e6SPeter Ujfalusi * bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG 71ed85a6e6SPeter Ujfalusi * enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG 72ed85a6e6SPeter Ujfalusi * bit 29: response - sof_ipc4_msg_dir 73ed85a6e6SPeter Ujfalusi * bit 30: target - enum sof_ipc4_msg_target 74ed85a6e6SPeter Ujfalusi * bit 31: reserved, unused 75ed85a6e6SPeter Ujfalusi */ 76ed85a6e6SPeter Ujfalusi 77ed85a6e6SPeter Ujfalusi /* Value of target field - must fit into 1 bit */ 78ed85a6e6SPeter Ujfalusi enum sof_ipc4_msg_target { 79ed85a6e6SPeter Ujfalusi /* Global FW message */ 80ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_GEN_MSG, 81ed85a6e6SPeter Ujfalusi 82ed85a6e6SPeter Ujfalusi /* Module message */ 83ed85a6e6SPeter Ujfalusi SOF_IPC4_MODULE_MSG 84ed85a6e6SPeter Ujfalusi }; 85ed85a6e6SPeter Ujfalusi 86ed85a6e6SPeter Ujfalusi /* Value of type field - must fit into 5 bits */ 87ed85a6e6SPeter Ujfalusi enum sof_ipc4_global_msg { 88ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_BOOT_CONFIG, 89ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_ROM_CONTROL, 90ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_IPCGATEWAY_CMD, 91ed85a6e6SPeter Ujfalusi 92ed85a6e6SPeter Ujfalusi /* 3 .. 12: RESERVED - do not use */ 93ed85a6e6SPeter Ujfalusi 94ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_PERF_MEASUREMENTS_CMD = 13, 95ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_CHAIN_DMA, 96ed85a6e6SPeter Ujfalusi 97ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_LOAD_MULTIPLE_MODULES, 98ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_UNLOAD_MULTIPLE_MODULES, 99ed85a6e6SPeter Ujfalusi 100ed85a6e6SPeter Ujfalusi /* pipeline settings */ 101ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_CREATE_PIPELINE, 102ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_DELETE_PIPELINE, 103ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_SET_PIPELINE_STATE, 104ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_GET_PIPELINE_STATE, 105ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_GET_PIPELINE_CONTEXT_SIZE, 106ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_SAVE_PIPELINE, 107ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_RESTORE_PIPELINE, 108ed85a6e6SPeter Ujfalusi 109ed85a6e6SPeter Ujfalusi /* Loads library (using Code Load or HD/A Host Output DMA) */ 110ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_LOAD_LIBRARY, 111ed85a6e6SPeter Ujfalusi 112ed85a6e6SPeter Ujfalusi /* 25: RESERVED - do not use */ 113ed85a6e6SPeter Ujfalusi 114ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_INTERNAL_MESSAGE = 26, 115ed85a6e6SPeter Ujfalusi 116ed85a6e6SPeter Ujfalusi /* Notification (FW to SW driver) */ 117ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_NOTIFICATION, 118ed85a6e6SPeter Ujfalusi 119ed85a6e6SPeter Ujfalusi /* 28 .. 31: RESERVED - do not use */ 120ed85a6e6SPeter Ujfalusi 121ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_TYPE_LAST, 122ed85a6e6SPeter Ujfalusi }; 123ed85a6e6SPeter Ujfalusi 124ed85a6e6SPeter Ujfalusi /* Value of response field - must fit into 1 bit */ 125ed85a6e6SPeter Ujfalusi enum sof_ipc4_msg_dir { 126ed85a6e6SPeter Ujfalusi SOF_IPC4_MSG_REQUEST, 127ed85a6e6SPeter Ujfalusi SOF_IPC4_MSG_REPLY, 128ed85a6e6SPeter Ujfalusi }; 129ed85a6e6SPeter Ujfalusi 130ed85a6e6SPeter Ujfalusi enum sof_ipc4_pipeline_state { 131ed85a6e6SPeter Ujfalusi SOF_IPC4_PIPE_INVALID_STATE, 132ed85a6e6SPeter Ujfalusi SOF_IPC4_PIPE_UNINITIALIZED, 133ed85a6e6SPeter Ujfalusi SOF_IPC4_PIPE_RESET, 134ed85a6e6SPeter Ujfalusi SOF_IPC4_PIPE_PAUSED, 135ed85a6e6SPeter Ujfalusi SOF_IPC4_PIPE_RUNNING, 136ed85a6e6SPeter Ujfalusi SOF_IPC4_PIPE_EOS 137ed85a6e6SPeter Ujfalusi }; 138ed85a6e6SPeter Ujfalusi 139ed85a6e6SPeter Ujfalusi /* Generic message fields (bit 24-30) */ 140ed85a6e6SPeter Ujfalusi 141ed85a6e6SPeter Ujfalusi /* encoded to header's msg_tgt field */ 142ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_TARGET_SHIFT 30 143ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_TARGET_MASK BIT(30) 144ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_TARGET(x) ((x) << SOF_IPC4_MSG_TARGET_SHIFT) 145ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_IS_MODULE_MSG(x) ((x) & SOF_IPC4_MSG_TARGET_MASK ? 1 : 0) 146ed85a6e6SPeter Ujfalusi 147ed85a6e6SPeter Ujfalusi /* encoded to header's rsp field */ 148ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_DIR_SHIFT 29 149ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_DIR_MASK BIT(29) 150ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_DIR(x) ((x) << SOF_IPC4_MSG_DIR_SHIFT) 151ed85a6e6SPeter Ujfalusi 152ed85a6e6SPeter Ujfalusi /* encoded to header's type field */ 153ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_TYPE_SHIFT 24 154ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_TYPE_MASK GENMASK(28, 24) 155ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_TYPE_SET(x) (((x) << SOF_IPC4_MSG_TYPE_SHIFT) & \ 156ed85a6e6SPeter Ujfalusi SOF_IPC4_MSG_TYPE_MASK) 157ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_TYPE_GET(x) (((x) & SOF_IPC4_MSG_TYPE_MASK) >> \ 158ed85a6e6SPeter Ujfalusi SOF_IPC4_MSG_TYPE_SHIFT) 159ed85a6e6SPeter Ujfalusi 160ed85a6e6SPeter Ujfalusi /* Global message type specific field definitions */ 161ed85a6e6SPeter Ujfalusi 162ed85a6e6SPeter Ujfalusi /* pipeline creation ipc msg */ 163ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT 16 164ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_INSTANCE_MASK GENMASK(23, 16) 165ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_INSTANCE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT) 166ed85a6e6SPeter Ujfalusi 167ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT 11 168ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_PRIORITY_MASK GENMASK(15, 11) 169ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_PRIORITY(x) ((x) << SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT) 170ed85a6e6SPeter Ujfalusi 171ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT 0 172ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK GENMASK(10, 0) 173ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_MEM_SIZE(x) ((x) << SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT) 174ed85a6e6SPeter Ujfalusi 175ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT 0 176ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_EXT_LP_MASK BIT(0) 177ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_EXT_LP(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT) 178ed85a6e6SPeter Ujfalusi 17911f45690SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT 20 18011f45690SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_MASK GENMASK(23, 20) 18111f45690SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_EXT_CORE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT) 18211f45690SPeter Ujfalusi 183ed85a6e6SPeter Ujfalusi /* pipeline set state ipc msg */ 184ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT 16 185ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_STATE_ID_MASK GENMASK(23, 16) 186ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_STATE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT) 187ed85a6e6SPeter Ujfalusi 188ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_STATE_SHIFT 0 189ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_STATE_MASK GENMASK(15, 0) 190ed85a6e6SPeter Ujfalusi #define SOF_IPC4_GLB_PIPE_STATE(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_SHIFT) 191ed85a6e6SPeter Ujfalusi 1922d271af1SRanjani Sridharan /* pipeline set state IPC msg extension */ 1932d271af1SRanjani Sridharan #define SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI BIT(0) 1942d271af1SRanjani Sridharan 1953ab2c21eSPeter Ujfalusi /* load library ipc msg */ 1963ab2c21eSPeter Ujfalusi #define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT 16 1973ab2c21eSPeter Ujfalusi #define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID(x) ((x) << SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT) 1983ab2c21eSPeter Ujfalusi 199*cb3cdef3SJyri Sarha /* chain dma ipc message */ 200*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT 0 201*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK GENMASK(4, 0) 202*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT) & \ 203*cb3cdef3SJyri Sarha SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK) 204*cb3cdef3SJyri Sarha 205*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT 8 206*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK GENMASK(12, 8) 207*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT) & \ 208*cb3cdef3SJyri Sarha SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK) 209*cb3cdef3SJyri Sarha 210*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT 16 211*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK BIT(16) 212*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT) 213*cb3cdef3SJyri Sarha 214*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT 17 215*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK BIT(17) 216*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_ENABLE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT) 217*cb3cdef3SJyri Sarha 218*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT 18 219*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_SCS_MASK BIT(18) 220*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_CHAIN_DMA_SCS(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT) 221*cb3cdef3SJyri Sarha 222*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT 0 223*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK GENMASK(24, 0) 224*cb3cdef3SJyri Sarha #define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE(x) (((x) << \ 225*cb3cdef3SJyri Sarha SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT) & \ 226*cb3cdef3SJyri Sarha SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK) 227*cb3cdef3SJyri Sarha 228ed85a6e6SPeter Ujfalusi enum sof_ipc4_channel_config { 229ed85a6e6SPeter Ujfalusi /* one channel only. */ 230ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_MONO, 231ed85a6e6SPeter Ujfalusi /* L & R. */ 232ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_STEREO, 233ed85a6e6SPeter Ujfalusi /* L, R & LFE; PCM only. */ 234ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_2_POINT_1, 235ed85a6e6SPeter Ujfalusi /* L, C & R; MP3 & AAC only. */ 236ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_3_POINT_0, 237ed85a6e6SPeter Ujfalusi /* L, C, R & LFE; PCM only. */ 238ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_3_POINT_1, 239ed85a6e6SPeter Ujfalusi /* L, R, Ls & Rs; PCM only. */ 240ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_QUATRO, 241ed85a6e6SPeter Ujfalusi /* L, C, R & Cs; MP3 & AAC only. */ 242ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_4_POINT_0, 243ed85a6e6SPeter Ujfalusi /* L, C, R, Ls & Rs. */ 244ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_5_POINT_0, 245ed85a6e6SPeter Ujfalusi /* L, C, R, Ls, Rs & LFE. */ 246ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_5_POINT_1, 247ed85a6e6SPeter Ujfalusi /* one channel replicated in two. */ 248ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_DUAL_MONO, 249ed85a6e6SPeter Ujfalusi /* Stereo (L,R) in 4 slots, 1st stream: [ L, R, -, - ] */ 250ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_0, 251ed85a6e6SPeter Ujfalusi /* Stereo (L,R) in 4 slots, 2nd stream: [ -, -, L, R ] */ 252ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_1, 253ed85a6e6SPeter Ujfalusi /* L, C, R, Ls, Rs & LFE., LS, RS */ 254ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNEL_CONFIG_7_POINT_1, 255ed85a6e6SPeter Ujfalusi }; 256ed85a6e6SPeter Ujfalusi 257ed85a6e6SPeter Ujfalusi enum sof_ipc4_interleaved_style { 258ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNELS_INTERLEAVED, 259ed85a6e6SPeter Ujfalusi SOF_IPC4_CHANNELS_NONINTERLEAVED, 260ed85a6e6SPeter Ujfalusi }; 261ed85a6e6SPeter Ujfalusi 262ed85a6e6SPeter Ujfalusi enum sof_ipc4_sample_type { 263ed85a6e6SPeter Ujfalusi SOF_IPC4_MSB_INTEGER, /* integer with Most Significant Byte first */ 264ed85a6e6SPeter Ujfalusi SOF_IPC4_LSB_INTEGER, /* integer with Least Significant Byte first */ 265ed85a6e6SPeter Ujfalusi }; 266ed85a6e6SPeter Ujfalusi 267ed85a6e6SPeter Ujfalusi struct sof_ipc4_audio_format { 268ed85a6e6SPeter Ujfalusi uint32_t sampling_frequency; 269ed85a6e6SPeter Ujfalusi uint32_t bit_depth; 270ed85a6e6SPeter Ujfalusi uint32_t ch_map; 271ed85a6e6SPeter Ujfalusi uint32_t ch_cfg; /* sof_ipc4_channel_config */ 272ed85a6e6SPeter Ujfalusi uint32_t interleaving_style; 273ed85a6e6SPeter Ujfalusi uint32_t fmt_cfg; /* channels_count valid_bit_depth s_type */ 274ed85a6e6SPeter Ujfalusi } __packed __aligned(4); 275ed85a6e6SPeter Ujfalusi 276ed85a6e6SPeter Ujfalusi #define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_SHIFT 0 277ed85a6e6SPeter Ujfalusi #define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK GENMASK(7, 0) 278ed85a6e6SPeter Ujfalusi #define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(x) \ 279ed85a6e6SPeter Ujfalusi ((x) & SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK) 280ed85a6e6SPeter Ujfalusi #define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT 8 281ed85a6e6SPeter Ujfalusi #define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK GENMASK(15, 8) 282ed85a6e6SPeter Ujfalusi #define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(x) \ 283ed85a6e6SPeter Ujfalusi (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK) >> \ 284ed85a6e6SPeter Ujfalusi SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT) 285ed85a6e6SPeter Ujfalusi #define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT 16 286ed85a6e6SPeter Ujfalusi #define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK GENMASK(23, 16) 287ed85a6e6SPeter Ujfalusi #define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE(x) \ 288ed85a6e6SPeter Ujfalusi (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK) >> \ 289ed85a6e6SPeter Ujfalusi SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT) 290ed85a6e6SPeter Ujfalusi 291ed85a6e6SPeter Ujfalusi /* Module message type specific field definitions */ 292ed85a6e6SPeter Ujfalusi 293ed85a6e6SPeter Ujfalusi enum sof_ipc4_module_type { 294ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_INIT_INSTANCE, 295ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_CONFIG_GET, 296ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_CONFIG_SET, 297ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_LARGE_CONFIG_GET, 298ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_LARGE_CONFIG_SET, 299ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_BIND, 300ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_UNBIND, 301ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_SET_DX, 302ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_SET_D0IX, 303ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_ENTER_MODULE_RESTORE, 304ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_EXIT_MODULE_RESTORE, 305ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_DELETE_INSTANCE, 306ed85a6e6SPeter Ujfalusi 307ed85a6e6SPeter Ujfalusi SOF_IPC4_MOD_TYPE_LAST, 308ed85a6e6SPeter Ujfalusi }; 309ed85a6e6SPeter Ujfalusi 310ed85a6e6SPeter Ujfalusi struct sof_ipc4_base_module_cfg { 311ed85a6e6SPeter Ujfalusi uint32_t cpc; /* the max count of Cycles Per Chunk processing */ 312ed85a6e6SPeter Ujfalusi uint32_t ibs; /* input Buffer Size (in bytes) */ 313ed85a6e6SPeter Ujfalusi uint32_t obs; /* output Buffer Size (in bytes) */ 314ed85a6e6SPeter Ujfalusi uint32_t is_pages; /* number of physical pages used */ 315ed85a6e6SPeter Ujfalusi struct sof_ipc4_audio_format audio_fmt; 316ed85a6e6SPeter Ujfalusi } __packed __aligned(4); 317ed85a6e6SPeter Ujfalusi 318ed85a6e6SPeter Ujfalusi /* common module ipc msg */ 319ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_INSTANCE_SHIFT 16 320ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_INSTANCE_MASK GENMASK(23, 16) 321ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_INSTANCE_SHIFT) 322ed85a6e6SPeter Ujfalusi 323ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_ID_SHIFT 0 324ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_ID_MASK GENMASK(15, 0) 325ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_ID(x) ((x) << SOF_IPC4_MOD_ID_SHIFT) 326ed85a6e6SPeter Ujfalusi 327ed85a6e6SPeter Ujfalusi /* init module ipc msg */ 328ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT 0 329ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK GENMASK(15, 0) 330ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_PARAM_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT) 331ed85a6e6SPeter Ujfalusi 332ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_PPL_ID_SHIFT 16 333ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_PPL_ID_MASK GENMASK(23, 16) 334ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_PPL_ID(x) ((x) << SOF_IPC4_MOD_EXT_PPL_ID_SHIFT) 335ed85a6e6SPeter Ujfalusi 336ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_CORE_ID_SHIFT 24 337ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_CORE_ID_MASK GENMASK(27, 24) 338ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_CORE_ID(x) ((x) << SOF_IPC4_MOD_EXT_CORE_ID_SHIFT) 339ed85a6e6SPeter Ujfalusi 340ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DOMAIN_SHIFT 28 341ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DOMAIN_MASK BIT(28) 342ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DOMAIN(x) ((x) << SOF_IPC4_MOD_EXT_DOMAIN_SHIFT) 343ed85a6e6SPeter Ujfalusi 344ed85a6e6SPeter Ujfalusi /* bind/unbind module ipc msg */ 345ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT 0 346ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DST_MOD_ID_MASK GENMASK(15, 0) 347ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DST_MOD_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT) 348ed85a6e6SPeter Ujfalusi 349ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT 16 350ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_MASK GENMASK(23, 16) 351ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT) 352ed85a6e6SPeter Ujfalusi 353ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT 24 354ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_MASK GENMASK(26, 24) 355ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT) 356ed85a6e6SPeter Ujfalusi 357ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT 27 358ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_MASK GENMASK(29, 27) 359ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT) 360ed85a6e6SPeter Ujfalusi 361ed85a6e6SPeter Ujfalusi #define MOD_ENABLE_LOG 6 362ed85a6e6SPeter Ujfalusi #define MOD_SYSTEM_TIME 20 363ed85a6e6SPeter Ujfalusi 364ed85a6e6SPeter Ujfalusi /* set module large config */ 365ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT 0 366ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK GENMASK(19, 0) 367ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT) 368ed85a6e6SPeter Ujfalusi 369ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT 20 370ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_MASK GENMASK(27, 20) 371ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_PARAM_ID(x) ((x) << SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT) 372ed85a6e6SPeter Ujfalusi 373ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT 28 374ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_MASK BIT(28) 375ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT) 376ed85a6e6SPeter Ujfalusi 377ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT 29 378ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK BIT(29) 379ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT) 380ed85a6e6SPeter Ujfalusi 381ed85a6e6SPeter Ujfalusi /* Init instance messagees */ 382ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_INIT_BASEFW_MOD_ID 0 383ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID 0 384ed85a6e6SPeter Ujfalusi 385ed85a6e6SPeter Ujfalusi enum sof_ipc4_base_fw_params { 386ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_PARAM_ENABLE_LOGS = 6, 387ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_PARAM_FW_CONFIG, 388ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_PARAM_HW_CONFIG_GET, 389ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_PARAM_MODULES_INFO_GET, 390ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_PARAM_LIBRARIES_INFO_GET = 16, 391ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_PARAM_SYSTEM_TIME = 20, 392ed85a6e6SPeter Ujfalusi }; 393ed85a6e6SPeter Ujfalusi 394ed85a6e6SPeter Ujfalusi enum sof_ipc4_fw_config_params { 395ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_FW_VERSION, 396ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_MEMORY_RECLAIMED, 397ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_SLOW_CLOCK_FREQ_HZ, 398ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_FAST_CLOCK_FREQ_HZ, 399ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_DMA_BUFFER_CONFIG, 400ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_ALH_SUPPORT_LEVEL, 401ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_DL_MAILBOX_BYTES, 402ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_UL_MAILBOX_BYTES, 403ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_TRACE_LOG_BYTES, 404ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_MAX_PPL_COUNT, 405ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_MAX_ASTATE_COUNT, 406ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_MAX_MODULE_PIN_COUNT, 407ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_MODULES_COUNT, 408ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_MAX_MOD_INST_COUNT, 409ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_MAX_LL_TASKS_PER_PRI_COUNT, 410ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_LL_PRI_COUNT, 411ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_MAX_DP_TASKS_COUNT, 412ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_MAX_LIBS_COUNT, 413ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_SCHEDULER_CONFIG, 414ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_XTAL_FREQ_HZ, 415ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_CLOCKS_CONFIG, 416ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_RESERVED, 417ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_POWER_GATING_POLICY, 418ed85a6e6SPeter Ujfalusi SOF_IPC4_FW_CFG_ASSERT_MODE, 419ed85a6e6SPeter Ujfalusi }; 420ed85a6e6SPeter Ujfalusi 421ed85a6e6SPeter Ujfalusi struct sof_ipc4_fw_version { 422ed85a6e6SPeter Ujfalusi uint16_t major; 423ed85a6e6SPeter Ujfalusi uint16_t minor; 424ed85a6e6SPeter Ujfalusi uint16_t hotfix; 425ed85a6e6SPeter Ujfalusi uint16_t build; 426ed85a6e6SPeter Ujfalusi } __packed; 427ed85a6e6SPeter Ujfalusi 428bd3df9ffSPeter Ujfalusi /* Payload data for SOF_IPC4_MOD_SET_DX */ 429bd3df9ffSPeter Ujfalusi struct sof_ipc4_dx_state_info { 430bd3df9ffSPeter Ujfalusi /* core(s) to apply the change */ 431bd3df9ffSPeter Ujfalusi uint32_t core_mask; 432bd3df9ffSPeter Ujfalusi /* core state: 0: put core_id to D3; 1: put core_id to D0 */ 433bd3df9ffSPeter Ujfalusi uint32_t dx_mask; 434bd3df9ffSPeter Ujfalusi } __packed __aligned(4); 435bd3df9ffSPeter Ujfalusi 436ed85a6e6SPeter Ujfalusi /* Reply messages */ 437ed85a6e6SPeter Ujfalusi 438ed85a6e6SPeter Ujfalusi /* 439ed85a6e6SPeter Ujfalusi * IPC4 primary header bit allocation for replies 440ed85a6e6SPeter Ujfalusi * bit 0-23: status 441ed85a6e6SPeter Ujfalusi * bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG 442ed85a6e6SPeter Ujfalusi * enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG 443ed85a6e6SPeter Ujfalusi * bit 29: response - sof_ipc4_msg_dir 444ed85a6e6SPeter Ujfalusi * bit 30: target - enum sof_ipc4_msg_target 445ed85a6e6SPeter Ujfalusi * bit 31: reserved, unused 446ed85a6e6SPeter Ujfalusi */ 447ed85a6e6SPeter Ujfalusi 448ed85a6e6SPeter Ujfalusi #define SOF_IPC4_REPLY_STATUS GENMASK(23, 0) 449ed85a6e6SPeter Ujfalusi 450ed85a6e6SPeter Ujfalusi /* Notification messages */ 451ed85a6e6SPeter Ujfalusi 452ed85a6e6SPeter Ujfalusi /* 453ed85a6e6SPeter Ujfalusi * IPC4 primary header bit allocation for notifications 454ed85a6e6SPeter Ujfalusi * bit 0-15: notification type specific 455ed85a6e6SPeter Ujfalusi * bit 16-23: enum sof_ipc4_notification_type 456ed85a6e6SPeter Ujfalusi * bit 24-28: SOF_IPC4_GLB_NOTIFICATION 457ed85a6e6SPeter Ujfalusi * bit 29: response - sof_ipc4_msg_dir 458ed85a6e6SPeter Ujfalusi * bit 30: target - enum sof_ipc4_msg_target 459ed85a6e6SPeter Ujfalusi * bit 31: reserved, unused 460ed85a6e6SPeter Ujfalusi */ 461ed85a6e6SPeter Ujfalusi 462ed85a6e6SPeter Ujfalusi #define SOF_IPC4_MSG_IS_NOTIFICATION(x) (SOF_IPC4_MSG_TYPE_GET(x) == \ 463ed85a6e6SPeter Ujfalusi SOF_IPC4_GLB_NOTIFICATION) 464ed85a6e6SPeter Ujfalusi 465ed85a6e6SPeter Ujfalusi #define SOF_IPC4_NOTIFICATION_TYPE_SHIFT 16 466ed85a6e6SPeter Ujfalusi #define SOF_IPC4_NOTIFICATION_TYPE_MASK GENMASK(23, 16) 467ed85a6e6SPeter Ujfalusi #define SOF_IPC4_NOTIFICATION_TYPE_GET(x) (((x) & SOF_IPC4_NOTIFICATION_TYPE_MASK) >> \ 468ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFICATION_TYPE_SHIFT) 469ed85a6e6SPeter Ujfalusi 470e9bcfea1SPeter Ujfalusi #define SOF_IPC4_LOG_CORE_SHIFT 12 471e9bcfea1SPeter Ujfalusi #define SOF_IPC4_LOG_CORE_MASK GENMASK(15, 12) 472e9bcfea1SPeter Ujfalusi #define SOF_IPC4_LOG_CORE_GET(x) (((x) & SOF_IPC4_LOG_CORE_MASK) >> \ 473e9bcfea1SPeter Ujfalusi SOF_IPC4_LOG_CORE_SHIFT) 474e9bcfea1SPeter Ujfalusi 475ed85a6e6SPeter Ujfalusi /* Value of notification type field - must fit into 8 bits */ 476ed85a6e6SPeter Ujfalusi enum sof_ipc4_notification_type { 477ed85a6e6SPeter Ujfalusi /* Phrase detected (notification from WoV module) */ 478ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_PHRASE_DETECTED = 4, 479ed85a6e6SPeter Ujfalusi /* Event from a resource (pipeline or module instance) */ 480ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_RESOURCE_EVENT, 481ed85a6e6SPeter Ujfalusi /* Debug log buffer status changed */ 482ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS, 483ed85a6e6SPeter Ujfalusi /* Timestamp captured at the link */ 484ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_TIMESTAMP_CAPTURED, 485ed85a6e6SPeter Ujfalusi /* FW complete initialization */ 486ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_FW_READY, 487ed85a6e6SPeter Ujfalusi /* Audio classifier result (ACA) */ 488ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_FW_AUD_CLASS_RESULT, 489ed85a6e6SPeter Ujfalusi /* Exception caught by DSP FW */ 490ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_EXCEPTION_CAUGHT, 491ed85a6e6SPeter Ujfalusi /* 11 is skipped by the existing cavs firmware */ 492ed85a6e6SPeter Ujfalusi /* Custom module notification */ 493ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_MODULE_NOTIFICATION = 12, 494ed85a6e6SPeter Ujfalusi /* 13 is reserved - do not use */ 495ed85a6e6SPeter Ujfalusi /* Probe notify data available */ 496ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_PROBE_DATA_AVAILABLE = 14, 497ed85a6e6SPeter Ujfalusi /* AM module notifications */ 498ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_ASYNC_MSG_SRVC_MESSAGE, 499ed85a6e6SPeter Ujfalusi 500ed85a6e6SPeter Ujfalusi SOF_IPC4_NOTIFY_TYPE_LAST, 501ed85a6e6SPeter Ujfalusi }; 502ed85a6e6SPeter Ujfalusi 503ed85a6e6SPeter Ujfalusi struct sof_ipc4_notify_resource_data { 504ed85a6e6SPeter Ujfalusi uint32_t resource_type; 505ed85a6e6SPeter Ujfalusi uint32_t resource_id; 506ed85a6e6SPeter Ujfalusi uint32_t event_type; 507ed85a6e6SPeter Ujfalusi uint32_t reserved; 508ed85a6e6SPeter Ujfalusi uint32_t data[6]; 509ed85a6e6SPeter Ujfalusi } __packed __aligned(4); 510ed85a6e6SPeter Ujfalusi 511ed85a6e6SPeter Ujfalusi /** @}*/ 512ed85a6e6SPeter Ujfalusi 513ed85a6e6SPeter Ujfalusi #endif 514