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/openbmc/linux/drivers/pinctrl/qcom/
H A DKconfig51 tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
59 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
63 tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
68 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
72 tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver"
77 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
81 tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
86 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
90 tristate "Qualcomm Technologies Inc SM8350 LPASS LPI pin controller driver"
95 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
[all …]
H A DMakefile37 obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
47 obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o
54 obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
56 obj-$(CONFIG_PINCTRL_SM8350_LPASS_LPI) += pinctrl-sm8350-lpass-lpi.o
58 obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o
60 obj-$(CONFIG_PINCTRL_SM8550_LPASS_LPI) += pinctrl-sm8550-lpass-lpi.o
61 obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o
62 obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
H A Dpinctrl-sm8250-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
145 .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
154 .name = "qcom-sm8250-lpass-lpi-pinctrl",
162 MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
H A Dpinctrl-sc7280-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
148 .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
157 .name = "qcom-sc7280-lpass-lpi-pinctrl",
165 MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
H A Dpinctrl-sm8350-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
148 .compatible = "qcom,sm8350-lpass-lpi-pinctrl",
157 .name = "qcom-sm8350-lpass-lpi-pinctrl",
166 MODULE_DESCRIPTION("QTI SM8350 LPI GPIO pin control driver");
H A Dpinctrl-sm6115-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
159 { .compatible = "qcom,sm6115-lpass-lpi-pinctrl", .data = &sm6115_lpi_data },
166 .name = "qcom-sm6115-lpass-lpi-pinctrl",
174 MODULE_DESCRIPTION("QTI SM6115 LPI GPIO pin control driver");
H A Dpinctrl-sc8280xp-lpass-lpi.c10 #include "pinctrl-lpass-lpi.h"
189 .compatible = "qcom,sc8280xp-lpass-lpi-pinctrl",
198 .name = "qcom-sc8280xp-lpass-lpi-pinctrl",
206 MODULE_DESCRIPTION("QTI SC8280XP LPI GPIO pin control driver");
/openbmc/linux/arch/arm64/kernel/
H A Dcpuidle.c23 struct acpi_lpi_state *lpi; in psci_acpi_cpu_init_idle() local
43 lpi = &pr->power.lpi_states[i + 1]; in psci_acpi_cpu_init_idle()
48 state = lpi->address; in psci_acpi_cpu_init_idle()
63 __cpuidle int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) in acpi_processor_ffh_lpi_enter() argument
65 u32 state = lpi->address; in acpi_processor_ffh_lpi_enter()
67 if (ARM64_LPI_IS_RETENTION_STATE(lpi->arch_flags)) in acpi_processor_ffh_lpi_enter()
69 lpi->index, state); in acpi_processor_ffh_lpi_enter()
72 lpi->index, state); in acpi_processor_ffh_lpi_enter()
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm6115-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM6115 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM6115 SoC.
19 const: qcom,sm6115-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
24 - description: LPASS LPI MCC registers
126 compatible = "qcom,sm6115-lpass-lpi-pinctrl";
H A Dqcom,sm8350-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8350 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8350 SoC.
19 const: qcom,sm8350-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
24 - description: LPASS LPI MCC registers
132 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
H A Dqcom,sc8280xp-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SC8280XP SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC.
18 const: qcom,sc8280xp-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
129 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
H A Dqcom,sm8550-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8550 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC.
19 const: qcom,sm8550-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
24 - description: LPASS LPI MCC registers
132 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
H A Dqcom,sm8450-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
131 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
H A Dqcom,sc7280-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SC7280 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SC7280 SoC.
18 const: qcom,sc7280-lpass-lpi-pinctrl
111 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
H A Dqcom,sm8250-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8250 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
18 const: qcom,sm8250-lpass-lpi-pinctrl
128 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
/openbmc/qemu/hw/intc/
H A Darm_gicv3_redist.c86 * update_for_one_lpi: Update pending information if this LPI is better
89 * @irq: interrupt to look up in the LPI Configuration table
90 * @ctbase: physical address of the LPI Configuration table to use
130 * update_for_all_lpis: Fully scan LPI tables and find best pending LPI
133 * @ptbase: physical address of LPI Pending table
134 * @ctbase: physical address of LPI Configuration table
139 * Recalculate the highest priority pending enabled LPI from scratch,
142 * We scan the LPI pending table @ptbase; for each pending LPI, we read the
143 * corresponding entry in the LPI configuration table @ctbase to extract
147 * LPI table sizes are architecturally specified in GICR_PROPBASER.IDBits
[all …]
H A Dgicv3_internal.h620 * Process a virtual LPI being directly injected by the ITS. This function
635 * Set/clear the pending status of a virtual LPI in the vLPI table
647 * Scan the LPI pending table and recalculate the highest priority
648 * pending LPI and also the overall highest priority pending interrupt.
655 * Scan the LPI pending table and recalculate cs->hpplpi only,
664 * @irq: LPI to invalidate cached information for
666 * Forget or update any cached information associated with this LPI.
682 * @irq: LPI to update
684 * Move the pending state of the specified LPI from @src to @dest,
693 * Scan the LPI pending table for @src, and for each pending LPI there
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000.h61 * LPI status, timer and control register offset
66 /* LPI control and status defines */
67 #define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */
70 #define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */
71 #define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */
72 #define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */
73 #define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */
74 #define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */
75 #define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */
76 #define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */
H A Ddwmac4.h180 * LPI status, timer and control register offset
187 /* LPI control and status defines */
188 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
189 #define GMAC4_LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable */
190 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
192 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
193 #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
194 #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
195 #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
196 #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
/openbmc/linux/drivers/acpi/
H A Dprocessor_idle.c935 /* LPI States start at index 3 */ in acpi_processor_evaluate_lpi()
1003 * flat_state_cnt - the number of composite LPI states after the process of flattening
1008 * combine_lpi_states - combine local and parent LPI states to form a composite LPI state
1010 * @local: local LPI state
1011 * @parent: parent LPI state
1012 * @result: composite LPI state
1064 pr_warn("Limiting number of LPI states to max (%d)\n", in flatten_lpi_states()
1146 /* flatten all the LPI states in this level of hierarchy */ in acpi_processor_get_lpi_info()
1166 int __weak acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) in acpi_processor_ffh_lpi_enter() argument
1172 * acpi_idle_lpi_enter - enters an ACPI any LPI state
[all …]
/openbmc/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c53 /* Reading this register shall clear all the LPI status bits */ in sxgbe_get_lpi_status()
190 /* Enable the LPI mode for transmit path with Tx automate bit set. in sxgbe_set_eee_mode()
192 * to LPI mode after all outstanding and pending packets are in sxgbe_set_eee_mode()
229 /* Program the timers in the LPI timer control register: in sxgbe_set_eee_timer()
232 * the LPI pattern. in sxgbe_set_eee_timer()
234 * after it has stopped transmitting the LPI pattern. in sxgbe_set_eee_timer()
H A Dsxgbe_common.h118 /* EEE-LPI mode flags*/
124 /* EEE-LPI Interrupt status flag */
127 /* EEE-LPI Default timer values */
131 /* EEE-LPI Control and status definitions */
243 /* EEE-LPI stats */
348 /* EEE-LPI specific operations */
501 /* EEE-LPI specific members */
/openbmc/openbmc/meta-fii/meta-kudo/recipes-kudo/kudo-fw-utility/kudo-fw/
H A Dkudo-fw.sh44 # Disable LPI mode NV_SI_CPU_LPI_FREQ_DISABLE for SCP 1.06 and older.
46 echo "Setting LPI mode for SCP 1.06 and older failed " >&2
50 # Disable LPI mode NV_SI_CPU_LPI_FREQ_DISABLE for SCP 1.07 and newer
52 echo "Setting LPI mode for SCP 1.07 and newer failed " >&2
/openbmc/linux/drivers/acpi/x86/
H A Ds2idle.c135 "LPI: constraints list begin:\n"); in lpi_device_get_constraints_amd()
186 acpi_handle_debug(lps0_device_handle, "LPI: constraints list end\n"); in lpi_device_get_constraints_amd()
213 acpi_handle_debug(lps0_device_handle, "LPI: constraints list begin:\n"); in lpi_device_get_constraints()
296 acpi_handle_debug(lps0_device_handle, "LPI: constraints list end\n"); in lpi_device_get_constraints()
337 "LPI: required min power state:%s current power state:%s\n", in lpi_check_constraints()
342 acpi_handle_info(entry->handle, "LPI: Device not power manageable\n"); in lpi_check_constraints()
349 "LPI: Constraint not met; min power state:%s current power state:%s\n", in lpi_check_constraints()
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt109 - snps,en-lpi: If present it enables use of the AXI low-power interface
118 - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
147 snps,en-tx-lpi-clockgating;
148 snps,en-lpi;

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