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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15 |
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| #
3abe84ea |
| 02-Mar-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
The description of second IO address is a bit confusing. It is supposed
to be the MCC range which contains the slew rate reg
dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
The description of second IO address is a bit confusing. It is supposed
to be the MCC range which contains the slew rate registers, not the slew
rate register base. The Linux driver then accesses slew rate register
with hard-coded offset (0xa000).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230302155255.857065-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Revision tags: v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10 |
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| #
315dffb8 |
| 03-Feb-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern
Narrow the pattern of possible GPIO names for pin controllers:
- SC7280 LPASS: GPIOs 0-14
- SM8250 LPASS: GPIOs 0-13
- SM8450 LPAS
dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern
Narrow the pattern of possible GPIO names for pin controllers:
- SC7280 LPASS: GPIOs 0-14
- SM8250 LPASS: GPIOs 0-13
- SM8450 LPASS: GPIOs 0-22
- SC8280XP LPASS: GPIOs 0-18
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230203164854.390080-1-krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20230203164854.390080-2-krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20230203164854.390080-3-krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20230203164854.390080-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Revision tags: v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16 |
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| #
a880fafb |
| 30-Dec-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: add input-enable and bias-bus-hold
Allow bias-bus-hold and input-enable properties (already used in
SC8280XP LPASS LPI nodes):
sa8540p-ride.dtb: pin
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: add input-enable and bias-bus-hold
Allow bias-bus-hold and input-enable properties (already used in
SC8280XP LPASS LPI nodes):
sa8540p-ride.dtb: pinctrl@33c0000: tx-swr-default-state: 'oneOf' conditional failed, one must be fixed:
'pins' is a required property
'function' is a required property
'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+'
'bias-bus-hold' does not match any of the regexes: 'pinctrl-[0-9]+'
Link: https://lore.kernel.org/r/20221230135645.56401-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| #
3c90b1ba |
| 30-Dec-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: correct pins pattern
SC8280XP LPASS LPI pin controller has GPIO 0-18:
sa8540p-ride.dtb: pinctrl@33c0000: tx-swr-default-state: 'oneOf' conditional f
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: correct pins pattern
SC8280XP LPASS LPI pin controller has GPIO 0-18:
sa8540p-ride.dtb: pinctrl@33c0000: tx-swr-default-state: 'oneOf' conditional failed, one must be fixed:
'pins' is a required property
'function' is a required property
'clk-pins', 'data-pins' do not match any of the regexes: 'pinctrl-[0-9]+'
'bias-bus-hold' does not match any of the regexes: 'pinctrl-[0-9]+'
'gpio2' does not match '^gpio([0-1]|1[0-8])$'
Fixes: 958bb025f5b3 ("dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings")
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221230135645.56401-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Revision tags: v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3 |
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| #
e1c36247 |
| 17-Oct-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: minor style cleanups
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently and drop redun
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: minor style cleanups
Drop "binding" from description (and align it with other Qualcomm
pinctrl bindings), use double quotes consistently and drop redundant
quotes.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221017230012.47878-31-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Revision tags: v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71 |
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| #
b47a6c8b |
| 27-Sep-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: fix matching pin config
The LPASS pin controller follows generic pin-controller bindings, so
just like TLMM, should have subnodes with '-state' and '-p
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: fix matching pin config
The LPASS pin controller follows generic pin-controller bindings, so
just like TLMM, should have subnodes with '-state' and '-pins'.
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220927153429.55365-9-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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| #
793b96bf |
| 27-Sep-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: fix gpio pattern
Fix double ']' in GPIO pattern to properly match "pins" property.
Otherwise schema for pins state fails.
Fixes: 958bb025f5b3 ("dt-bin
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: fix gpio pattern
Fix double ']' in GPIO pattern to properly match "pins" property.
Otherwise schema for pins state fails.
Fixes: 958bb025f5b3 ("dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings")
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220927153429.55365-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Revision tags: v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61 |
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| #
958bb025 |
| 17-Aug-2022 |
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> |
dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings
Add device tree binding Documentation details for Qualcomm SC8280XP
LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctr
dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings
Add device tree binding Documentation details for Qualcomm SC8280XP
LPASS(Low Power Audio Sub System) LPI(Low Power Island) pinctrl driver.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220817113747.9111-2-srinivas.kandagatla@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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