| /openbmc/linux/drivers/cpuidle/ |
| H A D | cpuidle-tegra.c | 281 * LP2 | C7 (CPU core power gating)
282 * LP2 | CC6 (CPU cluster power gating)
285 * differentiate the LP2 states because these states either used the same
354 /* LP2 could be disabled in device-tree */ in tegra_cpuidle_probe()
370 * cluster power-off (CC6 or LP2) states are common for all Tegra SoCs. in tegra_cpuidle_probe()
385 /* coupled CC6 (LP2) state isn't implemented yet */ in tegra_cpuidle_probe()
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| /openbmc/linux/arch/arm/mach-tegra/ |
| H A D | sleep.S | 84 * enters suspend in LP2 by turning off the mmu and jumping to
140 * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp
143 /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
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| H A D | reset-handler.S | 29 * an LP2 transition. Also branched to by LP0 and LP1 resume after
129 * R9 = CPU in LP2 state mask
206 /* Waking up from LP2? */
212 bleq __die @ no LP2 startup handler
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| H A D | sleep-tegra30.S | 245 /* flow controller set up for LP2 */
247 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
319 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
746 * executes from SDRAM with target state is LP2
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| H A D | pm.c | 150 * if any of secondary CPU's is online and this is the LP2-idle in tegra_sleep_cpu()
341 [TEGRA_SUSPEND_LP2] = "LP2",
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| H A D | sleep-tegra20.S | 324 * executes from SDRAM with target state is LP2
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| /openbmc/linux/arch/arm/include/asm/mach/ |
| H A D | arch.h | 42 unsigned char reserve_lp2 :1; /* never has lp2 */
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| /openbmc/linux/Documentation/devicetree/bindings/input/touchscreen/ |
| H A D | azoteq,iqs7211.yaml | 81 azoteq,rate-lp2-ms:
118 azoteq,timeout-lp2-ms:
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| /openbmc/linux/arch/arm/kernel/ |
| H A D | setup.c | 211 #define lp2 io_res[2] macro
921 * possessing lp0, lp1 or lp2 in request_standard_resources()
928 request_resource(&ioport_resource, &lp2); in request_standard_resources()
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-si514.c | 122 /* Calculate LP1/LP2 according to table 13 in the datasheet */ in si514_set_muldiv()
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| /openbmc/linux/Documentation/devicetree/bindings/arm/tegra/ |
| H A D | nvidia,tegra20-pmc.yaml | 93 Mode 2 is for LP2, CPU voltage off
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| /openbmc/linux/drivers/char/ |
| H A D | lp.c | 45 * bind lp2 to parport2)
73 * lp2 0x278
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| /openbmc/u-boot/lib/lzma/ |
| H A D | lzma.txt | 245 2) LZMA e file.bin file.lzma -lc0 -lp2
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| /openbmc/linux/drivers/input/touchscreen/ |
| H A D | iqs7211.c | 672 .name = "azoteq,rate-lp2-ms",
721 .name = "azoteq,timeout-lp2-ms",
733 .name = "azoteq,timeout-lp2-ms",
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| /openbmc/linux/drivers/scsi/isci/ |
| H A D | port_config.c | 154 * -> (PE0), (PE0, PE1), (PE0, PE1, PE2, PE3) LP1 -> (PE1) LP2 -> (PE2), (PE2,
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-tegra20.c | 987 * LP2 in idle or system suspend. in tegra20_cpu_clock_resume()
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| H A D | clk-tegra30.c | 1173 * LP2 in idle or system suspend. in tegra30_cpu_clock_resume()
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| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | i9xx_wm.c | 2820 /* ILK/SNB: LP2+ watermarks only w/o sprites */ in ilk_compute_pipe_wm()
2994 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ in ilk_wm_merge()
3007 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ in ilk_wm_lp_to_level()
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| /openbmc/linux/Documentation/admin-guide/ |
| H A D | devices.txt | 977 2 = /dev/pd_bdm2 PD BDM interface on lp2
980 6 = /dev/icd_bdm2 ICD BDM interface on lp2
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| /openbmc/linux/drivers/soc/tegra/ |
| H A D | pmc.c | 374 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
2990 * causes lockup if CPU enters LP2 idle state from some other in tegra_pmc_probe()
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