| /openbmc/u-boot/drivers/spi/ |
| H A D | Kconfig | 16 typically use driver-private data instead of extending the
24 by providing an high-level interface to send memory-like commands.
33 IP core. Please find details on the "Embedded Peripherals IP
56 this Andestech IP core.
65 please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
81 SPI core.
94 Enable the Broadcom set-top box SPI driver. This driver can
96 Broadcom SPI core.
101 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
103 Cadence IP core.
[all …]
|
| /openbmc/linux/drivers/usb/dwc3/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "DesignWare USB3 DRD Core Support"
11 USB controller based on the DesignWare USB3 IP Core.
64 AM437x use this IP for USB2/3 functionality.
74 Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3
75 IP inside, say 'Y' or 'M' if you have one such device.
78 tristate "PCIe-based Platforms"
82 If you're using the DesignWare Core IP with a PCIe (but not HAPS
86 tristate "Synopsys PCIe-based HAPS Platforms"
90 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
[all …]
|
| /openbmc/qemu/hw/intc/ |
| H A D | loongson_liointc.c | 26 #include "hw/qdev-properties.h"
52 uint8_t mapper[NUM_IRQS]; /* 0:3 for core, 4:7 for IP */
64 uint32_t irq, core, ip; in update_irq() local
68 p->isr = p->pin_state; in update_irq()
71 p->isr &= p->ien; in update_irq()
74 for (core = 0; core < NUM_CORES; core++) { in update_irq()
75 p->per_core_isr[core] = 0; in update_irq()
80 if (!(p->isr & (1 << irq))) { in update_irq()
84 for (core = 0; core < NUM_CORES; core++) { in update_irq()
85 if ((p->mapper[irq] & (1 << core))) { in update_irq()
[all …]
|
| /openbmc/linux/tools/testing/selftests/net/ |
| H A D | rps_default_mask.sh | 2 # SPDX-License-Identifier: GPL-2.0
8 [ $cpus -gt 2 ] || exit $ksft_skip
10 readonly INITIAL_RPS_DEFAULT_MASK=$(cat /proc/sys/net/core/rps_default_mask)
11 readonly TAG="$(mktemp -u XXXXXX)"
13 readonly NETNS="ns-${TAG}"
16 ip netns add "${NETNS}"
17 ip -netns "${NETNS}" link set lo up
21 echo $INITIAL_RPS_DEFAULT_MASK > /proc/sys/net/core/rps_default_mask
22 ip netns del $NETNS
32 [ -n "$netns" ] && cmd="ip netns exec $netns $cmd"
[all …]
|
| H A D | ipv6_route_update_soft_lockup.sh | 2 # SPDX-License-Identifier: GPL-2.0
11 # ┌----------------┐ ┌----------------┐
17 # | ┌-----------| nexthops |---------┐ |
18 # | |veth_source|<--------------------------------------->|veth_sink|<┐ |
19 # | └-----------|2001:0DB8:1::0:1/96 2001:0DB8:1::1:1/96 |---------┘ | |
22 # | ┌---------┐ | . . | | |
24 # | | routing | | . 2001:0DB8:1::1:80/96| ┌-----┐ |
26 # | | nexthop | | . └--------┴-----┴-┘
28 # | └-------- ┘ |
29 # └----------------┘
[all …]
|
| /openbmc/linux/drivers/net/can/ctucanfd/ |
| H A D | Kconfig | 2 tristate "CTU CAN-FD IP core" if COMPILE_TEST
4 This driver adds support for the CTU CAN FD open-source IP core.
5 More documentation and core sources at project page
7 The core integration to Xilinx Zynq system as platform driver
8 is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
9 Implementation on Intel FPGA-based PCI Express board is available
10 from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and
11 on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd).
15 tristate "CTU CAN-FD IP core PCI/PCIe driver"
19 This driver adds PCI/PCIe support for CTU CAN-FD IP core.
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/ |
| H A D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
11 control how the core is synthesized. Historically, the EDK tool would
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
[all …]
|
| H A D | example-schema.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 # All the top-level keys are standard json-schema keywords except for
10 $id: http://devicetree.org/schemas/example-schema.yaml#
11 # $schema is the meta-schema this schema should be validated with.
12 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Rob Herring <robh@kernel.org>
20 A more detailed multi-line description of the binding.
44 - items:
51 - enum:
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/pwm/ |
| H A D | microchip,corepwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip IP corePWM controller
11 - Conor Dooley <conor.dooley@microchip.com>
14 corePWM is an 16 channel pulse width modulator FPGA IP
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/media/xilinx/ |
| H A D | video.txt | 1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
[all …]
|
| H A D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
[all …]
|
| /openbmc/linux/drivers/staging/axis-fifo/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
|
| /openbmc/linux/Documentation/devicetree/bindings/ptp/ |
| H A D | ptp-ines.txt | 1 ZHAW InES PTP time stamping IP core
3 The IP core needs two different kinds of nodes. The control node
7 port index within the IP core.
11 - compatible: "ines,ptp-ctrl"
12 - reg: physical address and size of the register bank
16 - timestamper: provides control node reference and
17 the port channel within the IP core
22 compatible = "ines,ptp-ctrl";
30 ethernet-phy@3 {
|
| /openbmc/linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
[all …]
|
| /openbmc/linux/drivers/usb/usbip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "USB/IP support"
9 This enables pushing USB packets over IP to allow remote
11 USB/IP core that is required by both drivers.
17 be called usbip-core.
25 This enables the USB/IP virtual host controller driver,
29 module will be called vhci-hcd.
32 int "Number of ports per USB/IP virtual host controller"
37 To increase number of ports available for USB/IP virtual
39 USB/IP virtual host controller.
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | allegro,al5e.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allegro DVT Video IP Codecs
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
14 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.
23 - items:
24 - const: allegro,al5e-1.1
[all …]
|
| /openbmc/openbmc/poky/meta/lib/oeqa/runtime/cases/ |
| H A D | ping.py | 4 # SPDX-License-Identifier: MIT
11 from oeqa.core.decorator.oetimeout import OETimeout
12 from oeqa.core.exception import OEQATimeoutError
20 self.assertNotEqual(len(self.target.ip), 0, msg="No target IP address set")
22 # If the target IP is localhost (because user-space networking is being used),
24 if self.target.ip.startswith("127.0.0.") or self.target.ip in ("localhost", "::1"):
30 cmd = 'ping -c 1 %s' % self.target.ip
32 output += proc.communicate()[0].decode('utf-8')
39 …self.fail("Ping timeout error for address %s, count %s, output: %s" % (self.target.ip, count, outp…
|
| /openbmc/linux/Documentation/networking/caif/ |
| H A D | linux_caif.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 Copyright |copy| ST-Ericsson AB 2010
17 CAIF is a MUX protocol used by ST-Ericsson cellular modems for
22 ST-Ericsson modems support a number of transports between modem
31 * CAIF Socket Layer and GPRS IP Interface.
32 * CAIF Core Protocol Implementation
39 ! +------+ +------+
40 ! +------+! +------+!
41 ! ! IP !! !Socket!!
42 +-------> !interf!+ ! API !+ <- CAIF Client APIs
[all …]
|
| /openbmc/linux/drivers/pci/controller/dwc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
26 core plus Annapurna Labs proprietary hardware wrappers. This is
27 required only for DT-based platforms. ACPI platforms with the
38 and therefore the driver re-uses the DesignWare core functions to
45 bool "Axis ARTPEC-6 PCIe controller (host mode)"
51 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
52 host mode. This uses the DesignWare core.
55 bool "Axis ARTPEC-6 PCIe controller (endpoint mode)"
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | adi,axi-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI ADC IP core
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
17 interface for the actual ADC, while this IP core will interface
18 to the data-lines of the ADC and handle the streaming of data into
26 - adi,axi-adc-10.0.a
[all …]
|
| /openbmc/linux/fs/jfs/ |
| H A D | jfs_discard.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
23 * ip - pointer to in-core inode
24 * blkno - starting block number to be trimmed (0..N)
25 * nblocks - number of blocks to be trimmed
32 void jfs_issue_discard(struct inode *ip, u64 blkno, u64 nblocks) in jfs_issue_discard() argument
34 struct super_block *sb = ip->i_sb; in jfs_issue_discard()
58 * ip - pointer to in-core inode;
59 * range - the range, given by user space
62 * 0 - success
63 * -EIO - i/o error
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/input/ |
| H A D | ps2keyb-mouse-apbps2.txt | 1 Aeroflex Gaisler APBPS2 PS/2 Core, supporting Keyboard or Mouse.
3 The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the APBPS2 core, a LEON SPARC system,
11 - name : Should be "GAISLER_APBPS2" or "01_060"
12 - reg : Address and length of the register set for the device
13 - interrupts : Interrupt numbers for this device
15 For further information look in the documentation for the GLIB IP core library:
|
| /openbmc/openbmc/poky/meta/lib/oeqa/controllers/ |
| H A D | controllerimage.py | 3 # SPDX-License-Identifier: MIT
6 # tests using a "controller image" - this is a "known good" image that is
11 # For an example controller image, see core-image-testcontroller
12 # (meta/recipes-extended/images/core-image-testcontroller.bb)
34 # target ip
35 …addr = d.getVar("TEST_TARGET_IP") or bb.fatal('Please set TEST_TARGET_IP with the IP address of th…
36 self.ip = addr.split(":")[0]
41 bb.note("Target IP: %s" % self.ip)
45 …self.server_ip = subprocess.check_output(['ip', 'route', 'get', self.ip ]).split("\n")[0].split()[…
47 …bb.fatal("Failed to determine the host IP address (alternatively you can set TEST_SERVER_IP with t…
[all …]
|
| /openbmc/openbmc/poky/meta/lib/oeqa/ |
| H A D | runexported.py | 5 # SPDX-License-Identifier: MIT
11 #- export the tests:
16 # bitbake core-image-sato -c testimage
17 # Setup your target, e.g for qemu: runqemu core-image-sato
18 # cd build/tmp/testimage/core-image-sato
43 self.ip = None
56 self.connection = SSHControl(self.ip, logfile=self.sshlog)
75 …parser.add_argument("-t", "--target-ip", dest="ip", help="The IP address of the target machine. Us…
77 …parser.add_argument("-s", "--server-ip", dest="server_ip", help="The IP address of this machine. U…
79 …parser.add_argument("-d", "--deploy-dir", dest="deploy_dir", help="Full path to the package feeds,…
[all …]
|
| /openbmc/u-boot/arch/arm/cpu/armv7/ |
| H A D | nonsec_virt.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * code for switching cores into non-secure state and into HYP mode
12 #include <asm/proc-armv/ptrace.h>
39 * U-Boot calls this "software interrupt" in start.S
41 * to non-secure state.
43 * ip: target PC
55 push {r0, r1, r2, ip}
57 pop {r0, r1, r2, ip}
98 mov lr, ip
99 mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
[all …]
|