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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pidgin/pidgin-sipe/
H A D0001-Migrate-to-use-g_memdup2.patch3 Date: Mon, 5 Apr 2021 11:36:50 -0700
6 g_memdup has been deprecated for long and latest glib-2.0 2.68+ has
9 The fall-back to g_memdup isn't needed because pidgin provides g_memdup2
10 in pidgin-sipe/1.25.0-r0/recipe-sysroot/usr/include/libpurple/glibcompat.h
11 based on glib-2.0 version:
13 * see https://mail.gnome.org/archives/desktop-devel-list/2021-February/msg00000.html
30 Upstream-Status: Pending
31 Signed-off-by: Khem Raj <raj.khem@gmail.com>
32 ---
33 src/api/sipe-common.h | 3 +++
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/openbmc/qemu/include/qemu/
H A Dbitops.h9 * See the COPYING.LIB file in the top-level directory.
16 #include "host-utils.h"
27 #define MAKE_64BIT_MASK(shift, length) \ argument
28 (((~0ULL) >> (64 - (length))) << (shift))
33 * We provide a set of functions which work on arbitrary-length arrays of
37 * - Bits stored in an array of 'unsigned long': set_bit(), clear_bit(), etc
38 * - Bits stored in an array of 'uint32_t': set_bit32(), clear_bit32(), etc
43 * be some guest-visible register view of the bit array.
63 * set_bit - Set a bit in memory
76 * set_bit_atomic - Set a bit in memory atomically
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/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/
H A DPCIeSlot.interface.yaml6 - name: Generation
12 - name: Lanes
17 - name: SlotType
23 - name: HotPluggable
29 - name: Generations
33 - name: "Gen1"
37 - name: "Gen2"
41 - name: "Gen3"
45 - name: "Gen4"
49 - name: "Gen5"
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/openbmc/u-boot/lib/zlib/
H A Ddeflate.h1 /* deflate.h -- internal compression state
2 * Copyright (C) 1995-2010 Jean-loup Gailly
31 /* number of length codes, not counting the special END_BLOCK code */
37 /* number of Literal or Length codes, including the END_BLOCK code */
69 ush len; /* length of bit string */
111 uInt w_mask; /* w_size - 1 */
114 /* Sliding window. Input bytes are read into the second half of the window,
115 * and move to the first half later to keep a dictionary of at least wSize
117 * wSize-MAX_MATCH bytes, but this ensures that IO is always
118 * performed with a length multiple of the block size. Also, it limits
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/openbmc/qemu/docs/
H A Dxbzrle.txt1 XBZRLE (Xor Based Zero Run Length Encoding)
4 Using XBZRLE (Xor Based Zero Run Length Encoding) allows for the reduction
5 of VM downtime and the total live-migration time of Virtual machines.
28 A zero run is represented by its length (in bytes).
29 A non zero run is represented by its length (in bytes) and the new data.
30 The run length is encoded using ULEB128 (http://en.wikipedia.org/wiki/LEB128)
38 zrun = length
40 nzrun = length byte...
42 length = uleb128 encoded integer
55 XBZRLE has a sustained bandwidth of 2-2.5 GB/s for typical workloads making it
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/openbmc/u-boot/include/configs/
H A D3c120_devboard.h1 /* SPDX-License-Identifier: GPL-2.0+ */
44 * -Monitor at top of sdram.
45 * -The heap is placed below the monitor
46 * -The stack is placed below the heap (&grows down).
53 CONFIG_SYS_SDRAM_SIZE - \
58 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
61 * of flash. NOTE: the monitor length must be multiple of sector size
72 #define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */
75 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
76 CONFIG_ENV_SIZE - \
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H A D10m50_devboard.h1 /* SPDX-License-Identifier: GPL-2.0+ */
44 * -Monitor at top of sdram.
45 * -The heap is placed below the monitor
46 * -The stack is placed below the heap (&grows down).
53 CONFIG_SYS_SDRAM_SIZE - \
58 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
61 * of flash. NOTE: the monitor length must be multiple of sector size
72 #define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */
75 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
76 CONFIG_ENV_SIZE - \
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/openbmc/openbmc-test-automation/lib/
H A Dutils.py66 # The user has not set bmc_power_policy_method via a -v parm so we will
98 Using old style functions, callers might call like this with a hard-
129 [local_time]: Fri 2017-11-03 152756 UTC
131 [universal_time]: Fri 2017-11-03 152756 UTC
133 [rtc_time]: Fri 2016-05-20 163403
143 # Local time: Fri 2017-11-03 15:27:56 UTC
144 # Universal time: Fri 2017-11-03 15:27:56 UTC
145 # RTC time: Fri 2016-05-20 16:34:03
185 [1k-blocks]: 247120
192 [1k-blocks]: 247120
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/openbmc/u-boot/drivers/net/
H A De1000.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
10 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
36 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
40 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
51 writel((value), ((a)->hw_addr + E1000_##reg))
53 readl((a)->hw_addr + E1000_##reg)
55 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
57 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
349 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
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H A Ddm9000x.c1 // SPDX-License-Identifier: GPL-2.0+
8 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
15 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
28 --------------------------------------
30 12/15/2003 Initial port to u-boot by
34 - Fixed the driver to work with DM9000A.
38 - Added autodetect of databus width.
39 - Made debug code compile again.
40 - Adapt eth_send such that it matches the DM9000*
43 - Adapted reset procedure to match DM9000 application
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H A Dat91_emac.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Jens Scharsig (esw@bus-elektronik.de)
92 writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); in at91emac_EnableMDIO()
98 writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); in at91emac_DisableMDIO()
110 &at91mac->man); in at91emac_read()
113 netstat = readl(&at91mac->sr); in at91emac_read()
117 *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; in at91emac_read()
139 &at91mac->man); in at91emac_write()
142 netstat = readl(&at91mac->sr); in at91emac_write()
158 return (at91_emac_t *) netdev->iobase; in get_emacbase_by_name()
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H A Drtl8139.c2 * rtl8139.c : U-Boot driver for the RealTek RTL8139
10 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
13 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
19 - removed support for interrupts, switching to polling mode (yuck!)
20 - removed support for the 8129 chip (external MII)
33 Following email from Hyun-Joon Cha, added a disable routine, otherwise
36 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
40 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
44 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
51 hunting session. It took me about a week full time work - poking around
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H A Dnatsemi.c2 natsemi.c: A U-Boot driver for the NatSemi DP8381x series.
21 Written/copyright 1999-2001 by Donald Becker.
48 * Initial U-Boot Release. Tested with Netgear FA311 board
61 #define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
71 Unlike software-only systems, device drivers interact with complex hardware.
239 static int natsemi_send(struct eth_device *dev, void *packet, int length);
248 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
249 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
254 return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); in INW()
260 return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); in INL()
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H A Dax88180.c2 * ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
19 * ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver
23 * SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any
33 * Date : 2008-07-07
73 while (--us_cnt) { in ax88180_mdio_check_complete()
85 struct ax88180_private *priv = (struct ax88180_private *)dev->priv; in ax88180_mdio_read()
88 OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL); in ax88180_mdio_read()
102 struct ax88180_private *priv = (struct ax88180_private *)dev->priv; in ax88180_mdio_write()
106 OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL); in ax88180_mdio_write()
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/openbmc/ipmitool/src/plugins/bmc/
H A Dbmc_intf.h22 * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED.
103 * the request pkt is mainly for KCS-interface-BMC
104 * messages. Since the system interface is session-less
117 uint8_t datalength; /* length of following data */
126 * the respond pkt is mainly for KCS-interface-BMC
127 * messages. Since the system interface is session-less
139 uint8_t datalength; /* Length */
147 bmc_req_t req; /* request half */
148 bmc_rsp_t rsp; /* response half */
177 uint8_t msg[1]; /* Variable length message data */
/openbmc/qemu/hw/nvram/
H A Dmac_nvram.c4 * Copyright (c) 2005-2007 Fabrice Bellard
30 #include "hw/qdev-properties.h"
31 #include "hw/qdev-properties-system.h"
32 #include "system/block-backend.h"
36 #include "qemu/error-report.h"
48 addr = (addr >> s->it_shift) & (s->size - 1); in macio_nvram_writeb()
50 s->data[addr] = value; in macio_nvram_writeb()
51 if (s->blk) { in macio_nvram_writeb()
52 if (blk_pwrite(s->blk, addr, 1, &s->data[addr], 0) < 0) { in macio_nvram_writeb()
54 blk_name(s->blk)); in macio_nvram_writeb()
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/openbmc/u-boot/include/
H A Dfsl_dtsec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
30 u32 ipgifg; /* inter-packet/inter-frame gap */
31 u32 hafdup; /* half-duplex control */
63 u32 rflr; /* Receive frame length error */
121 /* IEVENT - interrupt events register */
141 /* IMASK - interrupt mask register */
161 /* ECNTRL - ethernet control register */
166 #define ECNTRL_GMIIM 0x00000040 /* 1- GMII or RGMII interface mode */
167 #define ECNTRL_TBIM 0x00000020 /* 1- Ten-bit interface mode */
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/openbmc/qemu/docs/specs/
H A Dfw_cfg.rst5 Guest-side Hardware Interface
15 ---------------------------
19 * Width: 16-bit
20 * Endianness: little-endian (if IOport), or big-endian (if MMIO)
34 the selector value is between 0x4000-0x7fff or 0xc000-0xffff.
38 longer supported, and will be ignored (treated as no-ops)!
49 items are accessed with a selector value between 0x0000-0x7fff, and
51 value between 0x8000-0xffff.
54 -------------
58 * Width: 8-bit (if IOport), 8/16/32/64-bit (if MMIO)
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/openbmc/u-boot/include/linux/
H A Dserial_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
91 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
116 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
126 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
222 * The Intel XScale on-chip UARTs define these bits
237 * Intel MID on-chip HSU (High Speed UART) defined bits
252 #define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */
277 #define UART_NMR 0x0D /* Nine-bit Mode Register */
293 * These definitions are for the RSA-DV II/S card, from
295 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
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/openbmc/u-boot/common/
H A Dkgdb.c1 /* taken from arch/powerpc/kernel/ppc-stub.c */
80 * When a packet is received, it is first acknowledged with either '+' or '-'.
81 * '+' indicates a successful transfer. '-' indicates a failed transfer.
121 return ch-'a'+10; in hex()
123 return ch-'0'; in hex()
125 return ch-'A'+10; in hex()
126 return -1; in hex()
139 * We use the upper half of buf as an intermediate buffer for the in mem2hex()
147 while (count-- > 0) { in mem2hex()
167 * We use the upper half of buf as an intermediate buffer for the in hex2mem()
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/openbmc/u-boot/drivers/spi/
H A Dmxs_spi.c1 // SPDX-License-Identifier: GPL-2.0+
8 * NOTE: This driver only supports the SPI-controller chipselects,
19 #include <asm/arch/imx-regs.h>
21 #include <asm/mach-imx/dma.h>
68 mxs_slave->max_khz = max_hz / 1000; in spi_setup_slave()
69 mxs_slave->mode = mode; in spi_setup_slave()
70 mxs_slave->regs = mxs_ssp_regs_by_bus(bus); in spi_setup_slave()
72 return &mxs_slave->slave; in spi_setup_slave()
88 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; in spi_claim_bus()
91 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); in spi_claim_bus()
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H A Dmt7621_spi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Derived from the Linux driver version drivers/spi/spi-mt7621.c
7 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
8 * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
50 setbits_le32(rs->base + MT7621_SPI_MASTER, in mt7621_spi_reset()
58 debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable"); in mt7621_spi_set_cs()
61 iowrite32(val, rs->base + MT7621_SPI_POLAR); in mt7621_spi_set_cs()
70 reg = ioread32(rs->base + MT7621_SPI_MASTER); in mt7621_spi_set_mode()
90 iowrite32(reg, rs->base + MT7621_SPI_MASTER); in mt7621_spi_set_mode()
102 rate = DIV_ROUND_UP(rs->sys_freq, speed); in mt7621_spi_set_speed()
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/openbmc/u-boot/drivers/i2c/
H A Dlpc32xx_i2c.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014-2015 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
59 return -EINVAL; in __i2c_set_bus_speed()
65 return -EINVAL; in __i2c_set_bus_speed()
69 return -EINVAL; in __i2c_set_bus_speed()
72 writel(half_period, &base->clk_hi); in __i2c_set_bus_speed()
73 writel(half_period, &base->clk_lo); in __i2c_set_bus_speed()
81 /* soft reset (auto-clears) */ in __i2c_init()
82 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl); in __i2c_init()
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/openbmc/qemu/monitor/
H A Dqmp.c4 * Copyright (c) 2003-2004 Fabrice Bellard
27 #include "chardev/char-io.h"
28 #include "monitor-internal.h"
30 #include "qapi/qapi-commands-control.h"
45 * be pushed onto mon->qmp_requests, and @qmp_dispatcher_co_shutdown may
65 * (exactly one of them is non-null)
76 return mon->capab[QMP_CAPABILITY_OOB]; in qmp_oob_enabled()
81 memset(mon->capab_offered, 0, sizeof(mon->capab_offered)); in monitor_qmp_caps_reset()
82 memset(mon->capab, 0, sizeof(mon->capab)); in monitor_qmp_caps_reset()
83 mon->capab_offered[QMP_CAPABILITY_OOB] = mon->common.use_io_thread; in monitor_qmp_caps_reset()
[all …]
/openbmc/u-boot/board/armadeus/apf27/
H A Dapf27.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
66 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
90 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
91 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
100 #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
103 #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
136 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
137 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
146 #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
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