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/openbmc/linux/drivers/gpu/drm/vc4/
H A Dvc4_hvs.c7 * DOC: VC4 HVS module.
9 * The Hardware Video Scaler (HVS) is the piece of hardware that does
16 * There is a single global HVS, with multiple output FIFOs that can
18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for
70 void vc4_hvs_dump_state(struct vc4_hvs *hvs) in vc4_hvs_dump_state() argument
72 struct drm_device *drm = &hvs->vc4->base; in vc4_hvs_dump_state()
73 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); in vc4_hvs_dump_state()
79 drm_print_regset32(&p, &hvs->regset); in vc4_hvs_dump_state()
81 DRM_INFO("HVS ctx:\n"); in vc4_hvs_dump_state()
85 readl((u32 __iomem *)hvs->dlist + i + 0), in vc4_hvs_dump_state()
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H A Dvc4_plane.c9 * Each DRM plane is a layer of pixels being scanned out by the HVS.
11 * At atomic modeset check time, we compute the HVS display element
15 * into the region of the HVS that it has allocated for us.
35 u32 hvs; /* HVS_FORMAT_* */ member
42 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
48 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
54 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
60 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
66 .hvs = HVS_PIXEL_FORMAT_RGB565,
72 .hvs = HVS_PIXEL_FORMAT_RGB565,
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H A Dvc4_crtc.c12 * the HVS at that timing, and feeds it to the encoder.
16 * responsible for writing the display list for the HVS channel that
85 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_cob_allocation() local
105 struct vc4_hvs *hvs = vc4->hvs; in vc4_crtc_get_scanout_position() local
122 * pixelvalve by the HVS, and also the scaler status. in vc4_crtc_get_scanout_position()
132 /* Vertical position of hvs composed scanline. */ in vc4_crtc_get_scanout_position()
140 if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2) in vc4_crtc_get_scanout_position()
145 /* This is the offset we need for translating hvs -> pv scanout pos. */ in vc4_crtc_get_scanout_position()
151 /* HVS more than fifo_lines into frame for compositing? */ in vc4_crtc_get_scanout_position()
155 * from HVS. The actual PV scanout can not trail behind more in vc4_crtc_get_scanout_position()
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H A Dvc4_kms.c137 struct vc4_hvs *hvs = vc4->hvs; in vc4_ctm_commit() local
211 struct vc4_hvs *hvs = vc4->hvs; in vc4_hvs_pv_muxing_commit() local
252 struct vc4_hvs *hvs = vc4->hvs; in vc5_hvs_pv_muxing_commit() local
327 struct vc4_hvs *hvs = vc4->hvs; in vc4_atomic_commit_tail() local
350 vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel); in vc4_atomic_commit_tail()
376 500000000, hvs->max_core_rate); in vc4_atomic_commit_tail()
384 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
411 hvs->max_core_rate, in vc4_atomic_commit_tail()
417 * Request a clock rate based on the current HVS in vc4_atomic_commit_tail()
420 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate)); in vc4_atomic_commit_tail()
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H A Dvc4_drv.h90 struct vc4_hvs *hvs; member
204 * demanding in term of memory or HVS bandwidth which is hard to guess
327 /* Memory manager for the LBM memory used by HVS scaling. */
436 /* Load of this plane on the HVS block. The load is expressed in HVS
499 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
502 /* Which output of the HVS this pixelvalve sources from. */
559 * set in the HVS for that CRTC. Protected by @irq_lock, and
566 * @current_hvs_channel: HVS channel currently assigned to the
634 readl(hvs->regs + (offset)); \
640 writel(val, hvs->regs + (offset)); \
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H A Dvc4_drv.c277 { .compatible = "brcm,bcm2711-hvs" },
278 { .compatible = "brcm,bcm2835-hvs" },
415 * but after the HVS to set the possible_crtc field properly
416 * - The HDMI driver needs to be bound after the HVS so that we can
417 * lookup the HVS maximum core clock rate and figure out if we
H A Dvc4_regs.h221 /* Global register for clock gating the HVS */
399 /* Last pixel in the COB (display FIFO memory) allocated to this HVS
405 /* First pixel in the COB (display FIFO memory) allocated to this HVS
494 /* Slave addresses for DMAing from HVS composition output to other
819 /* HVS display list information. */
H A Dvc4_txp.c50 /* Pre-rotation width/height of the image. Must match HVS config.
133 /* Request odd field from HVS. */
/openbmc/linux/net/vmw_vsock/
H A Dhyperv_transport.c251 struct hvsock *hvs = vsk->trans; in hvs_channel_cb() local
252 struct vmbus_channel *chan = hvs->chan; in hvs_channel_cb()
303 struct hvsock *hvs = NULL; in hvs_open_connection() local
353 hvs = vsock_sk(sk)->trans; in hvs_open_connection()
354 hvs->chan = chan; in hvs_open_connection()
393 hvs->chan = NULL; in hvs_open_connection()
444 struct hvsock *hvs; in hvs_sock_init() local
447 hvs = kzalloc(sizeof(*hvs), GFP_KERNEL); in hvs_sock_init()
448 if (!hvs) in hvs_sock_init()
451 vsk->trans = hvs; in hvs_sock_init()
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/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dbrcm,bcm2835-hvs.yaml4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-hvs.yaml#
15 - brcm,bcm2711-hvs
16 - brcm,bcm2835-hvs
39 const: brcm,bcm2711-hvs
47 hvs@7e400000 {
48 compatible = "brcm,bcm2835-hvs";
H A Dbrcm,bcm2835-vc4.yaml14 with HDMI output and the HVS (Hardware Video Scaler) for compositing
/openbmc/linux/Documentation/gpu/
H A Dvc4.rst21 HVS section in Display Hardware Handling
25 :doc: VC4 HVS module.
27 HVS planes
73 * The HVS to PixelValve dynamic FIFO assignment, for the BCM2835-7
/openbmc/linux/drivers/gpu/drm/vc4/tests/
H A Dvc4_mock.c183 vc4->hvs = __vc4_hvs_alloc(vc4, NULL); in __mock_device()
184 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, vc4->hvs); in __mock_device()
H A Dvc4_test_pv_muxing.c849 * This test makes sure that we never change the FIFO of an active HVS
/openbmc/linux/tools/testing/selftests/net/
H A Dtest_vxlan_under_vrf.sh7 # two for the HVs, two for the VMs.
88 # Check connectivity between HVs by pinging hv-2 from hv-1
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711-rpi.dtsi52 &hvs {
H A Dbcm283x.dtsi431 hvs@7e400000 {
432 compatible = "brcm,bcm2835-hvs";
H A Dbcm2711.dtsi292 hvs: hvs@7e400000 { label
293 compatible = "brcm,bcm2711-hvs";
/openbmc/linux/Documentation/virt/hyperv/
H A Dclocks.rst67 timer 0. Interrupts from stimer0 are recorded on the "HVS" line in
/openbmc/linux/drivers/clk/bcm/
H A Dclk-raspberrypi.c76 * The clock is shared between the HVS and the CSI
78 * on the pixels composited on the HVS and the capture
/openbmc/u-boot/arch/arm/dts/
H A Dbcm283x.dtsi515 hvs@7e400000 {
516 compatible = "brcm,bcm2835-hvs";
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_vfpf.h29 /* Common definitions for all HVs */
/openbmc/linux/drivers/media/i2c/
H A Dimx274.c230 {0x3018, 0xA2}, /* output XVS, HVS */
271 {0x3018, 0xA2}, /* output XVS, HVS */
311 {0x3018, 0xA2}, /* output XVS, HVS */
351 {0x3018, 0xA2}, /* output XVS, HVS */
/openbmc/linux/arch/x86/kernel/
H A Dirq.c156 seq_printf(p, "%*s: ", prec, "HVS"); in arch_show_interrupts()
/openbmc/openbmc/meta-raspberrypi/dynamic-layers/multimedia-layer/recipes-multimedia/rpidistro-vlc/files/
H A D0004-mmal_20.patch580 +#define MMAL_RESIZE_TEXT N_("Use mmal resizer rather than hvs.")
584 +#define MMAL_ISP_TEXT N_("Use mmal isp rather than hvs.")
585 +#define MMAL_ISP_LONGTEXT N_("Use mmal isp rather than hvs. This may be faster but has no blend.")
2342 + // HVS can take new formats without disable, others need it
2702 + // Must use ISP - HVS can't do this, nor can resizer
2707 + // otherwise downgrade HVS to ISP
2710 + // HVS can't do I420
2714 + // Only HVS can deal with SAND30
2739 + use_resizer ? "resize" : use_isp ? "isp" : "hvs",
2799 + msg_Warn(p_filter, "Failed to rcreate HVS resizer - retrying with ISP");
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