xref: /openbmc/linux/drivers/media/i2c/imx274.c (revision aaeb31c0)
1e6002df8SLuca Ceresoli // SPDX-License-Identifier: GPL-2.0
20985dd30SLeon Luo /*
30985dd30SLeon Luo  * imx274.c - IMX274 CMOS Image Sensor driver
40985dd30SLeon Luo  *
50985dd30SLeon Luo  * Copyright (C) 2017, Leopard Imaging, Inc.
60985dd30SLeon Luo  *
70985dd30SLeon Luo  * Leon Luo <leonl@leopardimaging.com>
80985dd30SLeon Luo  * Edwin Zou <edwinz@leopardimaging.com>
939dd23dcSLuca Ceresoli  * Luca Ceresoli <luca@lucaceresoli.net>
100985dd30SLeon Luo  */
110985dd30SLeon Luo 
120985dd30SLeon Luo #include <linux/clk.h>
130985dd30SLeon Luo #include <linux/delay.h>
140985dd30SLeon Luo #include <linux/gpio/consumer.h>
150985dd30SLeon Luo #include <linux/i2c.h>
160985dd30SLeon Luo #include <linux/init.h>
1739dd23dcSLuca Ceresoli #include <linux/kernel.h>
180985dd30SLeon Luo #include <linux/module.h>
19ad97bc37SSowjanya Komatineni #include <linux/pm_runtime.h>
200985dd30SLeon Luo #include <linux/regmap.h>
21ad97bc37SSowjanya Komatineni #include <linux/regulator/consumer.h>
220985dd30SLeon Luo #include <linux/slab.h>
230985dd30SLeon Luo #include <linux/v4l2-mediabus.h>
240985dd30SLeon Luo #include <linux/videodev2.h>
250985dd30SLeon Luo 
260985dd30SLeon Luo #include <media/v4l2-ctrls.h>
270985dd30SLeon Luo #include <media/v4l2-device.h>
280abb8f90SEugen Hristev #include <media/v4l2-fwnode.h>
290985dd30SLeon Luo #include <media/v4l2-subdev.h>
300985dd30SLeon Luo 
310985dd30SLeon Luo /*
320985dd30SLeon Luo  * See "SHR, SVR Setting" in datasheet
330985dd30SLeon Luo  */
340985dd30SLeon Luo #define IMX274_DEFAULT_FRAME_LENGTH		(4550)
350985dd30SLeon Luo #define IMX274_MAX_FRAME_LENGTH			(0x000fffff)
360985dd30SLeon Luo 
370985dd30SLeon Luo /*
380985dd30SLeon Luo  * See "Frame Rate Adjustment" in datasheet
390985dd30SLeon Luo  */
400985dd30SLeon Luo #define IMX274_PIXCLK_CONST1			(72000000)
410985dd30SLeon Luo #define IMX274_PIXCLK_CONST2			(1000000)
420985dd30SLeon Luo 
430985dd30SLeon Luo /*
440985dd30SLeon Luo  * The input gain is shifted by IMX274_GAIN_SHIFT to get
450985dd30SLeon Luo  * decimal number. The real gain is
460985dd30SLeon Luo  * (float)input_gain_value / (1 << IMX274_GAIN_SHIFT)
470985dd30SLeon Luo  */
480985dd30SLeon Luo #define IMX274_GAIN_SHIFT			(8)
490985dd30SLeon Luo #define IMX274_GAIN_SHIFT_MASK			((1 << IMX274_GAIN_SHIFT) - 1)
500985dd30SLeon Luo 
510985dd30SLeon Luo /*
520985dd30SLeon Luo  * See "Analog Gain" and "Digital Gain" in datasheet
530985dd30SLeon Luo  * min gain is 1X
540985dd30SLeon Luo  * max gain is calculated based on IMX274_GAIN_REG_MAX
550985dd30SLeon Luo  */
560985dd30SLeon Luo #define IMX274_GAIN_REG_MAX			(1957)
570985dd30SLeon Luo #define IMX274_MIN_GAIN				(0x01 << IMX274_GAIN_SHIFT)
580985dd30SLeon Luo #define IMX274_MAX_ANALOG_GAIN			((2048 << IMX274_GAIN_SHIFT)\
590985dd30SLeon Luo 					/ (2048 - IMX274_GAIN_REG_MAX))
600985dd30SLeon Luo #define IMX274_MAX_DIGITAL_GAIN			(8)
610985dd30SLeon Luo #define IMX274_DEF_GAIN				(20 << IMX274_GAIN_SHIFT)
620985dd30SLeon Luo #define IMX274_GAIN_CONST			(2048) /* for gain formula */
630985dd30SLeon Luo 
640985dd30SLeon Luo /*
650985dd30SLeon Luo  * 1 line time in us = (HMAX / 72), minimal is 4 lines
660985dd30SLeon Luo  */
670985dd30SLeon Luo #define IMX274_MIN_EXPOSURE_TIME		(4 * 260 / 72)
680985dd30SLeon Luo 
690985dd30SLeon Luo #define IMX274_MAX_WIDTH			(3840)
700985dd30SLeon Luo #define IMX274_MAX_HEIGHT			(2160)
710985dd30SLeon Luo #define IMX274_MAX_FRAME_RATE			(120)
720985dd30SLeon Luo #define IMX274_MIN_FRAME_RATE			(5)
730985dd30SLeon Luo #define IMX274_DEF_FRAME_RATE			(60)
740985dd30SLeon Luo 
750985dd30SLeon Luo /*
760985dd30SLeon Luo  * register SHR is limited to (SVR value + 1) x VMAX value - 4
770985dd30SLeon Luo  */
780985dd30SLeon Luo #define IMX274_SHR_LIMIT_CONST			(4)
790985dd30SLeon Luo 
800985dd30SLeon Luo /*
814c858e96SLuca Ceresoli  * Min and max sensor reset delay (microseconds)
820985dd30SLeon Luo  */
830985dd30SLeon Luo #define IMX274_RESET_DELAY1			(2000)
840985dd30SLeon Luo #define IMX274_RESET_DELAY2			(2200)
850985dd30SLeon Luo 
860985dd30SLeon Luo /*
870985dd30SLeon Luo  * shift and mask constants
880985dd30SLeon Luo  */
890985dd30SLeon Luo #define IMX274_SHIFT_8_BITS			(8)
900985dd30SLeon Luo #define IMX274_SHIFT_16_BITS			(16)
910985dd30SLeon Luo #define IMX274_MASK_LSB_2_BITS			(0x03)
920985dd30SLeon Luo #define IMX274_MASK_LSB_3_BITS			(0x07)
930985dd30SLeon Luo #define IMX274_MASK_LSB_4_BITS			(0x0f)
940985dd30SLeon Luo #define IMX274_MASK_LSB_8_BITS			(0x00ff)
950985dd30SLeon Luo 
960985dd30SLeon Luo #define DRIVER_NAME "IMX274"
970985dd30SLeon Luo 
980985dd30SLeon Luo /*
990985dd30SLeon Luo  * IMX274 register definitions
1000985dd30SLeon Luo  */
1014eb7846dSLuca Ceresoli #define IMX274_SHR_REG_MSB			0x300D /* SHR */
1024eb7846dSLuca Ceresoli #define IMX274_SHR_REG_LSB			0x300C /* SHR */
1030985dd30SLeon Luo #define IMX274_SVR_REG_MSB			0x300F /* SVR */
1040985dd30SLeon Luo #define IMX274_SVR_REG_LSB			0x300E /* SVR */
10539dd23dcSLuca Ceresoli #define IMX274_HTRIM_EN_REG			0x3037
10639dd23dcSLuca Ceresoli #define IMX274_HTRIM_START_REG_LSB		0x3038
10739dd23dcSLuca Ceresoli #define IMX274_HTRIM_START_REG_MSB		0x3039
10839dd23dcSLuca Ceresoli #define IMX274_HTRIM_END_REG_LSB		0x303A
10939dd23dcSLuca Ceresoli #define IMX274_HTRIM_END_REG_MSB		0x303B
11039dd23dcSLuca Ceresoli #define IMX274_VWIDCUTEN_REG			0x30DD
11139dd23dcSLuca Ceresoli #define IMX274_VWIDCUT_REG_LSB			0x30DE
11239dd23dcSLuca Ceresoli #define IMX274_VWIDCUT_REG_MSB			0x30DF
11339dd23dcSLuca Ceresoli #define IMX274_VWINPOS_REG_LSB			0x30E0
11439dd23dcSLuca Ceresoli #define IMX274_VWINPOS_REG_MSB			0x30E1
11539dd23dcSLuca Ceresoli #define IMX274_WRITE_VSIZE_REG_LSB		0x3130
11639dd23dcSLuca Ceresoli #define IMX274_WRITE_VSIZE_REG_MSB		0x3131
11739dd23dcSLuca Ceresoli #define IMX274_Y_OUT_SIZE_REG_LSB		0x3132
11839dd23dcSLuca Ceresoli #define IMX274_Y_OUT_SIZE_REG_MSB		0x3133
1194eb7846dSLuca Ceresoli #define IMX274_VMAX_REG_1			0x30FA /* VMAX, MSB */
1204eb7846dSLuca Ceresoli #define IMX274_VMAX_REG_2			0x30F9 /* VMAX */
1214eb7846dSLuca Ceresoli #define IMX274_VMAX_REG_3			0x30F8 /* VMAX, LSB */
1220985dd30SLeon Luo #define IMX274_HMAX_REG_MSB			0x30F7 /* HMAX */
1230985dd30SLeon Luo #define IMX274_HMAX_REG_LSB			0x30F6 /* HMAX */
1240985dd30SLeon Luo #define IMX274_ANALOG_GAIN_ADDR_LSB		0x300A /* ANALOG GAIN LSB */
1250985dd30SLeon Luo #define IMX274_ANALOG_GAIN_ADDR_MSB		0x300B /* ANALOG GAIN MSB */
1260985dd30SLeon Luo #define IMX274_DIGITAL_GAIN_REG			0x3012 /* Digital Gain */
1270985dd30SLeon Luo #define IMX274_VFLIP_REG			0x301A /* VERTICAL FLIP */
1280985dd30SLeon Luo #define IMX274_TEST_PATTERN_REG			0x303D /* TEST PATTERN */
1290985dd30SLeon Luo #define IMX274_STANDBY_REG			0x3000 /* STANDBY */
1300985dd30SLeon Luo 
1310985dd30SLeon Luo #define IMX274_TABLE_WAIT_MS			0
1320985dd30SLeon Luo #define IMX274_TABLE_END			1
1330985dd30SLeon Luo 
134ad97bc37SSowjanya Komatineni /* regulator supplies */
135ad97bc37SSowjanya Komatineni static const char * const imx274_supply_names[] = {
136ad97bc37SSowjanya Komatineni 	"vddl",  /* IF (1.2V) supply */
137ad97bc37SSowjanya Komatineni 	"vdig",  /* Digital Core (1.8V) supply */
138ad97bc37SSowjanya Komatineni 	"vana",  /* Analog (2.8V) supply */
139ad97bc37SSowjanya Komatineni };
140ad97bc37SSowjanya Komatineni 
141ad97bc37SSowjanya Komatineni #define IMX274_NUM_SUPPLIES ARRAY_SIZE(imx274_supply_names)
142ad97bc37SSowjanya Komatineni 
1430985dd30SLeon Luo /*
1440985dd30SLeon Luo  * imx274 I2C operation related structure
1450985dd30SLeon Luo  */
1460985dd30SLeon Luo struct reg_8 {
1470985dd30SLeon Luo 	u16 addr;
1480985dd30SLeon Luo 	u8 val;
1490985dd30SLeon Luo };
1500985dd30SLeon Luo 
1510985dd30SLeon Luo static const struct regmap_config imx274_regmap_config = {
1520985dd30SLeon Luo 	.reg_bits = 16,
1530985dd30SLeon Luo 	.val_bits = 8,
1540985dd30SLeon Luo 	.cache_type = REGCACHE_RBTREE,
1550985dd30SLeon Luo };
1560985dd30SLeon Luo 
1570985dd30SLeon Luo /*
15896a2c731SLuca Ceresoli  * Parameters for each imx274 readout mode.
15996a2c731SLuca Ceresoli  *
16096a2c731SLuca Ceresoli  * These are the values to configure the sensor in one of the
16196a2c731SLuca Ceresoli  * implemented modes.
16296a2c731SLuca Ceresoli  *
16396a2c731SLuca Ceresoli  * @init_regs: registers to initialize the mode
164f70ad2acSEugen Hristev  * @wbin_ratio: width downscale factor (e.g. 3 for 1280; 3 = 3840/1280)
165f70ad2acSEugen Hristev  * @hbin_ratio: height downscale factor (e.g. 3 for 720; 3 = 2160/720)
16696a2c731SLuca Ceresoli  * @min_frame_len: Minimum frame length for each mode (see "Frame Rate
16796a2c731SLuca Ceresoli  *                 Adjustment (CSI-2)" in the datasheet)
16896a2c731SLuca Ceresoli  * @min_SHR: Minimum SHR register value (see "Shutter Setting (CSI-2)" in the
16996a2c731SLuca Ceresoli  *           datasheet)
17096a2c731SLuca Ceresoli  * @max_fps: Maximum frames per second
17196a2c731SLuca Ceresoli  * @nocpiop: Number of clocks per internal offset period (see "Integration Time
17296a2c731SLuca Ceresoli  *           in Each Readout Drive Mode (CSI-2)" in the datasheet)
1730985dd30SLeon Luo  */
1749648cb57SLuca Ceresoli struct imx274_mode {
17596a2c731SLuca Ceresoli 	const struct reg_8 *init_regs;
176f70ad2acSEugen Hristev 	u8 wbin_ratio;
177f70ad2acSEugen Hristev 	u8 hbin_ratio;
17896a2c731SLuca Ceresoli 	int min_frame_len;
17996a2c731SLuca Ceresoli 	int min_SHR;
18096a2c731SLuca Ceresoli 	int max_fps;
18196a2c731SLuca Ceresoli 	int nocpiop;
1820985dd30SLeon Luo };
1830985dd30SLeon Luo 
1840985dd30SLeon Luo /*
1850985dd30SLeon Luo  * imx274 test pattern related structure
1860985dd30SLeon Luo  */
1870985dd30SLeon Luo enum {
1880985dd30SLeon Luo 	TEST_PATTERN_DISABLED = 0,
1890985dd30SLeon Luo 	TEST_PATTERN_ALL_000H,
1900985dd30SLeon Luo 	TEST_PATTERN_ALL_FFFH,
1910985dd30SLeon Luo 	TEST_PATTERN_ALL_555H,
1920985dd30SLeon Luo 	TEST_PATTERN_ALL_AAAH,
1930985dd30SLeon Luo 	TEST_PATTERN_VSP_5AH, /* VERTICAL STRIPE PATTERN 555H/AAAH */
1940985dd30SLeon Luo 	TEST_PATTERN_VSP_A5H, /* VERTICAL STRIPE PATTERN AAAH/555H */
1950985dd30SLeon Luo 	TEST_PATTERN_VSP_05H, /* VERTICAL STRIPE PATTERN 000H/555H */
1960985dd30SLeon Luo 	TEST_PATTERN_VSP_50H, /* VERTICAL STRIPE PATTERN 555H/000H */
1970985dd30SLeon Luo 	TEST_PATTERN_VSP_0FH, /* VERTICAL STRIPE PATTERN 000H/FFFH */
1980985dd30SLeon Luo 	TEST_PATTERN_VSP_F0H, /* VERTICAL STRIPE PATTERN FFFH/000H */
1990985dd30SLeon Luo 	TEST_PATTERN_H_COLOR_BARS,
2000985dd30SLeon Luo 	TEST_PATTERN_V_COLOR_BARS,
2010985dd30SLeon Luo };
2020985dd30SLeon Luo 
2030985dd30SLeon Luo static const char * const tp_qmenu[] = {
2040985dd30SLeon Luo 	"Disabled",
2050985dd30SLeon Luo 	"All 000h Pattern",
2060985dd30SLeon Luo 	"All FFFh Pattern",
2070985dd30SLeon Luo 	"All 555h Pattern",
2080985dd30SLeon Luo 	"All AAAh Pattern",
2090985dd30SLeon Luo 	"Vertical Stripe (555h / AAAh)",
2100985dd30SLeon Luo 	"Vertical Stripe (AAAh / 555h)",
2110985dd30SLeon Luo 	"Vertical Stripe (000h / 555h)",
2120985dd30SLeon Luo 	"Vertical Stripe (555h / 000h)",
2130985dd30SLeon Luo 	"Vertical Stripe (000h / FFFh)",
2140985dd30SLeon Luo 	"Vertical Stripe (FFFh / 000h)",
2150985dd30SLeon Luo 	"Vertical Color Bars",
21647ee7bdeSLuca Ceresoli 	"Horizontal Color Bars",
2170985dd30SLeon Luo };
2180985dd30SLeon Luo 
2190985dd30SLeon Luo /*
2200985dd30SLeon Luo  * All-pixel scan mode (10-bit)
2210985dd30SLeon Luo  * imx274 mode1(refer to datasheet) register configuration with
2220985dd30SLeon Luo  * 3840x2160 resolution, raw10 data and mipi four lane output
2230985dd30SLeon Luo  */
2240985dd30SLeon Luo static const struct reg_8 imx274_mode1_3840x2160_raw10[] = {
2250985dd30SLeon Luo 	{0x3004, 0x01},
2260985dd30SLeon Luo 	{0x3005, 0x01},
2270985dd30SLeon Luo 	{0x3006, 0x00},
22839dd23dcSLuca Ceresoli 	{0x3007, 0xa2},
2290985dd30SLeon Luo 
2300985dd30SLeon Luo 	{0x3018, 0xA2}, /* output XVS, HVS */
2310985dd30SLeon Luo 
2320985dd30SLeon Luo 	{0x306B, 0x05},
2330985dd30SLeon Luo 	{0x30E2, 0x01},
2340985dd30SLeon Luo 
2350985dd30SLeon Luo 	{0x30EE, 0x01},
2360985dd30SLeon Luo 	{0x3342, 0x0A},
2370985dd30SLeon Luo 	{0x3343, 0x00},
2380985dd30SLeon Luo 	{0x3344, 0x16},
2390985dd30SLeon Luo 	{0x3345, 0x00},
2400985dd30SLeon Luo 	{0x33A6, 0x01},
2410985dd30SLeon Luo 	{0x3528, 0x0E},
2420985dd30SLeon Luo 	{0x3554, 0x1F},
2430985dd30SLeon Luo 	{0x3555, 0x01},
2440985dd30SLeon Luo 	{0x3556, 0x01},
2450985dd30SLeon Luo 	{0x3557, 0x01},
2460985dd30SLeon Luo 	{0x3558, 0x01},
2470985dd30SLeon Luo 	{0x3559, 0x00},
2480985dd30SLeon Luo 	{0x355A, 0x00},
2490985dd30SLeon Luo 	{0x35BA, 0x0E},
2500985dd30SLeon Luo 	{0x366A, 0x1B},
2510985dd30SLeon Luo 	{0x366B, 0x1A},
2520985dd30SLeon Luo 	{0x366C, 0x19},
2530985dd30SLeon Luo 	{0x366D, 0x17},
2540985dd30SLeon Luo 	{0x3A41, 0x08},
2550985dd30SLeon Luo 
2560985dd30SLeon Luo 	{IMX274_TABLE_END, 0x00}
2570985dd30SLeon Luo };
2580985dd30SLeon Luo 
2590985dd30SLeon Luo /*
2600985dd30SLeon Luo  * Horizontal/vertical 2/2-line binning
2610985dd30SLeon Luo  * (Horizontal and vertical weightedbinning, 10-bit)
2620985dd30SLeon Luo  * imx274 mode3(refer to datasheet) register configuration with
2630985dd30SLeon Luo  * 1920x1080 resolution, raw10 data and mipi four lane output
2640985dd30SLeon Luo  */
2650985dd30SLeon Luo static const struct reg_8 imx274_mode3_1920x1080_raw10[] = {
2660985dd30SLeon Luo 	{0x3004, 0x02},
2670985dd30SLeon Luo 	{0x3005, 0x21},
2680985dd30SLeon Luo 	{0x3006, 0x00},
26939dd23dcSLuca Ceresoli 	{0x3007, 0xb1},
2700985dd30SLeon Luo 
2710985dd30SLeon Luo 	{0x3018, 0xA2}, /* output XVS, HVS */
2720985dd30SLeon Luo 
2730985dd30SLeon Luo 	{0x306B, 0x05},
2740985dd30SLeon Luo 	{0x30E2, 0x02},
2750985dd30SLeon Luo 
2760985dd30SLeon Luo 	{0x30EE, 0x01},
2770985dd30SLeon Luo 	{0x3342, 0x0A},
2780985dd30SLeon Luo 	{0x3343, 0x00},
2790985dd30SLeon Luo 	{0x3344, 0x1A},
2800985dd30SLeon Luo 	{0x3345, 0x00},
2810985dd30SLeon Luo 	{0x33A6, 0x01},
2820985dd30SLeon Luo 	{0x3528, 0x0E},
2830985dd30SLeon Luo 	{0x3554, 0x00},
2840985dd30SLeon Luo 	{0x3555, 0x01},
2850985dd30SLeon Luo 	{0x3556, 0x01},
2860985dd30SLeon Luo 	{0x3557, 0x01},
2870985dd30SLeon Luo 	{0x3558, 0x01},
2880985dd30SLeon Luo 	{0x3559, 0x00},
2890985dd30SLeon Luo 	{0x355A, 0x00},
2900985dd30SLeon Luo 	{0x35BA, 0x0E},
2910985dd30SLeon Luo 	{0x366A, 0x1B},
2920985dd30SLeon Luo 	{0x366B, 0x1A},
2930985dd30SLeon Luo 	{0x366C, 0x19},
2940985dd30SLeon Luo 	{0x366D, 0x17},
2950985dd30SLeon Luo 	{0x3A41, 0x08},
2960985dd30SLeon Luo 
2970985dd30SLeon Luo 	{IMX274_TABLE_END, 0x00}
2980985dd30SLeon Luo };
2990985dd30SLeon Luo 
3000985dd30SLeon Luo /*
3010985dd30SLeon Luo  * Vertical 2/3 subsampling binning horizontal 3 binning
3020985dd30SLeon Luo  * imx274 mode5(refer to datasheet) register configuration with
3030985dd30SLeon Luo  * 1280x720 resolution, raw10 data and mipi four lane output
3040985dd30SLeon Luo  */
3050985dd30SLeon Luo static const struct reg_8 imx274_mode5_1280x720_raw10[] = {
3060985dd30SLeon Luo 	{0x3004, 0x03},
3070985dd30SLeon Luo 	{0x3005, 0x31},
3080985dd30SLeon Luo 	{0x3006, 0x00},
30939dd23dcSLuca Ceresoli 	{0x3007, 0xa9},
3100985dd30SLeon Luo 
3110985dd30SLeon Luo 	{0x3018, 0xA2}, /* output XVS, HVS */
3120985dd30SLeon Luo 
3130985dd30SLeon Luo 	{0x306B, 0x05},
3140985dd30SLeon Luo 	{0x30E2, 0x03},
3150985dd30SLeon Luo 
3160985dd30SLeon Luo 	{0x30EE, 0x01},
3170985dd30SLeon Luo 	{0x3342, 0x0A},
3180985dd30SLeon Luo 	{0x3343, 0x00},
3190985dd30SLeon Luo 	{0x3344, 0x1B},
3200985dd30SLeon Luo 	{0x3345, 0x00},
3210985dd30SLeon Luo 	{0x33A6, 0x01},
3220985dd30SLeon Luo 	{0x3528, 0x0E},
3230985dd30SLeon Luo 	{0x3554, 0x00},
3240985dd30SLeon Luo 	{0x3555, 0x01},
3250985dd30SLeon Luo 	{0x3556, 0x01},
3260985dd30SLeon Luo 	{0x3557, 0x01},
3270985dd30SLeon Luo 	{0x3558, 0x01},
3280985dd30SLeon Luo 	{0x3559, 0x00},
3290985dd30SLeon Luo 	{0x355A, 0x00},
3300985dd30SLeon Luo 	{0x35BA, 0x0E},
3310985dd30SLeon Luo 	{0x366A, 0x1B},
3320985dd30SLeon Luo 	{0x366B, 0x19},
3330985dd30SLeon Luo 	{0x366C, 0x17},
3340985dd30SLeon Luo 	{0x366D, 0x17},
3350985dd30SLeon Luo 	{0x3A41, 0x04},
3360985dd30SLeon Luo 
3370985dd30SLeon Luo 	{IMX274_TABLE_END, 0x00}
3380985dd30SLeon Luo };
3390985dd30SLeon Luo 
3400985dd30SLeon Luo /*
341f70ad2acSEugen Hristev  * Vertical 2/8 subsampling horizontal 3 binning
342f70ad2acSEugen Hristev  * imx274 mode6(refer to datasheet) register configuration with
343f70ad2acSEugen Hristev  * 1280x540 resolution, raw10 data and mipi four lane output
344f70ad2acSEugen Hristev  */
345f70ad2acSEugen Hristev static const struct reg_8 imx274_mode6_1280x540_raw10[] = {
346f70ad2acSEugen Hristev 	{0x3004, 0x04}, /* mode setting */
347f70ad2acSEugen Hristev 	{0x3005, 0x31},
348f70ad2acSEugen Hristev 	{0x3006, 0x00},
349f70ad2acSEugen Hristev 	{0x3007, 0x02}, /* mode setting */
350f70ad2acSEugen Hristev 
351f70ad2acSEugen Hristev 	{0x3018, 0xA2}, /* output XVS, HVS */
352f70ad2acSEugen Hristev 
353f70ad2acSEugen Hristev 	{0x306B, 0x05},
354f70ad2acSEugen Hristev 	{0x30E2, 0x04}, /* mode setting */
355f70ad2acSEugen Hristev 
356f70ad2acSEugen Hristev 	{0x30EE, 0x01},
357f70ad2acSEugen Hristev 	{0x3342, 0x0A},
358f70ad2acSEugen Hristev 	{0x3343, 0x00},
359f70ad2acSEugen Hristev 	{0x3344, 0x16},
360f70ad2acSEugen Hristev 	{0x3345, 0x00},
361f70ad2acSEugen Hristev 	{0x33A6, 0x01},
362f70ad2acSEugen Hristev 	{0x3528, 0x0E},
363f70ad2acSEugen Hristev 	{0x3554, 0x1F},
364f70ad2acSEugen Hristev 	{0x3555, 0x01},
365f70ad2acSEugen Hristev 	{0x3556, 0x01},
366f70ad2acSEugen Hristev 	{0x3557, 0x01},
367f70ad2acSEugen Hristev 	{0x3558, 0x01},
368f70ad2acSEugen Hristev 	{0x3559, 0x00},
369f70ad2acSEugen Hristev 	{0x355A, 0x00},
370f70ad2acSEugen Hristev 	{0x35BA, 0x0E},
371f70ad2acSEugen Hristev 	{0x366A, 0x1B},
372f70ad2acSEugen Hristev 	{0x366B, 0x1A},
373f70ad2acSEugen Hristev 	{0x366C, 0x19},
374f70ad2acSEugen Hristev 	{0x366D, 0x17},
375f70ad2acSEugen Hristev 	{0x3A41, 0x04},
376f70ad2acSEugen Hristev 
377f70ad2acSEugen Hristev 	{IMX274_TABLE_END, 0x00}
378f70ad2acSEugen Hristev };
379f70ad2acSEugen Hristev 
380f70ad2acSEugen Hristev /*
3810985dd30SLeon Luo  * imx274 first step register configuration for
3820985dd30SLeon Luo  * starting stream
3830985dd30SLeon Luo  */
3840985dd30SLeon Luo static const struct reg_8 imx274_start_1[] = {
3850985dd30SLeon Luo 	{IMX274_STANDBY_REG, 0x12},
3860985dd30SLeon Luo 
3877d2332c7SLuca Ceresoli 	/* PLRD: clock settings */
3887d2332c7SLuca Ceresoli 	{0x3120, 0xF0},
3897d2332c7SLuca Ceresoli 	{0x3121, 0x00},
3907d2332c7SLuca Ceresoli 	{0x3122, 0x02},
3917d2332c7SLuca Ceresoli 	{0x3129, 0x9C},
3927d2332c7SLuca Ceresoli 	{0x312A, 0x02},
3937d2332c7SLuca Ceresoli 	{0x312D, 0x02},
3940985dd30SLeon Luo 
3950985dd30SLeon Luo 	{0x310B, 0x00},
3960985dd30SLeon Luo 
3970985dd30SLeon Luo 	/* PLSTMG */
3980985dd30SLeon Luo 	{0x304C, 0x00}, /* PLSTMG01 */
3990985dd30SLeon Luo 	{0x304D, 0x03},
4000985dd30SLeon Luo 	{0x331C, 0x1A},
4010985dd30SLeon Luo 	{0x331D, 0x00},
4020985dd30SLeon Luo 	{0x3502, 0x02},
4030985dd30SLeon Luo 	{0x3529, 0x0E},
4040985dd30SLeon Luo 	{0x352A, 0x0E},
4050985dd30SLeon Luo 	{0x352B, 0x0E},
4060985dd30SLeon Luo 	{0x3538, 0x0E},
4070985dd30SLeon Luo 	{0x3539, 0x0E},
4080985dd30SLeon Luo 	{0x3553, 0x00},
4090985dd30SLeon Luo 	{0x357D, 0x05},
4100985dd30SLeon Luo 	{0x357F, 0x05},
4110985dd30SLeon Luo 	{0x3581, 0x04},
4120985dd30SLeon Luo 	{0x3583, 0x76},
4130985dd30SLeon Luo 	{0x3587, 0x01},
4140985dd30SLeon Luo 	{0x35BB, 0x0E},
4150985dd30SLeon Luo 	{0x35BC, 0x0E},
4160985dd30SLeon Luo 	{0x35BD, 0x0E},
4170985dd30SLeon Luo 	{0x35BE, 0x0E},
4180985dd30SLeon Luo 	{0x35BF, 0x0E},
4190985dd30SLeon Luo 	{0x366E, 0x00},
4200985dd30SLeon Luo 	{0x366F, 0x00},
4210985dd30SLeon Luo 	{0x3670, 0x00},
4220985dd30SLeon Luo 	{0x3671, 0x00},
4230985dd30SLeon Luo 
4240985dd30SLeon Luo 	/* PSMIPI */
4250985dd30SLeon Luo 	{0x3304, 0x32}, /* PSMIPI1 */
4260985dd30SLeon Luo 	{0x3305, 0x00},
4270985dd30SLeon Luo 	{0x3306, 0x32},
4280985dd30SLeon Luo 	{0x3307, 0x00},
4290985dd30SLeon Luo 	{0x3590, 0x32},
4300985dd30SLeon Luo 	{0x3591, 0x00},
4310985dd30SLeon Luo 	{0x3686, 0x32},
4320985dd30SLeon Luo 	{0x3687, 0x00},
4330985dd30SLeon Luo 
4340985dd30SLeon Luo 	{IMX274_TABLE_END, 0x00}
4350985dd30SLeon Luo };
4360985dd30SLeon Luo 
4370985dd30SLeon Luo /*
4387d2332c7SLuca Ceresoli  * imx274 second step register configuration for
4390985dd30SLeon Luo  * starting stream
4400985dd30SLeon Luo  */
4417d2332c7SLuca Ceresoli static const struct reg_8 imx274_start_2[] = {
4420985dd30SLeon Luo 	{IMX274_STANDBY_REG, 0x00},
4430985dd30SLeon Luo 	{0x303E, 0x02}, /* SYS_MODE = 2 */
4440985dd30SLeon Luo 	{IMX274_TABLE_END, 0x00}
4450985dd30SLeon Luo };
4460985dd30SLeon Luo 
4470985dd30SLeon Luo /*
4487d2332c7SLuca Ceresoli  * imx274 third step register configuration for
4490985dd30SLeon Luo  * starting stream
4500985dd30SLeon Luo  */
4517d2332c7SLuca Ceresoli static const struct reg_8 imx274_start_3[] = {
4520985dd30SLeon Luo 	{0x30F4, 0x00},
453f8a7647dSMauro Carvalho Chehab 	{0x3018, 0xA2}, /* XHS VHS OUTPUT */
4540985dd30SLeon Luo 	{IMX274_TABLE_END, 0x00}
4550985dd30SLeon Luo };
4560985dd30SLeon Luo 
4570985dd30SLeon Luo /*
458f8a7647dSMauro Carvalho Chehab  * imx274 register configuration for stopping stream
4590985dd30SLeon Luo  */
4600985dd30SLeon Luo static const struct reg_8 imx274_stop[] = {
4610985dd30SLeon Luo 	{IMX274_STANDBY_REG, 0x01},
4620985dd30SLeon Luo 	{IMX274_TABLE_END, 0x00}
4630985dd30SLeon Luo };
4640985dd30SLeon Luo 
4650985dd30SLeon Luo /*
4660985dd30SLeon Luo  * imx274 disable test pattern register configuration
4670985dd30SLeon Luo  */
4680985dd30SLeon Luo static const struct reg_8 imx274_tp_disabled[] = {
4690985dd30SLeon Luo 	{0x303C, 0x00},
4700985dd30SLeon Luo 	{0x377F, 0x00},
4710985dd30SLeon Luo 	{0x3781, 0x00},
4720985dd30SLeon Luo 	{0x370B, 0x00},
4730985dd30SLeon Luo 	{IMX274_TABLE_END, 0x00}
4740985dd30SLeon Luo };
4750985dd30SLeon Luo 
4760985dd30SLeon Luo /*
4770985dd30SLeon Luo  * imx274 test pattern register configuration
4780985dd30SLeon Luo  * reg 0x303D defines the test pattern modes
4790985dd30SLeon Luo  */
4800985dd30SLeon Luo static const struct reg_8 imx274_tp_regs[] = {
4810985dd30SLeon Luo 	{0x303C, 0x11},
4820985dd30SLeon Luo 	{0x370E, 0x01},
4830985dd30SLeon Luo 	{0x377F, 0x01},
4840985dd30SLeon Luo 	{0x3781, 0x01},
4850985dd30SLeon Luo 	{0x370B, 0x11},
4860985dd30SLeon Luo 	{IMX274_TABLE_END, 0x00}
4870985dd30SLeon Luo };
4880985dd30SLeon Luo 
48996a2c731SLuca Ceresoli /* nocpiop happens to be the same number for the implemented modes */
4909648cb57SLuca Ceresoli static const struct imx274_mode imx274_modes[] = {
49196a2c731SLuca Ceresoli 	{
49296a2c731SLuca Ceresoli 		/* mode 1, 4K */
493f70ad2acSEugen Hristev 		.wbin_ratio = 1, /* 3840 */
494f70ad2acSEugen Hristev 		.hbin_ratio = 1, /* 2160 */
49596a2c731SLuca Ceresoli 		.init_regs = imx274_mode1_3840x2160_raw10,
49696a2c731SLuca Ceresoli 		.min_frame_len = 4550,
49796a2c731SLuca Ceresoli 		.min_SHR = 12,
49896a2c731SLuca Ceresoli 		.max_fps = 60,
49996a2c731SLuca Ceresoli 		.nocpiop = 112,
50096a2c731SLuca Ceresoli 	},
50196a2c731SLuca Ceresoli 	{
50296a2c731SLuca Ceresoli 		/* mode 3, 1080p */
503f70ad2acSEugen Hristev 		.wbin_ratio = 2, /* 1920 */
504f70ad2acSEugen Hristev 		.hbin_ratio = 2, /* 1080 */
50596a2c731SLuca Ceresoli 		.init_regs = imx274_mode3_1920x1080_raw10,
50696a2c731SLuca Ceresoli 		.min_frame_len = 2310,
50796a2c731SLuca Ceresoli 		.min_SHR = 8,
50896a2c731SLuca Ceresoli 		.max_fps = 120,
50996a2c731SLuca Ceresoli 		.nocpiop = 112,
51096a2c731SLuca Ceresoli 	},
51196a2c731SLuca Ceresoli 	{
51296a2c731SLuca Ceresoli 		/* mode 5, 720p */
513f70ad2acSEugen Hristev 		.wbin_ratio = 3, /* 1280 */
514f70ad2acSEugen Hristev 		.hbin_ratio = 3, /* 720 */
51596a2c731SLuca Ceresoli 		.init_regs = imx274_mode5_1280x720_raw10,
51696a2c731SLuca Ceresoli 		.min_frame_len = 2310,
51796a2c731SLuca Ceresoli 		.min_SHR = 8,
51896a2c731SLuca Ceresoli 		.max_fps = 120,
51996a2c731SLuca Ceresoli 		.nocpiop = 112,
52096a2c731SLuca Ceresoli 	},
521f70ad2acSEugen Hristev 	{
522f70ad2acSEugen Hristev 		/* mode 6, 540p */
523f70ad2acSEugen Hristev 		.wbin_ratio = 3, /* 1280 */
524f70ad2acSEugen Hristev 		.hbin_ratio = 4, /* 540 */
525f70ad2acSEugen Hristev 		.init_regs = imx274_mode6_1280x540_raw10,
526f70ad2acSEugen Hristev 		.min_frame_len = 2310,
527f70ad2acSEugen Hristev 		.min_SHR = 4,
528f70ad2acSEugen Hristev 		.max_fps = 120,
529f70ad2acSEugen Hristev 		.nocpiop = 112,
530f70ad2acSEugen Hristev 	},
5310985dd30SLeon Luo };
5320985dd30SLeon Luo 
5330985dd30SLeon Luo /*
5340985dd30SLeon Luo  * struct imx274_ctrls - imx274 ctrl structure
5350985dd30SLeon Luo  * @handler: V4L2 ctrl handler structure
5360985dd30SLeon Luo  * @exposure: Pointer to expsure ctrl structure
5370985dd30SLeon Luo  * @gain: Pointer to gain ctrl structure
5380985dd30SLeon Luo  * @vflip: Pointer to vflip ctrl structure
5390985dd30SLeon Luo  * @test_pattern: Pointer to test pattern ctrl structure
5400985dd30SLeon Luo  */
5410985dd30SLeon Luo struct imx274_ctrls {
5420985dd30SLeon Luo 	struct v4l2_ctrl_handler handler;
5430985dd30SLeon Luo 	struct v4l2_ctrl *exposure;
5440985dd30SLeon Luo 	struct v4l2_ctrl *gain;
5450985dd30SLeon Luo 	struct v4l2_ctrl *vflip;
5460985dd30SLeon Luo 	struct v4l2_ctrl *test_pattern;
5470985dd30SLeon Luo };
5480985dd30SLeon Luo 
5490985dd30SLeon Luo /*
5500985dd30SLeon Luo  * struct stim274 - imx274 device structure
5510985dd30SLeon Luo  * @sd: V4L2 subdevice structure
55219d38b23SLuca Ceresoli  * @pad: Media pad structure
5530985dd30SLeon Luo  * @client: Pointer to I2C client
5540985dd30SLeon Luo  * @ctrls: imx274 control structure
55539dd23dcSLuca Ceresoli  * @crop: rect to be captured
55639dd23dcSLuca Ceresoli  * @compose: compose rect, i.e. output resolution
5570985dd30SLeon Luo  * @format: V4L2 media bus frame format structure
55839dd23dcSLuca Ceresoli  *          (width and height are in sync with the compose rect)
5590985dd30SLeon Luo  * @frame_rate: V4L2 frame rate structure
5600985dd30SLeon Luo  * @regmap: Pointer to regmap structure
5610985dd30SLeon Luo  * @reset_gpio: Pointer to reset gpio
562ad97bc37SSowjanya Komatineni  * @supplies: List of analog and digital supply regulators
563ad97bc37SSowjanya Komatineni  * @inck: Pointer to sensor input clock
5640985dd30SLeon Luo  * @lock: Mutex structure
56596a2c731SLuca Ceresoli  * @mode: Parameters for the selected readout mode
5660985dd30SLeon Luo  */
5670985dd30SLeon Luo struct stimx274 {
5680985dd30SLeon Luo 	struct v4l2_subdev sd;
5690985dd30SLeon Luo 	struct media_pad pad;
5700985dd30SLeon Luo 	struct i2c_client *client;
5710985dd30SLeon Luo 	struct imx274_ctrls ctrls;
57239dd23dcSLuca Ceresoli 	struct v4l2_rect crop;
5730985dd30SLeon Luo 	struct v4l2_mbus_framefmt format;
5740985dd30SLeon Luo 	struct v4l2_fract frame_interval;
5750985dd30SLeon Luo 	struct regmap *regmap;
5760985dd30SLeon Luo 	struct gpio_desc *reset_gpio;
577ad97bc37SSowjanya Komatineni 	struct regulator_bulk_data supplies[IMX274_NUM_SUPPLIES];
578ad97bc37SSowjanya Komatineni 	struct clk *inck;
5790985dd30SLeon Luo 	struct mutex lock; /* mutex lock for operations */
5809648cb57SLuca Ceresoli 	const struct imx274_mode *mode;
5810985dd30SLeon Luo };
5820985dd30SLeon Luo 
58339dd23dcSLuca Ceresoli #define IMX274_ROUND(dim, step, flags)			\
58439dd23dcSLuca Ceresoli 	((flags) & V4L2_SEL_FLAG_GE			\
58539dd23dcSLuca Ceresoli 	 ? roundup((dim), (step))			\
58639dd23dcSLuca Ceresoli 	 : ((flags) & V4L2_SEL_FLAG_LE			\
58739dd23dcSLuca Ceresoli 	    ? rounddown((dim), (step))			\
58839dd23dcSLuca Ceresoli 	    : rounddown((dim) + (step) / 2, (step))))
58939dd23dcSLuca Ceresoli 
5900985dd30SLeon Luo /*
5910985dd30SLeon Luo  * Function declaration
5920985dd30SLeon Luo  */
5930985dd30SLeon Luo static int imx274_set_gain(struct stimx274 *priv, struct v4l2_ctrl *ctrl);
5940985dd30SLeon Luo static int imx274_set_exposure(struct stimx274 *priv, int val);
5950985dd30SLeon Luo static int imx274_set_vflip(struct stimx274 *priv, int val);
5960985dd30SLeon Luo static int imx274_set_test_pattern(struct stimx274 *priv, int val);
5970985dd30SLeon Luo static int imx274_set_frame_interval(struct stimx274 *priv,
5980985dd30SLeon Luo 				     struct v4l2_fract frame_interval);
5990985dd30SLeon Luo 
msleep_range(unsigned int delay_base)6000985dd30SLeon Luo static inline void msleep_range(unsigned int delay_base)
6010985dd30SLeon Luo {
6020985dd30SLeon Luo 	usleep_range(delay_base * 1000, delay_base * 1000 + 500);
6030985dd30SLeon Luo }
6040985dd30SLeon Luo 
6050985dd30SLeon Luo /*
6060985dd30SLeon Luo  * v4l2_ctrl and v4l2_subdev related operations
6070985dd30SLeon Luo  */
ctrl_to_sd(struct v4l2_ctrl * ctrl)6080985dd30SLeon Luo static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
6090985dd30SLeon Luo {
6100985dd30SLeon Luo 	return &container_of(ctrl->handler,
6110985dd30SLeon Luo 			     struct stimx274, ctrls.handler)->sd;
6120985dd30SLeon Luo }
6130985dd30SLeon Luo 
to_imx274(struct v4l2_subdev * sd)6140985dd30SLeon Luo static inline struct stimx274 *to_imx274(struct v4l2_subdev *sd)
6150985dd30SLeon Luo {
6160985dd30SLeon Luo 	return container_of(sd, struct stimx274, sd);
6170985dd30SLeon Luo }
6180985dd30SLeon Luo 
6190985dd30SLeon Luo /*
6207ff67863SLuca Ceresoli  * Writing a register table
6217ff67863SLuca Ceresoli  *
6227ff67863SLuca Ceresoli  * @priv: Pointer to device
6237ff67863SLuca Ceresoli  * @table: Table containing register values (with optional delays)
6240985dd30SLeon Luo  *
6250985dd30SLeon Luo  * This is used to write register table into sensor's reg map.
6260985dd30SLeon Luo  *
6270985dd30SLeon Luo  * Return: 0 on success, errors otherwise
6280985dd30SLeon Luo  */
imx274_write_table(struct stimx274 * priv,const struct reg_8 table[])6297ff67863SLuca Ceresoli static int imx274_write_table(struct stimx274 *priv, const struct reg_8 table[])
6300985dd30SLeon Luo {
6317ff67863SLuca Ceresoli 	struct regmap *regmap = priv->regmap;
632021741adSDan Carpenter 	int err = 0;
6330985dd30SLeon Luo 	const struct reg_8 *next;
6340985dd30SLeon Luo 	u8 val;
6350985dd30SLeon Luo 
6360985dd30SLeon Luo 	int range_start = -1;
6370985dd30SLeon Luo 	int range_count = 0;
6380985dd30SLeon Luo 	u8 range_vals[16];
6390985dd30SLeon Luo 	int max_range_vals = ARRAY_SIZE(range_vals);
6400985dd30SLeon Luo 
6410985dd30SLeon Luo 	for (next = table;; next++) {
6420985dd30SLeon Luo 		if ((next->addr != range_start + range_count) ||
6437ff67863SLuca Ceresoli 		    (next->addr == IMX274_TABLE_END) ||
6447ff67863SLuca Ceresoli 		    (next->addr == IMX274_TABLE_WAIT_MS) ||
6450985dd30SLeon Luo 		    (range_count == max_range_vals)) {
6460985dd30SLeon Luo 			if (range_count == 1)
6470985dd30SLeon Luo 				err = regmap_write(regmap,
6480985dd30SLeon Luo 						   range_start, range_vals[0]);
6490985dd30SLeon Luo 			else if (range_count > 1)
6500985dd30SLeon Luo 				err = regmap_bulk_write(regmap, range_start,
6510985dd30SLeon Luo 							&range_vals[0],
6520985dd30SLeon Luo 							range_count);
65300b4bac7SMauro Carvalho Chehab 			else
65400b4bac7SMauro Carvalho Chehab 				err = 0;
6550985dd30SLeon Luo 
6560985dd30SLeon Luo 			if (err)
6570985dd30SLeon Luo 				return err;
6580985dd30SLeon Luo 
6590985dd30SLeon Luo 			range_start = -1;
6600985dd30SLeon Luo 			range_count = 0;
6610985dd30SLeon Luo 
6620985dd30SLeon Luo 			/* Handle special address values */
6637ff67863SLuca Ceresoli 			if (next->addr == IMX274_TABLE_END)
6640985dd30SLeon Luo 				break;
6650985dd30SLeon Luo 
6667ff67863SLuca Ceresoli 			if (next->addr == IMX274_TABLE_WAIT_MS) {
6670985dd30SLeon Luo 				msleep_range(next->val);
6680985dd30SLeon Luo 				continue;
6690985dd30SLeon Luo 			}
6700985dd30SLeon Luo 		}
6710985dd30SLeon Luo 
6720985dd30SLeon Luo 		val = next->val;
6730985dd30SLeon Luo 
6740985dd30SLeon Luo 		if (range_start == -1)
6750985dd30SLeon Luo 			range_start = next->addr;
6760985dd30SLeon Luo 
6770985dd30SLeon Luo 		range_vals[range_count++] = val;
6780985dd30SLeon Luo 	}
6790985dd30SLeon Luo 	return 0;
6800985dd30SLeon Luo }
6810985dd30SLeon Luo 
imx274_write_reg(struct stimx274 * priv,u16 addr,u8 val)6820985dd30SLeon Luo static inline int imx274_write_reg(struct stimx274 *priv, u16 addr, u8 val)
6830985dd30SLeon Luo {
6840985dd30SLeon Luo 	int err;
6850985dd30SLeon Luo 
6860985dd30SLeon Luo 	err = regmap_write(priv->regmap, addr, val);
6870985dd30SLeon Luo 	if (err)
6880985dd30SLeon Luo 		dev_err(&priv->client->dev,
6890985dd30SLeon Luo 			"%s : i2c write failed, %x = %x\n", __func__,
6900985dd30SLeon Luo 			addr, val);
6910985dd30SLeon Luo 	else
6920985dd30SLeon Luo 		dev_dbg(&priv->client->dev,
6930985dd30SLeon Luo 			"%s : addr 0x%x, val=0x%x\n", __func__,
6940985dd30SLeon Luo 			addr, val);
6950985dd30SLeon Luo 	return err;
6960985dd30SLeon Luo }
6970985dd30SLeon Luo 
698279b4b9aSLuca Ceresoli /**
699a4184b4fSHans Verkuil  * imx274_read_mbreg - Read a multibyte register.
700ca017467SLuca Ceresoli  *
701ca017467SLuca Ceresoli  * Uses a bulk read where possible.
702ca017467SLuca Ceresoli  *
703ca017467SLuca Ceresoli  * @priv: Pointer to device structure
704ca017467SLuca Ceresoli  * @addr: Address of the LSB register.  Other registers must be
705ca017467SLuca Ceresoli  *        consecutive, least-to-most significant.
706ca017467SLuca Ceresoli  * @val: Pointer to store the register value (cpu endianness)
707ca017467SLuca Ceresoli  * @nbytes: Number of bytes to read (range: [1..3]).
708ca017467SLuca Ceresoli  *          Other bytes are zet to 0.
709ca017467SLuca Ceresoli  *
710ca017467SLuca Ceresoli  * Return: 0 on success, errors otherwise
711ca017467SLuca Ceresoli  */
imx274_read_mbreg(struct stimx274 * priv,u16 addr,u32 * val,size_t nbytes)712ca017467SLuca Ceresoli static int imx274_read_mbreg(struct stimx274 *priv, u16 addr, u32 *val,
713ca017467SLuca Ceresoli 			     size_t nbytes)
714ca017467SLuca Ceresoli {
715ca017467SLuca Ceresoli 	__le32 val_le = 0;
716ca017467SLuca Ceresoli 	int err;
717ca017467SLuca Ceresoli 
718ca017467SLuca Ceresoli 	err = regmap_bulk_read(priv->regmap, addr, &val_le, nbytes);
719ca017467SLuca Ceresoli 	if (err) {
720ca017467SLuca Ceresoli 		dev_err(&priv->client->dev,
721ca017467SLuca Ceresoli 			"%s : i2c bulk read failed, %x (%zu bytes)\n",
722ca017467SLuca Ceresoli 			__func__, addr, nbytes);
723ca017467SLuca Ceresoli 	} else {
724ca017467SLuca Ceresoli 		*val = le32_to_cpu(val_le);
725ca017467SLuca Ceresoli 		dev_dbg(&priv->client->dev,
726ca017467SLuca Ceresoli 			"%s : addr 0x%x, val=0x%x (%zu bytes)\n",
727ca017467SLuca Ceresoli 			__func__, addr, *val, nbytes);
728ca017467SLuca Ceresoli 	}
729ca017467SLuca Ceresoli 
730ca017467SLuca Ceresoli 	return err;
731ca017467SLuca Ceresoli }
732ca017467SLuca Ceresoli 
733ca017467SLuca Ceresoli /**
734a4184b4fSHans Verkuil  * imx274_write_mbreg - Write a multibyte register.
735279b4b9aSLuca Ceresoli  *
736279b4b9aSLuca Ceresoli  * Uses a bulk write where possible.
737279b4b9aSLuca Ceresoli  *
738279b4b9aSLuca Ceresoli  * @priv: Pointer to device structure
739279b4b9aSLuca Ceresoli  * @addr: Address of the LSB register.  Other registers must be
740279b4b9aSLuca Ceresoli  *        consecutive, least-to-most significant.
741279b4b9aSLuca Ceresoli  * @val: Value to be written to the register (cpu endianness)
7421657c28dSLuca Ceresoli  * @nbytes: Number of bytes to write (range: [1..3])
743279b4b9aSLuca Ceresoli  */
imx274_write_mbreg(struct stimx274 * priv,u16 addr,u32 val,size_t nbytes)744279b4b9aSLuca Ceresoli static int imx274_write_mbreg(struct stimx274 *priv, u16 addr, u32 val,
745279b4b9aSLuca Ceresoli 			      size_t nbytes)
746279b4b9aSLuca Ceresoli {
747279b4b9aSLuca Ceresoli 	__le32 val_le = cpu_to_le32(val);
748279b4b9aSLuca Ceresoli 	int err;
749279b4b9aSLuca Ceresoli 
750279b4b9aSLuca Ceresoli 	err = regmap_bulk_write(priv->regmap, addr, &val_le, nbytes);
751279b4b9aSLuca Ceresoli 	if (err)
752279b4b9aSLuca Ceresoli 		dev_err(&priv->client->dev,
753279b4b9aSLuca Ceresoli 			"%s : i2c bulk write failed, %x = %x (%zu bytes)\n",
754279b4b9aSLuca Ceresoli 			__func__, addr, val, nbytes);
755279b4b9aSLuca Ceresoli 	else
756279b4b9aSLuca Ceresoli 		dev_dbg(&priv->client->dev,
757279b4b9aSLuca Ceresoli 			"%s : addr 0x%x, val=0x%x (%zu bytes)\n",
758279b4b9aSLuca Ceresoli 			__func__, addr, val, nbytes);
759279b4b9aSLuca Ceresoli 	return err;
760279b4b9aSLuca Ceresoli }
761279b4b9aSLuca Ceresoli 
7620985dd30SLeon Luo /*
76396a2c731SLuca Ceresoli  * Set mode registers to start stream.
7640985dd30SLeon Luo  * @priv: Pointer to device structure
7650985dd30SLeon Luo  *
7660985dd30SLeon Luo  * Return: 0 on success, errors otherwise
7670985dd30SLeon Luo  */
imx274_mode_regs(struct stimx274 * priv)76896a2c731SLuca Ceresoli static int imx274_mode_regs(struct stimx274 *priv)
7690985dd30SLeon Luo {
7700985dd30SLeon Luo 	int err = 0;
7710985dd30SLeon Luo 
7728ed8bba7SLuca Ceresoli 	err = imx274_write_table(priv, imx274_start_1);
7730985dd30SLeon Luo 	if (err)
7740985dd30SLeon Luo 		return err;
7750985dd30SLeon Luo 
77696a2c731SLuca Ceresoli 	err = imx274_write_table(priv, priv->mode->init_regs);
7770985dd30SLeon Luo 
7780985dd30SLeon Luo 	return err;
7790985dd30SLeon Luo }
7800985dd30SLeon Luo 
7810985dd30SLeon Luo /*
7820985dd30SLeon Luo  * imx274_start_stream - Function for starting stream per mode index
7830985dd30SLeon Luo  * @priv: Pointer to device structure
7840985dd30SLeon Luo  *
7850985dd30SLeon Luo  * Return: 0 on success, errors otherwise
7860985dd30SLeon Luo  */
imx274_start_stream(struct stimx274 * priv)7870985dd30SLeon Luo static int imx274_start_stream(struct stimx274 *priv)
7880985dd30SLeon Luo {
7890985dd30SLeon Luo 	int err = 0;
7900985dd30SLeon Luo 
791ad97bc37SSowjanya Komatineni 	err = __v4l2_ctrl_handler_setup(&priv->ctrls.handler);
792ad97bc37SSowjanya Komatineni 	if (err) {
793ad97bc37SSowjanya Komatineni 		dev_err(&priv->client->dev, "Error %d setup controls\n", err);
794ad97bc37SSowjanya Komatineni 		return err;
795ad97bc37SSowjanya Komatineni 	}
796ad97bc37SSowjanya Komatineni 
7970985dd30SLeon Luo 	/*
7980985dd30SLeon Luo 	 * Refer to "Standby Cancel Sequence when using CSI-2" in
7990985dd30SLeon Luo 	 * imx274 datasheet, it should wait 10ms or more here.
8000985dd30SLeon Luo 	 * give it 1 extra ms for margin
8010985dd30SLeon Luo 	 */
8020985dd30SLeon Luo 	msleep_range(11);
8037d2332c7SLuca Ceresoli 	err = imx274_write_table(priv, imx274_start_2);
8040985dd30SLeon Luo 	if (err)
8050985dd30SLeon Luo 		return err;
8060985dd30SLeon Luo 
8070985dd30SLeon Luo 	/*
8080985dd30SLeon Luo 	 * Refer to "Standby Cancel Sequence when using CSI-2" in
8090985dd30SLeon Luo 	 * imx274 datasheet, it should wait 7ms or more here.
8100985dd30SLeon Luo 	 * give it 1 extra ms for margin
8110985dd30SLeon Luo 	 */
8120985dd30SLeon Luo 	msleep_range(8);
8137d2332c7SLuca Ceresoli 	err = imx274_write_table(priv, imx274_start_3);
8140985dd30SLeon Luo 	if (err)
8150985dd30SLeon Luo 		return err;
8160985dd30SLeon Luo 
8170985dd30SLeon Luo 	return 0;
8180985dd30SLeon Luo }
8190985dd30SLeon Luo 
8200985dd30SLeon Luo /*
8210985dd30SLeon Luo  * imx274_reset - Function called to reset the sensor
8220985dd30SLeon Luo  * @priv: Pointer to device structure
8230985dd30SLeon Luo  * @rst: Input value for determining the sensor's end state after reset
8240985dd30SLeon Luo  *
8250985dd30SLeon Luo  * Set the senor in reset and then
8260985dd30SLeon Luo  * if rst = 0, keep it in reset;
8270985dd30SLeon Luo  * if rst = 1, bring it out of reset.
8280985dd30SLeon Luo  *
8290985dd30SLeon Luo  */
imx274_reset(struct stimx274 * priv,int rst)8300985dd30SLeon Luo static void imx274_reset(struct stimx274 *priv, int rst)
8310985dd30SLeon Luo {
8320985dd30SLeon Luo 	gpiod_set_value_cansleep(priv->reset_gpio, 0);
8330985dd30SLeon Luo 	usleep_range(IMX274_RESET_DELAY1, IMX274_RESET_DELAY2);
8340985dd30SLeon Luo 	gpiod_set_value_cansleep(priv->reset_gpio, !!rst);
8350985dd30SLeon Luo 	usleep_range(IMX274_RESET_DELAY1, IMX274_RESET_DELAY2);
8360985dd30SLeon Luo }
8370985dd30SLeon Luo 
imx274_power_on(struct device * dev)838ad97bc37SSowjanya Komatineni static int imx274_power_on(struct device *dev)
839ad97bc37SSowjanya Komatineni {
840ad97bc37SSowjanya Komatineni 	struct i2c_client *client = to_i2c_client(dev);
841ad97bc37SSowjanya Komatineni 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
842ad97bc37SSowjanya Komatineni 	struct stimx274 *imx274 = to_imx274(sd);
843ad97bc37SSowjanya Komatineni 	int ret;
844ad97bc37SSowjanya Komatineni 
845ad97bc37SSowjanya Komatineni 	/* keep sensor in reset before power on */
846ad97bc37SSowjanya Komatineni 	imx274_reset(imx274, 0);
847ad97bc37SSowjanya Komatineni 
848ad97bc37SSowjanya Komatineni 	ret = clk_prepare_enable(imx274->inck);
849ad97bc37SSowjanya Komatineni 	if (ret) {
850ad97bc37SSowjanya Komatineni 		dev_err(&imx274->client->dev,
851ad97bc37SSowjanya Komatineni 			"Failed to enable input clock: %d\n", ret);
852ad97bc37SSowjanya Komatineni 		return ret;
853ad97bc37SSowjanya Komatineni 	}
854ad97bc37SSowjanya Komatineni 
855ad97bc37SSowjanya Komatineni 	ret = regulator_bulk_enable(IMX274_NUM_SUPPLIES, imx274->supplies);
856ad97bc37SSowjanya Komatineni 	if (ret) {
857ad97bc37SSowjanya Komatineni 		dev_err(&imx274->client->dev,
858ad97bc37SSowjanya Komatineni 			"Failed to enable regulators: %d\n", ret);
859ad97bc37SSowjanya Komatineni 		goto fail_reg;
860ad97bc37SSowjanya Komatineni 	}
861ad97bc37SSowjanya Komatineni 
862ad97bc37SSowjanya Komatineni 	udelay(2);
863ad97bc37SSowjanya Komatineni 	imx274_reset(imx274, 1);
864ad97bc37SSowjanya Komatineni 
865ad97bc37SSowjanya Komatineni 	return 0;
866ad97bc37SSowjanya Komatineni 
867ad97bc37SSowjanya Komatineni fail_reg:
868ad97bc37SSowjanya Komatineni 	clk_disable_unprepare(imx274->inck);
869ad97bc37SSowjanya Komatineni 	return ret;
870ad97bc37SSowjanya Komatineni }
871ad97bc37SSowjanya Komatineni 
imx274_power_off(struct device * dev)872ad97bc37SSowjanya Komatineni static int imx274_power_off(struct device *dev)
873ad97bc37SSowjanya Komatineni {
874ad97bc37SSowjanya Komatineni 	struct i2c_client *client = to_i2c_client(dev);
875ad97bc37SSowjanya Komatineni 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
876ad97bc37SSowjanya Komatineni 	struct stimx274 *imx274 = to_imx274(sd);
877ad97bc37SSowjanya Komatineni 
878ad97bc37SSowjanya Komatineni 	imx274_reset(imx274, 0);
879ad97bc37SSowjanya Komatineni 
880ad97bc37SSowjanya Komatineni 	regulator_bulk_disable(IMX274_NUM_SUPPLIES, imx274->supplies);
881ad97bc37SSowjanya Komatineni 
882ad97bc37SSowjanya Komatineni 	clk_disable_unprepare(imx274->inck);
883ad97bc37SSowjanya Komatineni 
884ad97bc37SSowjanya Komatineni 	return 0;
885ad97bc37SSowjanya Komatineni }
886ad97bc37SSowjanya Komatineni 
imx274_regulators_get(struct device * dev,struct stimx274 * imx274)887ad97bc37SSowjanya Komatineni static int imx274_regulators_get(struct device *dev, struct stimx274 *imx274)
888ad97bc37SSowjanya Komatineni {
889ad97bc37SSowjanya Komatineni 	unsigned int i;
890ad97bc37SSowjanya Komatineni 
891ad97bc37SSowjanya Komatineni 	for (i = 0; i < IMX274_NUM_SUPPLIES; i++)
892ad97bc37SSowjanya Komatineni 		imx274->supplies[i].supply = imx274_supply_names[i];
893ad97bc37SSowjanya Komatineni 
894ad97bc37SSowjanya Komatineni 	return devm_regulator_bulk_get(dev, IMX274_NUM_SUPPLIES,
895ad97bc37SSowjanya Komatineni 					imx274->supplies);
896ad97bc37SSowjanya Komatineni }
897ad97bc37SSowjanya Komatineni 
8980985dd30SLeon Luo /**
8990985dd30SLeon Luo  * imx274_s_ctrl - This is used to set the imx274 V4L2 controls
9000985dd30SLeon Luo  * @ctrl: V4L2 control to be set
9010985dd30SLeon Luo  *
9020985dd30SLeon Luo  * This function is used to set the V4L2 controls for the imx274 sensor.
9030985dd30SLeon Luo  *
9040985dd30SLeon Luo  * Return: 0 on success, errors otherwise
9050985dd30SLeon Luo  */
imx274_s_ctrl(struct v4l2_ctrl * ctrl)9060985dd30SLeon Luo static int imx274_s_ctrl(struct v4l2_ctrl *ctrl)
9070985dd30SLeon Luo {
9080985dd30SLeon Luo 	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
9090985dd30SLeon Luo 	struct stimx274 *imx274 = to_imx274(sd);
9100985dd30SLeon Luo 	int ret = -EINVAL;
9110985dd30SLeon Luo 
912ad97bc37SSowjanya Komatineni 	if (!pm_runtime_get_if_in_use(&imx274->client->dev))
913ad97bc37SSowjanya Komatineni 		return 0;
914ad97bc37SSowjanya Komatineni 
9150985dd30SLeon Luo 	dev_dbg(&imx274->client->dev,
9160985dd30SLeon Luo 		"%s : s_ctrl: %s, value: %d\n", __func__,
9170985dd30SLeon Luo 		ctrl->name, ctrl->val);
9180985dd30SLeon Luo 
9190985dd30SLeon Luo 	switch (ctrl->id) {
9200985dd30SLeon Luo 	case V4L2_CID_EXPOSURE:
9210985dd30SLeon Luo 		dev_dbg(&imx274->client->dev,
9220985dd30SLeon Luo 			"%s : set V4L2_CID_EXPOSURE\n", __func__);
9230985dd30SLeon Luo 		ret = imx274_set_exposure(imx274, ctrl->val);
9240985dd30SLeon Luo 		break;
9250985dd30SLeon Luo 
9260985dd30SLeon Luo 	case V4L2_CID_GAIN:
9270985dd30SLeon Luo 		dev_dbg(&imx274->client->dev,
9280985dd30SLeon Luo 			"%s : set V4L2_CID_GAIN\n", __func__);
9290985dd30SLeon Luo 		ret = imx274_set_gain(imx274, ctrl);
9300985dd30SLeon Luo 		break;
9310985dd30SLeon Luo 
9320985dd30SLeon Luo 	case V4L2_CID_VFLIP:
9330985dd30SLeon Luo 		dev_dbg(&imx274->client->dev,
9340985dd30SLeon Luo 			"%s : set V4L2_CID_VFLIP\n", __func__);
9350985dd30SLeon Luo 		ret = imx274_set_vflip(imx274, ctrl->val);
9360985dd30SLeon Luo 		break;
9370985dd30SLeon Luo 
9380985dd30SLeon Luo 	case V4L2_CID_TEST_PATTERN:
9390985dd30SLeon Luo 		dev_dbg(&imx274->client->dev,
9400985dd30SLeon Luo 			"%s : set V4L2_CID_TEST_PATTERN\n", __func__);
9410985dd30SLeon Luo 		ret = imx274_set_test_pattern(imx274, ctrl->val);
9420985dd30SLeon Luo 		break;
9430985dd30SLeon Luo 	}
9440985dd30SLeon Luo 
945ad97bc37SSowjanya Komatineni 	pm_runtime_put(&imx274->client->dev);
946ad97bc37SSowjanya Komatineni 
9470985dd30SLeon Luo 	return ret;
9480985dd30SLeon Luo }
9490985dd30SLeon Luo 
imx274_binning_goodness(struct stimx274 * imx274,int w,int ask_w,int h,int ask_h,u32 flags)95039dd23dcSLuca Ceresoli static int imx274_binning_goodness(struct stimx274 *imx274,
95139dd23dcSLuca Ceresoli 				   int w, int ask_w,
95239dd23dcSLuca Ceresoli 				   int h, int ask_h, u32 flags)
95339dd23dcSLuca Ceresoli {
95439dd23dcSLuca Ceresoli 	struct device *dev = &imx274->client->dev;
95539dd23dcSLuca Ceresoli 	const int goodness = 100000;
95639dd23dcSLuca Ceresoli 	int val = 0;
95739dd23dcSLuca Ceresoli 
95839dd23dcSLuca Ceresoli 	if (flags & V4L2_SEL_FLAG_GE) {
95939dd23dcSLuca Ceresoli 		if (w < ask_w)
96039dd23dcSLuca Ceresoli 			val -= goodness;
96139dd23dcSLuca Ceresoli 		if (h < ask_h)
96239dd23dcSLuca Ceresoli 			val -= goodness;
96339dd23dcSLuca Ceresoli 	}
96439dd23dcSLuca Ceresoli 
96539dd23dcSLuca Ceresoli 	if (flags & V4L2_SEL_FLAG_LE) {
96639dd23dcSLuca Ceresoli 		if (w > ask_w)
96739dd23dcSLuca Ceresoli 			val -= goodness;
96839dd23dcSLuca Ceresoli 		if (h > ask_h)
96939dd23dcSLuca Ceresoli 			val -= goodness;
97039dd23dcSLuca Ceresoli 	}
97139dd23dcSLuca Ceresoli 
97239dd23dcSLuca Ceresoli 	val -= abs(w - ask_w);
97339dd23dcSLuca Ceresoli 	val -= abs(h - ask_h);
97439dd23dcSLuca Ceresoli 
97539dd23dcSLuca Ceresoli 	dev_dbg(dev, "%s: ask %dx%d, size %dx%d, goodness %d\n",
97639dd23dcSLuca Ceresoli 		__func__, ask_w, ask_h, w, h, val);
97739dd23dcSLuca Ceresoli 
97839dd23dcSLuca Ceresoli 	return val;
97939dd23dcSLuca Ceresoli }
98039dd23dcSLuca Ceresoli 
98139dd23dcSLuca Ceresoli /**
982a4184b4fSHans Verkuil  * __imx274_change_compose - Helper function to change binning and set both
983a4184b4fSHans Verkuil  *	compose and format.
98439dd23dcSLuca Ceresoli  *
98539dd23dcSLuca Ceresoli  * We have two entry points to change binning: set_fmt and
98639dd23dcSLuca Ceresoli  * set_selection(COMPOSE). Both have to compute the new output size
98739dd23dcSLuca Ceresoli  * and set it in both the compose rect and the frame format size. We
98839dd23dcSLuca Ceresoli  * also need to do the same things after setting cropping to restore
98939dd23dcSLuca Ceresoli  * 1:1 binning.
99039dd23dcSLuca Ceresoli  *
99139dd23dcSLuca Ceresoli  * This function contains the common code for these three cases, it
99239dd23dcSLuca Ceresoli  * has many arguments in order to accommodate the needs of all of
99339dd23dcSLuca Ceresoli  * them.
99439dd23dcSLuca Ceresoli  *
99539dd23dcSLuca Ceresoli  * Must be called with imx274->lock locked.
99639dd23dcSLuca Ceresoli  *
99739dd23dcSLuca Ceresoli  * @imx274: The device object
9980d346d2aSTomi Valkeinen  * @sd_state: The subdev state we are editing for TRY requests
99939dd23dcSLuca Ceresoli  * @which:  V4L2_SUBDEV_FORMAT_ACTIVE or V4L2_SUBDEV_FORMAT_TRY from the caller
100039dd23dcSLuca Ceresoli  * @width:  Input-output parameter: set to the desired width before
100139dd23dcSLuca Ceresoli  *          the call, contains the chosen value after returning successfully
100239dd23dcSLuca Ceresoli  * @height: Input-output parameter for height (see @width)
100339dd23dcSLuca Ceresoli  * @flags:  Selection flags from struct v4l2_subdev_selection, or 0 if not
100439dd23dcSLuca Ceresoli  *          available (when called from set_fmt)
100539dd23dcSLuca Ceresoli  */
__imx274_change_compose(struct stimx274 * imx274,struct v4l2_subdev_state * sd_state,u32 which,u32 * width,u32 * height,u32 flags)100639dd23dcSLuca Ceresoli static int __imx274_change_compose(struct stimx274 *imx274,
10070d346d2aSTomi Valkeinen 				   struct v4l2_subdev_state *sd_state,
100839dd23dcSLuca Ceresoli 				   u32 which,
100939dd23dcSLuca Ceresoli 				   u32 *width,
101039dd23dcSLuca Ceresoli 				   u32 *height,
101139dd23dcSLuca Ceresoli 				   u32 flags)
101239dd23dcSLuca Ceresoli {
101339dd23dcSLuca Ceresoli 	struct device *dev = &imx274->client->dev;
101439dd23dcSLuca Ceresoli 	const struct v4l2_rect *cur_crop;
101539dd23dcSLuca Ceresoli 	struct v4l2_mbus_framefmt *tgt_fmt;
101639dd23dcSLuca Ceresoli 	unsigned int i;
10179648cb57SLuca Ceresoli 	const struct imx274_mode *best_mode = &imx274_modes[0];
101839dd23dcSLuca Ceresoli 	int best_goodness = INT_MIN;
101939dd23dcSLuca Ceresoli 
102039dd23dcSLuca Ceresoli 	if (which == V4L2_SUBDEV_FORMAT_TRY) {
10210d346d2aSTomi Valkeinen 		cur_crop = &sd_state->pads->try_crop;
10220d346d2aSTomi Valkeinen 		tgt_fmt = &sd_state->pads->try_fmt;
102339dd23dcSLuca Ceresoli 	} else {
102439dd23dcSLuca Ceresoli 		cur_crop = &imx274->crop;
102539dd23dcSLuca Ceresoli 		tgt_fmt = &imx274->format;
102639dd23dcSLuca Ceresoli 	}
102739dd23dcSLuca Ceresoli 
10289648cb57SLuca Ceresoli 	for (i = 0; i < ARRAY_SIZE(imx274_modes); i++) {
1029f70ad2acSEugen Hristev 		u8 wratio = imx274_modes[i].wbin_ratio;
1030f70ad2acSEugen Hristev 		u8 hratio = imx274_modes[i].hbin_ratio;
103139dd23dcSLuca Ceresoli 
103239dd23dcSLuca Ceresoli 		int goodness = imx274_binning_goodness(
103339dd23dcSLuca Ceresoli 			imx274,
1034f70ad2acSEugen Hristev 			cur_crop->width / wratio, *width,
1035f70ad2acSEugen Hristev 			cur_crop->height / hratio, *height,
103639dd23dcSLuca Ceresoli 			flags);
103739dd23dcSLuca Ceresoli 
103839dd23dcSLuca Ceresoli 		if (goodness >= best_goodness) {
103939dd23dcSLuca Ceresoli 			best_goodness = goodness;
10409648cb57SLuca Ceresoli 			best_mode = &imx274_modes[i];
104139dd23dcSLuca Ceresoli 		}
104239dd23dcSLuca Ceresoli 	}
104339dd23dcSLuca Ceresoli 
1044f70ad2acSEugen Hristev 	*width = cur_crop->width / best_mode->wbin_ratio;
1045f70ad2acSEugen Hristev 	*height = cur_crop->height / best_mode->hbin_ratio;
104639dd23dcSLuca Ceresoli 
104739dd23dcSLuca Ceresoli 	if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
104839dd23dcSLuca Ceresoli 		imx274->mode = best_mode;
104939dd23dcSLuca Ceresoli 
1050f70ad2acSEugen Hristev 	dev_dbg(dev, "%s: selected %ux%u binning\n",
1051f70ad2acSEugen Hristev 		__func__, best_mode->wbin_ratio, best_mode->hbin_ratio);
105239dd23dcSLuca Ceresoli 
105339dd23dcSLuca Ceresoli 	tgt_fmt->width = *width;
105439dd23dcSLuca Ceresoli 	tgt_fmt->height = *height;
105539dd23dcSLuca Ceresoli 	tgt_fmt->field = V4L2_FIELD_NONE;
105639dd23dcSLuca Ceresoli 
105739dd23dcSLuca Ceresoli 	return 0;
105839dd23dcSLuca Ceresoli }
105939dd23dcSLuca Ceresoli 
10600985dd30SLeon Luo /**
10610985dd30SLeon Luo  * imx274_get_fmt - Get the pad format
10620985dd30SLeon Luo  * @sd: Pointer to V4L2 Sub device structure
10630d346d2aSTomi Valkeinen  * @sd_state: Pointer to sub device state structure
10640985dd30SLeon Luo  * @fmt: Pointer to pad level media bus format
10650985dd30SLeon Luo  *
10660985dd30SLeon Luo  * This function is used to get the pad format information.
10670985dd30SLeon Luo  *
10680985dd30SLeon Luo  * Return: 0 on success
10690985dd30SLeon Luo  */
imx274_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)10700985dd30SLeon Luo static int imx274_get_fmt(struct v4l2_subdev *sd,
10710d346d2aSTomi Valkeinen 			  struct v4l2_subdev_state *sd_state,
10720985dd30SLeon Luo 			  struct v4l2_subdev_format *fmt)
10730985dd30SLeon Luo {
10740985dd30SLeon Luo 	struct stimx274 *imx274 = to_imx274(sd);
10750985dd30SLeon Luo 
10760985dd30SLeon Luo 	mutex_lock(&imx274->lock);
10770985dd30SLeon Luo 	fmt->format = imx274->format;
10780985dd30SLeon Luo 	mutex_unlock(&imx274->lock);
10790985dd30SLeon Luo 	return 0;
10800985dd30SLeon Luo }
10810985dd30SLeon Luo 
10820985dd30SLeon Luo /**
10830985dd30SLeon Luo  * imx274_set_fmt - This is used to set the pad format
10840985dd30SLeon Luo  * @sd: Pointer to V4L2 Sub device structure
10850d346d2aSTomi Valkeinen  * @sd_state: Pointer to sub device state information structure
10860985dd30SLeon Luo  * @format: Pointer to pad level media bus format
10870985dd30SLeon Luo  *
10880985dd30SLeon Luo  * This function is used to set the pad format.
10890985dd30SLeon Luo  *
10900985dd30SLeon Luo  * Return: 0 on success
10910985dd30SLeon Luo  */
imx274_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)10920985dd30SLeon Luo static int imx274_set_fmt(struct v4l2_subdev *sd,
10930d346d2aSTomi Valkeinen 			  struct v4l2_subdev_state *sd_state,
10940985dd30SLeon Luo 			  struct v4l2_subdev_format *format)
10950985dd30SLeon Luo {
10960985dd30SLeon Luo 	struct v4l2_mbus_framefmt *fmt = &format->format;
10970985dd30SLeon Luo 	struct stimx274 *imx274 = to_imx274(sd);
109839dd23dcSLuca Ceresoli 	int err = 0;
10990985dd30SLeon Luo 
11000985dd30SLeon Luo 	mutex_lock(&imx274->lock);
11010985dd30SLeon Luo 
11020d346d2aSTomi Valkeinen 	err = __imx274_change_compose(imx274, sd_state, format->which,
110339dd23dcSLuca Ceresoli 				      &fmt->width, &fmt->height, 0);
11040985dd30SLeon Luo 
110539dd23dcSLuca Ceresoli 	if (err)
110639dd23dcSLuca Ceresoli 		goto out;
11070985dd30SLeon Luo 
110839dd23dcSLuca Ceresoli 	/*
110939dd23dcSLuca Ceresoli 	 * __imx274_change_compose already set width and height in the
111039dd23dcSLuca Ceresoli 	 * applicable format, but we need to keep all other format
111139dd23dcSLuca Ceresoli 	 * values, so do a full copy here
111239dd23dcSLuca Ceresoli 	 */
11130985dd30SLeon Luo 	fmt->field = V4L2_FIELD_NONE;
11140985dd30SLeon Luo 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
11150d346d2aSTomi Valkeinen 		sd_state->pads->try_fmt = *fmt;
11160985dd30SLeon Luo 	else
11170985dd30SLeon Luo 		imx274->format = *fmt;
11180985dd30SLeon Luo 
111939dd23dcSLuca Ceresoli out:
11200985dd30SLeon Luo 	mutex_unlock(&imx274->lock);
112139dd23dcSLuca Ceresoli 
112239dd23dcSLuca Ceresoli 	return err;
112339dd23dcSLuca Ceresoli }
112439dd23dcSLuca Ceresoli 
imx274_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)112539dd23dcSLuca Ceresoli static int imx274_get_selection(struct v4l2_subdev *sd,
11260d346d2aSTomi Valkeinen 				struct v4l2_subdev_state *sd_state,
112739dd23dcSLuca Ceresoli 				struct v4l2_subdev_selection *sel)
112839dd23dcSLuca Ceresoli {
112939dd23dcSLuca Ceresoli 	struct stimx274 *imx274 = to_imx274(sd);
113039dd23dcSLuca Ceresoli 	const struct v4l2_rect *src_crop;
113139dd23dcSLuca Ceresoli 	const struct v4l2_mbus_framefmt *src_fmt;
113239dd23dcSLuca Ceresoli 	int ret = 0;
113339dd23dcSLuca Ceresoli 
113439dd23dcSLuca Ceresoli 	if (sel->pad != 0)
113539dd23dcSLuca Ceresoli 		return -EINVAL;
113639dd23dcSLuca Ceresoli 
113739dd23dcSLuca Ceresoli 	if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
113839dd23dcSLuca Ceresoli 		sel->r.left = 0;
113939dd23dcSLuca Ceresoli 		sel->r.top = 0;
114039dd23dcSLuca Ceresoli 		sel->r.width = IMX274_MAX_WIDTH;
114139dd23dcSLuca Ceresoli 		sel->r.height = IMX274_MAX_HEIGHT;
11420985dd30SLeon Luo 		return 0;
11430985dd30SLeon Luo 	}
11440985dd30SLeon Luo 
114539dd23dcSLuca Ceresoli 	if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
11460d346d2aSTomi Valkeinen 		src_crop = &sd_state->pads->try_crop;
11470d346d2aSTomi Valkeinen 		src_fmt = &sd_state->pads->try_fmt;
114839dd23dcSLuca Ceresoli 	} else {
114939dd23dcSLuca Ceresoli 		src_crop = &imx274->crop;
115039dd23dcSLuca Ceresoli 		src_fmt = &imx274->format;
115139dd23dcSLuca Ceresoli 	}
115239dd23dcSLuca Ceresoli 
115339dd23dcSLuca Ceresoli 	mutex_lock(&imx274->lock);
115439dd23dcSLuca Ceresoli 
115539dd23dcSLuca Ceresoli 	switch (sel->target) {
115639dd23dcSLuca Ceresoli 	case V4L2_SEL_TGT_CROP:
115739dd23dcSLuca Ceresoli 		sel->r = *src_crop;
115839dd23dcSLuca Ceresoli 		break;
115939dd23dcSLuca Ceresoli 	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
116039dd23dcSLuca Ceresoli 		sel->r.top = 0;
116139dd23dcSLuca Ceresoli 		sel->r.left = 0;
116239dd23dcSLuca Ceresoli 		sel->r.width = src_crop->width;
116339dd23dcSLuca Ceresoli 		sel->r.height = src_crop->height;
116439dd23dcSLuca Ceresoli 		break;
116539dd23dcSLuca Ceresoli 	case V4L2_SEL_TGT_COMPOSE:
116639dd23dcSLuca Ceresoli 		sel->r.top = 0;
116739dd23dcSLuca Ceresoli 		sel->r.left = 0;
116839dd23dcSLuca Ceresoli 		sel->r.width = src_fmt->width;
116939dd23dcSLuca Ceresoli 		sel->r.height = src_fmt->height;
117039dd23dcSLuca Ceresoli 		break;
117139dd23dcSLuca Ceresoli 	default:
117239dd23dcSLuca Ceresoli 		ret = -EINVAL;
117339dd23dcSLuca Ceresoli 	}
117439dd23dcSLuca Ceresoli 
117539dd23dcSLuca Ceresoli 	mutex_unlock(&imx274->lock);
117639dd23dcSLuca Ceresoli 
117739dd23dcSLuca Ceresoli 	return ret;
117839dd23dcSLuca Ceresoli }
117939dd23dcSLuca Ceresoli 
imx274_set_selection_crop(struct stimx274 * imx274,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)118039dd23dcSLuca Ceresoli static int imx274_set_selection_crop(struct stimx274 *imx274,
11810d346d2aSTomi Valkeinen 				     struct v4l2_subdev_state *sd_state,
118239dd23dcSLuca Ceresoli 				     struct v4l2_subdev_selection *sel)
118339dd23dcSLuca Ceresoli {
118439dd23dcSLuca Ceresoli 	struct v4l2_rect *tgt_crop;
118539dd23dcSLuca Ceresoli 	struct v4l2_rect new_crop;
118639dd23dcSLuca Ceresoli 	bool size_changed;
118739dd23dcSLuca Ceresoli 
118839dd23dcSLuca Ceresoli 	/*
118939dd23dcSLuca Ceresoli 	 * h_step could be 12 or 24 depending on the binning. But we
119039dd23dcSLuca Ceresoli 	 * won't know the binning until we choose the mode later in
119139dd23dcSLuca Ceresoli 	 * __imx274_change_compose(). Thus let's be safe and use the
119239dd23dcSLuca Ceresoli 	 * most conservative value in all cases.
119339dd23dcSLuca Ceresoli 	 */
119439dd23dcSLuca Ceresoli 	const u32 h_step = 24;
119539dd23dcSLuca Ceresoli 
119639dd23dcSLuca Ceresoli 	new_crop.width = min_t(u32,
119739dd23dcSLuca Ceresoli 			       IMX274_ROUND(sel->r.width, h_step, sel->flags),
119839dd23dcSLuca Ceresoli 			       IMX274_MAX_WIDTH);
119939dd23dcSLuca Ceresoli 
120039dd23dcSLuca Ceresoli 	/* Constraint: HTRIMMING_END - HTRIMMING_START >= 144 */
120139dd23dcSLuca Ceresoli 	if (new_crop.width < 144)
120239dd23dcSLuca Ceresoli 		new_crop.width = 144;
120339dd23dcSLuca Ceresoli 
120439dd23dcSLuca Ceresoli 	new_crop.left = min_t(u32,
120539dd23dcSLuca Ceresoli 			      IMX274_ROUND(sel->r.left, h_step, 0),
120639dd23dcSLuca Ceresoli 			      IMX274_MAX_WIDTH - new_crop.width);
120739dd23dcSLuca Ceresoli 
120839dd23dcSLuca Ceresoli 	new_crop.height = min_t(u32,
120939dd23dcSLuca Ceresoli 				IMX274_ROUND(sel->r.height, 2, sel->flags),
121039dd23dcSLuca Ceresoli 				IMX274_MAX_HEIGHT);
121139dd23dcSLuca Ceresoli 
121239dd23dcSLuca Ceresoli 	new_crop.top = min_t(u32, IMX274_ROUND(sel->r.top, 2, 0),
121339dd23dcSLuca Ceresoli 			     IMX274_MAX_HEIGHT - new_crop.height);
121439dd23dcSLuca Ceresoli 
121539dd23dcSLuca Ceresoli 	sel->r = new_crop;
121639dd23dcSLuca Ceresoli 
121739dd23dcSLuca Ceresoli 	if (sel->which == V4L2_SUBDEV_FORMAT_TRY)
12180d346d2aSTomi Valkeinen 		tgt_crop = &sd_state->pads->try_crop;
121939dd23dcSLuca Ceresoli 	else
122039dd23dcSLuca Ceresoli 		tgt_crop = &imx274->crop;
122139dd23dcSLuca Ceresoli 
122239dd23dcSLuca Ceresoli 	mutex_lock(&imx274->lock);
122339dd23dcSLuca Ceresoli 
122439dd23dcSLuca Ceresoli 	size_changed = (new_crop.width != tgt_crop->width ||
122539dd23dcSLuca Ceresoli 			new_crop.height != tgt_crop->height);
122639dd23dcSLuca Ceresoli 
122739dd23dcSLuca Ceresoli 	/* __imx274_change_compose needs the new size in *tgt_crop */
122839dd23dcSLuca Ceresoli 	*tgt_crop = new_crop;
122939dd23dcSLuca Ceresoli 
123039dd23dcSLuca Ceresoli 	/* if crop size changed then reset the output image size */
123139dd23dcSLuca Ceresoli 	if (size_changed)
12320d346d2aSTomi Valkeinen 		__imx274_change_compose(imx274, sd_state, sel->which,
123339dd23dcSLuca Ceresoli 					&new_crop.width, &new_crop.height,
123439dd23dcSLuca Ceresoli 					sel->flags);
123539dd23dcSLuca Ceresoli 
123639dd23dcSLuca Ceresoli 	mutex_unlock(&imx274->lock);
123739dd23dcSLuca Ceresoli 
123839dd23dcSLuca Ceresoli 	return 0;
123939dd23dcSLuca Ceresoli }
124039dd23dcSLuca Ceresoli 
imx274_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)124139dd23dcSLuca Ceresoli static int imx274_set_selection(struct v4l2_subdev *sd,
12420d346d2aSTomi Valkeinen 				struct v4l2_subdev_state *sd_state,
124339dd23dcSLuca Ceresoli 				struct v4l2_subdev_selection *sel)
124439dd23dcSLuca Ceresoli {
124539dd23dcSLuca Ceresoli 	struct stimx274 *imx274 = to_imx274(sd);
124639dd23dcSLuca Ceresoli 
124739dd23dcSLuca Ceresoli 	if (sel->pad != 0)
124839dd23dcSLuca Ceresoli 		return -EINVAL;
124939dd23dcSLuca Ceresoli 
125039dd23dcSLuca Ceresoli 	if (sel->target == V4L2_SEL_TGT_CROP)
12510d346d2aSTomi Valkeinen 		return imx274_set_selection_crop(imx274, sd_state, sel);
125239dd23dcSLuca Ceresoli 
125339dd23dcSLuca Ceresoli 	if (sel->target == V4L2_SEL_TGT_COMPOSE) {
125439dd23dcSLuca Ceresoli 		int err;
125539dd23dcSLuca Ceresoli 
125639dd23dcSLuca Ceresoli 		mutex_lock(&imx274->lock);
12570d346d2aSTomi Valkeinen 		err =  __imx274_change_compose(imx274, sd_state, sel->which,
125839dd23dcSLuca Ceresoli 					       &sel->r.width, &sel->r.height,
125939dd23dcSLuca Ceresoli 					       sel->flags);
126039dd23dcSLuca Ceresoli 		mutex_unlock(&imx274->lock);
126139dd23dcSLuca Ceresoli 
126239dd23dcSLuca Ceresoli 		/*
126339dd23dcSLuca Ceresoli 		 * __imx274_change_compose already set width and
126439dd23dcSLuca Ceresoli 		 * height in set->r, we still need to set top-left
126539dd23dcSLuca Ceresoli 		 */
126639dd23dcSLuca Ceresoli 		if (!err) {
126739dd23dcSLuca Ceresoli 			sel->r.top = 0;
126839dd23dcSLuca Ceresoli 			sel->r.left = 0;
126939dd23dcSLuca Ceresoli 		}
127039dd23dcSLuca Ceresoli 
127139dd23dcSLuca Ceresoli 		return err;
127239dd23dcSLuca Ceresoli 	}
127339dd23dcSLuca Ceresoli 
127439dd23dcSLuca Ceresoli 	return -EINVAL;
127539dd23dcSLuca Ceresoli }
127639dd23dcSLuca Ceresoli 
imx274_apply_trimming(struct stimx274 * imx274)127739dd23dcSLuca Ceresoli static int imx274_apply_trimming(struct stimx274 *imx274)
127839dd23dcSLuca Ceresoli {
127939dd23dcSLuca Ceresoli 	u32 h_start;
128039dd23dcSLuca Ceresoli 	u32 h_end;
128139dd23dcSLuca Ceresoli 	u32 hmax;
128239dd23dcSLuca Ceresoli 	u32 v_cut;
128339dd23dcSLuca Ceresoli 	s32 v_pos;
128439dd23dcSLuca Ceresoli 	u32 write_v_size;
128539dd23dcSLuca Ceresoli 	u32 y_out_size;
128639dd23dcSLuca Ceresoli 	int err;
128739dd23dcSLuca Ceresoli 
128839dd23dcSLuca Ceresoli 	h_start = imx274->crop.left + 12;
128939dd23dcSLuca Ceresoli 	h_end = h_start + imx274->crop.width;
129039dd23dcSLuca Ceresoli 
129139dd23dcSLuca Ceresoli 	/* Use the minimum allowed value of HMAX */
129239dd23dcSLuca Ceresoli 	/* Note: except in mode 1, (width / 16 + 23) is always < hmax_min */
129339dd23dcSLuca Ceresoli 	/* Note: 260 is the minimum HMAX in all implemented modes */
129439dd23dcSLuca Ceresoli 	hmax = max_t(u32, 260, (imx274->crop.width) / 16 + 23);
129539dd23dcSLuca Ceresoli 
129639dd23dcSLuca Ceresoli 	/* invert v_pos if VFLIP */
129739dd23dcSLuca Ceresoli 	v_pos = imx274->ctrls.vflip->cur.val ?
129839dd23dcSLuca Ceresoli 		(-imx274->crop.top / 2) : (imx274->crop.top / 2);
129939dd23dcSLuca Ceresoli 	v_cut = (IMX274_MAX_HEIGHT - imx274->crop.height) / 2;
130039dd23dcSLuca Ceresoli 	write_v_size = imx274->crop.height + 22;
1301c87bfb62SSowjanya Komatineni 	y_out_size   = imx274->crop.height;
130239dd23dcSLuca Ceresoli 
130339dd23dcSLuca Ceresoli 	err = imx274_write_mbreg(imx274, IMX274_HMAX_REG_LSB, hmax, 2);
130439dd23dcSLuca Ceresoli 	if (!err)
130539dd23dcSLuca Ceresoli 		err = imx274_write_mbreg(imx274, IMX274_HTRIM_EN_REG, 1, 1);
130639dd23dcSLuca Ceresoli 	if (!err)
130739dd23dcSLuca Ceresoli 		err = imx274_write_mbreg(imx274, IMX274_HTRIM_START_REG_LSB,
130839dd23dcSLuca Ceresoli 					 h_start, 2);
130939dd23dcSLuca Ceresoli 	if (!err)
131039dd23dcSLuca Ceresoli 		err = imx274_write_mbreg(imx274, IMX274_HTRIM_END_REG_LSB,
131139dd23dcSLuca Ceresoli 					 h_end, 2);
131239dd23dcSLuca Ceresoli 	if (!err)
131339dd23dcSLuca Ceresoli 		err = imx274_write_mbreg(imx274, IMX274_VWIDCUTEN_REG, 1, 1);
131439dd23dcSLuca Ceresoli 	if (!err)
131539dd23dcSLuca Ceresoli 		err = imx274_write_mbreg(imx274, IMX274_VWIDCUT_REG_LSB,
131639dd23dcSLuca Ceresoli 					 v_cut, 2);
131739dd23dcSLuca Ceresoli 	if (!err)
131839dd23dcSLuca Ceresoli 		err = imx274_write_mbreg(imx274, IMX274_VWINPOS_REG_LSB,
131939dd23dcSLuca Ceresoli 					 v_pos, 2);
132039dd23dcSLuca Ceresoli 	if (!err)
132139dd23dcSLuca Ceresoli 		err = imx274_write_mbreg(imx274, IMX274_WRITE_VSIZE_REG_LSB,
132239dd23dcSLuca Ceresoli 					 write_v_size, 2);
132339dd23dcSLuca Ceresoli 	if (!err)
132439dd23dcSLuca Ceresoli 		err = imx274_write_mbreg(imx274, IMX274_Y_OUT_SIZE_REG_LSB,
132539dd23dcSLuca Ceresoli 					 y_out_size, 2);
132639dd23dcSLuca Ceresoli 
132739dd23dcSLuca Ceresoli 	return err;
132839dd23dcSLuca Ceresoli }
132939dd23dcSLuca Ceresoli 
13300985dd30SLeon Luo /**
13310985dd30SLeon Luo  * imx274_g_frame_interval - Get the frame interval
13320985dd30SLeon Luo  * @sd: Pointer to V4L2 Sub device structure
13330985dd30SLeon Luo  * @fi: Pointer to V4l2 Sub device frame interval structure
13340985dd30SLeon Luo  *
13350985dd30SLeon Luo  * This function is used to get the frame interval.
13360985dd30SLeon Luo  *
13370985dd30SLeon Luo  * Return: 0 on success
13380985dd30SLeon Luo  */
imx274_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)13390985dd30SLeon Luo static int imx274_g_frame_interval(struct v4l2_subdev *sd,
13400985dd30SLeon Luo 				   struct v4l2_subdev_frame_interval *fi)
13410985dd30SLeon Luo {
13420985dd30SLeon Luo 	struct stimx274 *imx274 = to_imx274(sd);
13430985dd30SLeon Luo 
13440985dd30SLeon Luo 	fi->interval = imx274->frame_interval;
13450985dd30SLeon Luo 	dev_dbg(&imx274->client->dev, "%s frame rate = %d / %d\n",
13460985dd30SLeon Luo 		__func__, imx274->frame_interval.numerator,
13470985dd30SLeon Luo 		imx274->frame_interval.denominator);
13480985dd30SLeon Luo 
13490985dd30SLeon Luo 	return 0;
13500985dd30SLeon Luo }
13510985dd30SLeon Luo 
13520985dd30SLeon Luo /**
13530985dd30SLeon Luo  * imx274_s_frame_interval - Set the frame interval
13540985dd30SLeon Luo  * @sd: Pointer to V4L2 Sub device structure
13550985dd30SLeon Luo  * @fi: Pointer to V4l2 Sub device frame interval structure
13560985dd30SLeon Luo  *
13570985dd30SLeon Luo  * This function is used to set the frame intervavl.
13580985dd30SLeon Luo  *
13590985dd30SLeon Luo  * Return: 0 on success
13600985dd30SLeon Luo  */
imx274_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)13610985dd30SLeon Luo static int imx274_s_frame_interval(struct v4l2_subdev *sd,
13620985dd30SLeon Luo 				   struct v4l2_subdev_frame_interval *fi)
13630985dd30SLeon Luo {
13640985dd30SLeon Luo 	struct stimx274 *imx274 = to_imx274(sd);
13650985dd30SLeon Luo 	struct v4l2_ctrl *ctrl = imx274->ctrls.exposure;
13660985dd30SLeon Luo 	int min, max, def;
13670985dd30SLeon Luo 	int ret;
13680985dd30SLeon Luo 
1369da653498SEugen Hristev 	ret = pm_runtime_resume_and_get(&imx274->client->dev);
1370da653498SEugen Hristev 	if (ret < 0)
1371da653498SEugen Hristev 		return ret;
1372da653498SEugen Hristev 
13730985dd30SLeon Luo 	mutex_lock(&imx274->lock);
13740985dd30SLeon Luo 	ret = imx274_set_frame_interval(imx274, fi->interval);
13750985dd30SLeon Luo 
13760985dd30SLeon Luo 	if (!ret) {
137749b20d98SHans Verkuil 		fi->interval = imx274->frame_interval;
137849b20d98SHans Verkuil 
13790985dd30SLeon Luo 		/*
13800985dd30SLeon Luo 		 * exposure time range is decided by frame interval
138101343391SLuca Ceresoli 		 * need to update it after frame interval changes
13820985dd30SLeon Luo 		 */
13830985dd30SLeon Luo 		min = IMX274_MIN_EXPOSURE_TIME;
13840985dd30SLeon Luo 		max = fi->interval.numerator * 1000000
13850985dd30SLeon Luo 			/ fi->interval.denominator;
13860985dd30SLeon Luo 		def = max;
13879a4619efSJia-Ju Bai 		ret = __v4l2_ctrl_modify_range(ctrl, min, max, 1, def);
13889a4619efSJia-Ju Bai 		if (ret) {
13890985dd30SLeon Luo 			dev_err(&imx274->client->dev,
13900985dd30SLeon Luo 				"Exposure ctrl range update failed\n");
13910985dd30SLeon Luo 			goto unlock;
13920985dd30SLeon Luo 		}
13930985dd30SLeon Luo 
13940985dd30SLeon Luo 		/* update exposure time accordingly */
1395cf908704SLuca Ceresoli 		imx274_set_exposure(imx274, ctrl->val);
13960985dd30SLeon Luo 
13970985dd30SLeon Luo 		dev_dbg(&imx274->client->dev, "set frame interval to %uus\n",
13980985dd30SLeon Luo 			fi->interval.numerator * 1000000
13990985dd30SLeon Luo 			/ fi->interval.denominator);
14000985dd30SLeon Luo 	}
14010985dd30SLeon Luo 
14020985dd30SLeon Luo unlock:
14030985dd30SLeon Luo 	mutex_unlock(&imx274->lock);
1404da653498SEugen Hristev 	pm_runtime_put(&imx274->client->dev);
14050985dd30SLeon Luo 
14060985dd30SLeon Luo 	return ret;
14070985dd30SLeon Luo }
14080985dd30SLeon Luo 
14090985dd30SLeon Luo /**
14100985dd30SLeon Luo  * imx274_load_default - load default control values
14110985dd30SLeon Luo  * @priv: Pointer to device structure
14120985dd30SLeon Luo  *
14130985dd30SLeon Luo  * Return: 0 on success, errors otherwise
14140985dd30SLeon Luo  */
imx274_load_default(struct stimx274 * priv)1415ad97bc37SSowjanya Komatineni static void imx274_load_default(struct stimx274 *priv)
14160985dd30SLeon Luo {
14170985dd30SLeon Luo 	/* load default control values */
14180985dd30SLeon Luo 	priv->frame_interval.numerator = 1;
14190985dd30SLeon Luo 	priv->frame_interval.denominator = IMX274_DEF_FRAME_RATE;
14200985dd30SLeon Luo 	priv->ctrls.exposure->val = 1000000 / IMX274_DEF_FRAME_RATE;
14210985dd30SLeon Luo 	priv->ctrls.gain->val = IMX274_DEF_GAIN;
14220985dd30SLeon Luo 	priv->ctrls.vflip->val = 0;
14230985dd30SLeon Luo 	priv->ctrls.test_pattern->val = TEST_PATTERN_DISABLED;
14240985dd30SLeon Luo }
14250985dd30SLeon Luo 
14260985dd30SLeon Luo /**
14270985dd30SLeon Luo  * imx274_s_stream - It is used to start/stop the streaming.
14280985dd30SLeon Luo  * @sd: V4L2 Sub device
14290985dd30SLeon Luo  * @on: Flag (True / False)
14300985dd30SLeon Luo  *
14310985dd30SLeon Luo  * This function controls the start or stop of streaming for the
14320985dd30SLeon Luo  * imx274 sensor.
14330985dd30SLeon Luo  *
14340985dd30SLeon Luo  * Return: 0 on success, errors otherwise
14350985dd30SLeon Luo  */
imx274_s_stream(struct v4l2_subdev * sd,int on)14360985dd30SLeon Luo static int imx274_s_stream(struct v4l2_subdev *sd, int on)
14370985dd30SLeon Luo {
14380985dd30SLeon Luo 	struct stimx274 *imx274 = to_imx274(sd);
14390985dd30SLeon Luo 	int ret = 0;
14400985dd30SLeon Luo 
14414317322dSLuca Ceresoli 	dev_dbg(&imx274->client->dev, "%s : %s, mode index = %td\n", __func__,
14424317322dSLuca Ceresoli 		on ? "Stream Start" : "Stream Stop",
14439648cb57SLuca Ceresoli 		imx274->mode - &imx274_modes[0]);
14440985dd30SLeon Luo 
14450985dd30SLeon Luo 	mutex_lock(&imx274->lock);
14460985dd30SLeon Luo 
14470985dd30SLeon Luo 	if (on) {
1448bb94b8f3SMauro Carvalho Chehab 		ret = pm_runtime_resume_and_get(&imx274->client->dev);
1449ad97bc37SSowjanya Komatineni 		if (ret < 0) {
1450ad97bc37SSowjanya Komatineni 			mutex_unlock(&imx274->lock);
1451ad97bc37SSowjanya Komatineni 			return ret;
1452ad97bc37SSowjanya Komatineni 		}
1453ad97bc37SSowjanya Komatineni 
14540985dd30SLeon Luo 		/* load mode registers */
145596a2c731SLuca Ceresoli 		ret = imx274_mode_regs(imx274);
14560985dd30SLeon Luo 		if (ret)
14570985dd30SLeon Luo 			goto fail;
14580985dd30SLeon Luo 
145939dd23dcSLuca Ceresoli 		ret = imx274_apply_trimming(imx274);
146039dd23dcSLuca Ceresoli 		if (ret)
146139dd23dcSLuca Ceresoli 			goto fail;
146239dd23dcSLuca Ceresoli 
14630985dd30SLeon Luo 		/*
14644e05d5f2SEugen Hristev 		 * update frame rate & exposure. if the last mode is different,
14650985dd30SLeon Luo 		 * HMAX could be changed. As the result, frame rate & exposure
14660985dd30SLeon Luo 		 * are changed.
14670985dd30SLeon Luo 		 * gain is not affected.
14680985dd30SLeon Luo 		 */
14690985dd30SLeon Luo 		ret = imx274_set_frame_interval(imx274,
14700985dd30SLeon Luo 						imx274->frame_interval);
14710985dd30SLeon Luo 		if (ret)
14720985dd30SLeon Luo 			goto fail;
14730985dd30SLeon Luo 
14740985dd30SLeon Luo 		/* start stream */
14750985dd30SLeon Luo 		ret = imx274_start_stream(imx274);
14760985dd30SLeon Luo 		if (ret)
14770985dd30SLeon Luo 			goto fail;
14780985dd30SLeon Luo 	} else {
14790985dd30SLeon Luo 		/* stop stream */
14808ed8bba7SLuca Ceresoli 		ret = imx274_write_table(imx274, imx274_stop);
14810985dd30SLeon Luo 		if (ret)
14820985dd30SLeon Luo 			goto fail;
1483ad97bc37SSowjanya Komatineni 
1484ad97bc37SSowjanya Komatineni 		pm_runtime_put(&imx274->client->dev);
14850985dd30SLeon Luo 	}
14860985dd30SLeon Luo 
14870985dd30SLeon Luo 	mutex_unlock(&imx274->lock);
14884317322dSLuca Ceresoli 	dev_dbg(&imx274->client->dev, "%s : Done\n", __func__);
14890985dd30SLeon Luo 	return 0;
14900985dd30SLeon Luo 
14910985dd30SLeon Luo fail:
1492ad97bc37SSowjanya Komatineni 	pm_runtime_put(&imx274->client->dev);
14930985dd30SLeon Luo 	mutex_unlock(&imx274->lock);
14940985dd30SLeon Luo 	dev_err(&imx274->client->dev, "s_stream failed\n");
14950985dd30SLeon Luo 	return ret;
14960985dd30SLeon Luo }
14970985dd30SLeon Luo 
14980985dd30SLeon Luo /*
14990985dd30SLeon Luo  * imx274_get_frame_length - Function for obtaining current frame length
15000985dd30SLeon Luo  * @priv: Pointer to device structure
1501358ed66bSEugen Hristev  * @val: Pointer to obtained value
15020985dd30SLeon Luo  *
15030985dd30SLeon Luo  * frame_length = vmax x (svr + 1), in unit of hmax.
15040985dd30SLeon Luo  *
15050985dd30SLeon Luo  * Return: 0 on success
15060985dd30SLeon Luo  */
imx274_get_frame_length(struct stimx274 * priv,u32 * val)15070985dd30SLeon Luo static int imx274_get_frame_length(struct stimx274 *priv, u32 *val)
15080985dd30SLeon Luo {
15090985dd30SLeon Luo 	int err;
1510ca017467SLuca Ceresoli 	u32 svr;
15110985dd30SLeon Luo 	u32 vmax;
15120985dd30SLeon Luo 
1513ca017467SLuca Ceresoli 	err = imx274_read_mbreg(priv, IMX274_SVR_REG_LSB, &svr, 2);
15140985dd30SLeon Luo 	if (err)
15150985dd30SLeon Luo 		goto fail;
15160985dd30SLeon Luo 
1517ca017467SLuca Ceresoli 	err = imx274_read_mbreg(priv, IMX274_VMAX_REG_3, &vmax, 3);
15180985dd30SLeon Luo 	if (err)
15190985dd30SLeon Luo 		goto fail;
15200985dd30SLeon Luo 
15210985dd30SLeon Luo 	*val = vmax * (svr + 1);
15220985dd30SLeon Luo 
15230985dd30SLeon Luo 	return 0;
15240985dd30SLeon Luo 
15250985dd30SLeon Luo fail:
15260985dd30SLeon Luo 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
15270985dd30SLeon Luo 	return err;
15280985dd30SLeon Luo }
15290985dd30SLeon Luo 
imx274_clamp_coarse_time(struct stimx274 * priv,u32 * val,u32 * frame_length)15300985dd30SLeon Luo static int imx274_clamp_coarse_time(struct stimx274 *priv, u32 *val,
15310985dd30SLeon Luo 				    u32 *frame_length)
15320985dd30SLeon Luo {
15330985dd30SLeon Luo 	int err;
15340985dd30SLeon Luo 
15350985dd30SLeon Luo 	err = imx274_get_frame_length(priv, frame_length);
15360985dd30SLeon Luo 	if (err)
15370985dd30SLeon Luo 		return err;
15380985dd30SLeon Luo 
153996a2c731SLuca Ceresoli 	if (*frame_length < priv->mode->min_frame_len)
154096a2c731SLuca Ceresoli 		*frame_length =  priv->mode->min_frame_len;
15410985dd30SLeon Luo 
15420985dd30SLeon Luo 	*val = *frame_length - *val; /* convert to raw shr */
15430985dd30SLeon Luo 	if (*val > *frame_length - IMX274_SHR_LIMIT_CONST)
15440985dd30SLeon Luo 		*val = *frame_length - IMX274_SHR_LIMIT_CONST;
154596a2c731SLuca Ceresoli 	else if (*val < priv->mode->min_SHR)
154696a2c731SLuca Ceresoli 		*val = priv->mode->min_SHR;
15470985dd30SLeon Luo 
15480985dd30SLeon Luo 	return 0;
15490985dd30SLeon Luo }
15500985dd30SLeon Luo 
15510985dd30SLeon Luo /*
15520985dd30SLeon Luo  * imx274_set_digital gain - Function called when setting digital gain
15530985dd30SLeon Luo  * @priv: Pointer to device structure
15540985dd30SLeon Luo  * @dgain: Value of digital gain.
15550985dd30SLeon Luo  *
15560985dd30SLeon Luo  * Digital gain has only 4 steps: 1x, 2x, 4x, and 8x
15570985dd30SLeon Luo  *
15580985dd30SLeon Luo  * Return: 0 on success
15590985dd30SLeon Luo  */
imx274_set_digital_gain(struct stimx274 * priv,u32 dgain)15600985dd30SLeon Luo static int imx274_set_digital_gain(struct stimx274 *priv, u32 dgain)
15610985dd30SLeon Luo {
15620985dd30SLeon Luo 	u8 reg_val;
15630985dd30SLeon Luo 
15640985dd30SLeon Luo 	reg_val = ffs(dgain);
15650985dd30SLeon Luo 
15660985dd30SLeon Luo 	if (reg_val)
15670985dd30SLeon Luo 		reg_val--;
15680985dd30SLeon Luo 
15690985dd30SLeon Luo 	reg_val = clamp(reg_val, (u8)0, (u8)3);
15700985dd30SLeon Luo 
15710985dd30SLeon Luo 	return imx274_write_reg(priv, IMX274_DIGITAL_GAIN_REG,
15720985dd30SLeon Luo 				reg_val & IMX274_MASK_LSB_4_BITS);
15730985dd30SLeon Luo }
15740985dd30SLeon Luo 
15750985dd30SLeon Luo /*
15760985dd30SLeon Luo  * imx274_set_gain - Function called when setting gain
15770985dd30SLeon Luo  * @priv: Pointer to device structure
15780985dd30SLeon Luo  * @val: Value of gain. the real value = val << IMX274_GAIN_SHIFT;
15790985dd30SLeon Luo  * @ctrl: v4l2 control pointer
15800985dd30SLeon Luo  *
15810985dd30SLeon Luo  * Set the gain based on input value.
15820985dd30SLeon Luo  * The caller should hold the mutex lock imx274->lock if necessary
15830985dd30SLeon Luo  *
15840985dd30SLeon Luo  * Return: 0 on success
15850985dd30SLeon Luo  */
imx274_set_gain(struct stimx274 * priv,struct v4l2_ctrl * ctrl)15860985dd30SLeon Luo static int imx274_set_gain(struct stimx274 *priv, struct v4l2_ctrl *ctrl)
15870985dd30SLeon Luo {
15880985dd30SLeon Luo 	int err;
15890985dd30SLeon Luo 	u32 gain, analog_gain, digital_gain, gain_reg;
15900985dd30SLeon Luo 
15910985dd30SLeon Luo 	gain = (u32)(ctrl->val);
15920985dd30SLeon Luo 
15930985dd30SLeon Luo 	dev_dbg(&priv->client->dev,
15940985dd30SLeon Luo 		"%s : input gain = %d.%d\n", __func__,
15950985dd30SLeon Luo 		gain >> IMX274_GAIN_SHIFT,
15960985dd30SLeon Luo 		((gain & IMX274_GAIN_SHIFT_MASK) * 100) >> IMX274_GAIN_SHIFT);
15970985dd30SLeon Luo 
15980985dd30SLeon Luo 	if (gain > IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN)
15990985dd30SLeon Luo 		gain = IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN;
16000985dd30SLeon Luo 	else if (gain < IMX274_MIN_GAIN)
16010985dd30SLeon Luo 		gain = IMX274_MIN_GAIN;
16020985dd30SLeon Luo 
16030985dd30SLeon Luo 	if (gain <= IMX274_MAX_ANALOG_GAIN)
16040985dd30SLeon Luo 		digital_gain = 1;
16050985dd30SLeon Luo 	else if (gain <= IMX274_MAX_ANALOG_GAIN * 2)
16060985dd30SLeon Luo 		digital_gain = 2;
16070985dd30SLeon Luo 	else if (gain <= IMX274_MAX_ANALOG_GAIN * 4)
16080985dd30SLeon Luo 		digital_gain = 4;
16090985dd30SLeon Luo 	else
16100985dd30SLeon Luo 		digital_gain = IMX274_MAX_DIGITAL_GAIN;
16110985dd30SLeon Luo 
16120985dd30SLeon Luo 	analog_gain = gain / digital_gain;
16130985dd30SLeon Luo 
16140985dd30SLeon Luo 	dev_dbg(&priv->client->dev,
16150985dd30SLeon Luo 		"%s : digital gain = %d, analog gain = %d.%d\n",
16160985dd30SLeon Luo 		__func__, digital_gain, analog_gain >> IMX274_GAIN_SHIFT,
16170985dd30SLeon Luo 		((analog_gain & IMX274_GAIN_SHIFT_MASK) * 100)
16180985dd30SLeon Luo 		>> IMX274_GAIN_SHIFT);
16190985dd30SLeon Luo 
16200985dd30SLeon Luo 	err = imx274_set_digital_gain(priv, digital_gain);
16210985dd30SLeon Luo 	if (err)
16220985dd30SLeon Luo 		goto fail;
16230985dd30SLeon Luo 
16240985dd30SLeon Luo 	/* convert to register value, refer to imx274 datasheet */
16250985dd30SLeon Luo 	gain_reg = (u32)IMX274_GAIN_CONST -
16260985dd30SLeon Luo 		(IMX274_GAIN_CONST << IMX274_GAIN_SHIFT) / analog_gain;
16270985dd30SLeon Luo 	if (gain_reg > IMX274_GAIN_REG_MAX)
16280985dd30SLeon Luo 		gain_reg = IMX274_GAIN_REG_MAX;
16290985dd30SLeon Luo 
1630279b4b9aSLuca Ceresoli 	err = imx274_write_mbreg(priv, IMX274_ANALOG_GAIN_ADDR_LSB, gain_reg,
1631279b4b9aSLuca Ceresoli 				 2);
16320985dd30SLeon Luo 	if (err)
16330985dd30SLeon Luo 		goto fail;
16340985dd30SLeon Luo 
16350985dd30SLeon Luo 	if (IMX274_GAIN_CONST - gain_reg == 0) {
16360985dd30SLeon Luo 		err = -EINVAL;
16370985dd30SLeon Luo 		goto fail;
16380985dd30SLeon Luo 	}
16390985dd30SLeon Luo 
16400985dd30SLeon Luo 	/* convert register value back to gain value */
16410985dd30SLeon Luo 	ctrl->val = (IMX274_GAIN_CONST << IMX274_GAIN_SHIFT)
16420985dd30SLeon Luo 			/ (IMX274_GAIN_CONST - gain_reg) * digital_gain;
16430985dd30SLeon Luo 
16440985dd30SLeon Luo 	dev_dbg(&priv->client->dev,
16450985dd30SLeon Luo 		"%s : GAIN control success, gain_reg = %d, new gain = %d\n",
16460985dd30SLeon Luo 		__func__, gain_reg, ctrl->val);
16470985dd30SLeon Luo 
16480985dd30SLeon Luo 	return 0;
16490985dd30SLeon Luo 
16500985dd30SLeon Luo fail:
16510985dd30SLeon Luo 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
16520985dd30SLeon Luo 	return err;
16530985dd30SLeon Luo }
16540985dd30SLeon Luo 
16550985dd30SLeon Luo /*
16560985dd30SLeon Luo  * imx274_set_coarse_time - Function called when setting SHR value
16570985dd30SLeon Luo  * @priv: Pointer to device structure
16580985dd30SLeon Luo  * @val: Value for exposure time in number of line_length, or [HMAX]
16590985dd30SLeon Luo  *
16600985dd30SLeon Luo  * Set SHR value based on input value.
16610985dd30SLeon Luo  *
16620985dd30SLeon Luo  * Return: 0 on success
16630985dd30SLeon Luo  */
imx274_set_coarse_time(struct stimx274 * priv,u32 * val)16640985dd30SLeon Luo static int imx274_set_coarse_time(struct stimx274 *priv, u32 *val)
16650985dd30SLeon Luo {
16660985dd30SLeon Luo 	int err;
16670985dd30SLeon Luo 	u32 coarse_time, frame_length;
16680985dd30SLeon Luo 
16690985dd30SLeon Luo 	coarse_time = *val;
16700985dd30SLeon Luo 
16710985dd30SLeon Luo 	/* convert exposure_time to appropriate SHR value */
16720985dd30SLeon Luo 	err = imx274_clamp_coarse_time(priv, &coarse_time, &frame_length);
16730985dd30SLeon Luo 	if (err)
16740985dd30SLeon Luo 		goto fail;
16750985dd30SLeon Luo 
1676279b4b9aSLuca Ceresoli 	err = imx274_write_mbreg(priv, IMX274_SHR_REG_LSB, coarse_time, 2);
16770985dd30SLeon Luo 	if (err)
16780985dd30SLeon Luo 		goto fail;
16790985dd30SLeon Luo 
16800985dd30SLeon Luo 	*val = frame_length - coarse_time;
16810985dd30SLeon Luo 	return 0;
16820985dd30SLeon Luo 
16830985dd30SLeon Luo fail:
16840985dd30SLeon Luo 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
16850985dd30SLeon Luo 	return err;
16860985dd30SLeon Luo }
16870985dd30SLeon Luo 
16880985dd30SLeon Luo /*
16890985dd30SLeon Luo  * imx274_set_exposure - Function called when setting exposure time
16900985dd30SLeon Luo  * @priv: Pointer to device structure
16910985dd30SLeon Luo  * @val: Variable for exposure time, in the unit of micro-second
16920985dd30SLeon Luo  *
16930985dd30SLeon Luo  * Set exposure time based on input value.
16940985dd30SLeon Luo  * The caller should hold the mutex lock imx274->lock if necessary
16950985dd30SLeon Luo  *
16960985dd30SLeon Luo  * Return: 0 on success
16970985dd30SLeon Luo  */
imx274_set_exposure(struct stimx274 * priv,int val)16980985dd30SLeon Luo static int imx274_set_exposure(struct stimx274 *priv, int val)
16990985dd30SLeon Luo {
17000985dd30SLeon Luo 	int err;
1701ca017467SLuca Ceresoli 	u32 hmax;
17020985dd30SLeon Luo 	u32 coarse_time; /* exposure time in unit of line (HMAX)*/
17030985dd30SLeon Luo 
17040985dd30SLeon Luo 	dev_dbg(&priv->client->dev,
17050985dd30SLeon Luo 		"%s : EXPOSURE control input = %d\n", __func__, val);
17060985dd30SLeon Luo 
17070985dd30SLeon Luo 	/* step 1: convert input exposure_time (val) into number of 1[HMAX] */
17080985dd30SLeon Luo 
1709ca017467SLuca Ceresoli 	err = imx274_read_mbreg(priv, IMX274_HMAX_REG_LSB, &hmax, 2);
17100985dd30SLeon Luo 	if (err)
17110985dd30SLeon Luo 		goto fail;
1712ca017467SLuca Ceresoli 
17130985dd30SLeon Luo 	if (hmax == 0) {
17140985dd30SLeon Luo 		err = -EINVAL;
17150985dd30SLeon Luo 		goto fail;
17160985dd30SLeon Luo 	}
17170985dd30SLeon Luo 
17180985dd30SLeon Luo 	coarse_time = (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2 * val
171996a2c731SLuca Ceresoli 			- priv->mode->nocpiop) / hmax;
17200985dd30SLeon Luo 
17210985dd30SLeon Luo 	/* step 2: convert exposure_time into SHR value */
17220985dd30SLeon Luo 
17230985dd30SLeon Luo 	/* set SHR */
17240985dd30SLeon Luo 	err = imx274_set_coarse_time(priv, &coarse_time);
17250985dd30SLeon Luo 	if (err)
17260985dd30SLeon Luo 		goto fail;
17270985dd30SLeon Luo 
17280985dd30SLeon Luo 	priv->ctrls.exposure->val =
172996a2c731SLuca Ceresoli 			(coarse_time * hmax + priv->mode->nocpiop)
17300985dd30SLeon Luo 			/ (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2);
17310985dd30SLeon Luo 
17320985dd30SLeon Luo 	dev_dbg(&priv->client->dev,
17330985dd30SLeon Luo 		"%s : EXPOSURE control success\n", __func__);
17340985dd30SLeon Luo 	return 0;
17350985dd30SLeon Luo 
17360985dd30SLeon Luo fail:
17370985dd30SLeon Luo 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
17380985dd30SLeon Luo 
17390985dd30SLeon Luo 	return err;
17400985dd30SLeon Luo }
17410985dd30SLeon Luo 
17420985dd30SLeon Luo /*
17430985dd30SLeon Luo  * imx274_set_vflip - Function called when setting vertical flip
17440985dd30SLeon Luo  * @priv: Pointer to device structure
17450985dd30SLeon Luo  * @val: Value for vflip setting
17460985dd30SLeon Luo  *
17470985dd30SLeon Luo  * Set vertical flip based on input value.
17480985dd30SLeon Luo  * val = 0: normal, no vertical flip
17490985dd30SLeon Luo  * val = 1: vertical flip enabled
17500985dd30SLeon Luo  * The caller should hold the mutex lock imx274->lock if necessary
17510985dd30SLeon Luo  *
17520985dd30SLeon Luo  * Return: 0 on success
17530985dd30SLeon Luo  */
imx274_set_vflip(struct stimx274 * priv,int val)17540985dd30SLeon Luo static int imx274_set_vflip(struct stimx274 *priv, int val)
17550985dd30SLeon Luo {
17560985dd30SLeon Luo 	int err;
17570985dd30SLeon Luo 
17580985dd30SLeon Luo 	err = imx274_write_reg(priv, IMX274_VFLIP_REG, val);
17590985dd30SLeon Luo 	if (err) {
17609f67a5e2SLuca Ceresoli 		dev_err(&priv->client->dev, "VFLIP control error\n");
17610985dd30SLeon Luo 		return err;
17620985dd30SLeon Luo 	}
17630985dd30SLeon Luo 
17640985dd30SLeon Luo 	dev_dbg(&priv->client->dev,
17650985dd30SLeon Luo 		"%s : VFLIP control success\n", __func__);
17660985dd30SLeon Luo 
17670985dd30SLeon Luo 	return 0;
17680985dd30SLeon Luo }
17690985dd30SLeon Luo 
17700985dd30SLeon Luo /*
17710985dd30SLeon Luo  * imx274_set_test_pattern - Function called when setting test pattern
17720985dd30SLeon Luo  * @priv: Pointer to device structure
17730985dd30SLeon Luo  * @val: Variable for test pattern
17740985dd30SLeon Luo  *
17750985dd30SLeon Luo  * Set to different test patterns based on input value.
17760985dd30SLeon Luo  *
17770985dd30SLeon Luo  * Return: 0 on success
17780985dd30SLeon Luo  */
imx274_set_test_pattern(struct stimx274 * priv,int val)17790985dd30SLeon Luo static int imx274_set_test_pattern(struct stimx274 *priv, int val)
17800985dd30SLeon Luo {
17810985dd30SLeon Luo 	int err = 0;
17820985dd30SLeon Luo 
17830985dd30SLeon Luo 	if (val == TEST_PATTERN_DISABLED) {
17840985dd30SLeon Luo 		err = imx274_write_table(priv, imx274_tp_disabled);
17850985dd30SLeon Luo 	} else if (val <= TEST_PATTERN_V_COLOR_BARS) {
17860985dd30SLeon Luo 		err = imx274_write_reg(priv, IMX274_TEST_PATTERN_REG, val - 1);
17870985dd30SLeon Luo 		if (!err)
17880985dd30SLeon Luo 			err = imx274_write_table(priv, imx274_tp_regs);
17890985dd30SLeon Luo 	} else {
17900985dd30SLeon Luo 		err = -EINVAL;
17910985dd30SLeon Luo 	}
17920985dd30SLeon Luo 
17930985dd30SLeon Luo 	if (!err)
17940985dd30SLeon Luo 		dev_dbg(&priv->client->dev,
17950985dd30SLeon Luo 			"%s : TEST PATTERN control success\n", __func__);
17960985dd30SLeon Luo 	else
17970985dd30SLeon Luo 		dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
17980985dd30SLeon Luo 
17990985dd30SLeon Luo 	return err;
18000985dd30SLeon Luo }
18010985dd30SLeon Luo 
18020985dd30SLeon Luo /*
18030985dd30SLeon Luo  * imx274_set_frame_length - Function called when setting frame length
18040985dd30SLeon Luo  * @priv: Pointer to device structure
18050985dd30SLeon Luo  * @val: Variable for frame length (= VMAX, i.e. vertical drive period length)
18060985dd30SLeon Luo  *
18070985dd30SLeon Luo  * Set frame length based on input value.
18080985dd30SLeon Luo  *
18090985dd30SLeon Luo  * Return: 0 on success
18100985dd30SLeon Luo  */
imx274_set_frame_length(struct stimx274 * priv,u32 val)18110985dd30SLeon Luo static int imx274_set_frame_length(struct stimx274 *priv, u32 val)
18120985dd30SLeon Luo {
18130985dd30SLeon Luo 	int err;
18140985dd30SLeon Luo 	u32 frame_length;
18150985dd30SLeon Luo 
18160985dd30SLeon Luo 	dev_dbg(&priv->client->dev, "%s : input length = %d\n",
18170985dd30SLeon Luo 		__func__, val);
18180985dd30SLeon Luo 
18190985dd30SLeon Luo 	frame_length = (u32)val;
18200985dd30SLeon Luo 
1821279b4b9aSLuca Ceresoli 	err = imx274_write_mbreg(priv, IMX274_VMAX_REG_3, frame_length, 3);
18220985dd30SLeon Luo 	if (err)
18230985dd30SLeon Luo 		goto fail;
18240985dd30SLeon Luo 
18250985dd30SLeon Luo 	return 0;
18260985dd30SLeon Luo 
18270985dd30SLeon Luo fail:
18280985dd30SLeon Luo 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
18290985dd30SLeon Luo 	return err;
18300985dd30SLeon Luo }
18310985dd30SLeon Luo 
18320985dd30SLeon Luo /*
18330985dd30SLeon Luo  * imx274_set_frame_interval - Function called when setting frame interval
18340985dd30SLeon Luo  * @priv: Pointer to device structure
18350985dd30SLeon Luo  * @frame_interval: Variable for frame interval
18360985dd30SLeon Luo  *
18370985dd30SLeon Luo  * Change frame interval by updating VMAX value
18380985dd30SLeon Luo  * The caller should hold the mutex lock imx274->lock if necessary
18390985dd30SLeon Luo  *
18400985dd30SLeon Luo  * Return: 0 on success
18410985dd30SLeon Luo  */
imx274_set_frame_interval(struct stimx274 * priv,struct v4l2_fract frame_interval)18420985dd30SLeon Luo static int imx274_set_frame_interval(struct stimx274 *priv,
18430985dd30SLeon Luo 				     struct v4l2_fract frame_interval)
18440985dd30SLeon Luo {
18450985dd30SLeon Luo 	int err;
18460985dd30SLeon Luo 	u32 frame_length, req_frame_rate;
1847ca017467SLuca Ceresoli 	u32 svr;
1848ca017467SLuca Ceresoli 	u32 hmax;
18490985dd30SLeon Luo 
18500985dd30SLeon Luo 	dev_dbg(&priv->client->dev, "%s: input frame interval = %d / %d",
18510985dd30SLeon Luo 		__func__, frame_interval.numerator,
18520985dd30SLeon Luo 		frame_interval.denominator);
18530985dd30SLeon Luo 
185449b20d98SHans Verkuil 	if (frame_interval.numerator == 0 || frame_interval.denominator == 0) {
185549b20d98SHans Verkuil 		frame_interval.denominator = IMX274_DEF_FRAME_RATE;
185649b20d98SHans Verkuil 		frame_interval.numerator = 1;
18570985dd30SLeon Luo 	}
18580985dd30SLeon Luo 
18590985dd30SLeon Luo 	req_frame_rate = (u32)(frame_interval.denominator
18600985dd30SLeon Luo 				/ frame_interval.numerator);
18610985dd30SLeon Luo 
18620985dd30SLeon Luo 	/* boundary check */
186396a2c731SLuca Ceresoli 	if (req_frame_rate > priv->mode->max_fps) {
18640985dd30SLeon Luo 		frame_interval.numerator = 1;
186596a2c731SLuca Ceresoli 		frame_interval.denominator = priv->mode->max_fps;
18660985dd30SLeon Luo 	} else if (req_frame_rate < IMX274_MIN_FRAME_RATE) {
18670985dd30SLeon Luo 		frame_interval.numerator = 1;
18680985dd30SLeon Luo 		frame_interval.denominator = IMX274_MIN_FRAME_RATE;
18690985dd30SLeon Luo 	}
18700985dd30SLeon Luo 
18710985dd30SLeon Luo 	/*
18720985dd30SLeon Luo 	 * VMAX = 1/frame_rate x 72M / (SVR+1) / HMAX
18730985dd30SLeon Luo 	 * frame_length (i.e. VMAX) = (frame_interval) x 72M /(SVR+1) / HMAX
18740985dd30SLeon Luo 	 */
18750985dd30SLeon Luo 
1876ca017467SLuca Ceresoli 	err = imx274_read_mbreg(priv, IMX274_SVR_REG_LSB, &svr, 2);
18770985dd30SLeon Luo 	if (err)
18780985dd30SLeon Luo 		goto fail;
1879ca017467SLuca Ceresoli 
18800985dd30SLeon Luo 	dev_dbg(&priv->client->dev,
18810985dd30SLeon Luo 		"%s : register SVR = %d\n", __func__, svr);
18820985dd30SLeon Luo 
1883ca017467SLuca Ceresoli 	err = imx274_read_mbreg(priv, IMX274_HMAX_REG_LSB, &hmax, 2);
18840985dd30SLeon Luo 	if (err)
18850985dd30SLeon Luo 		goto fail;
1886ca017467SLuca Ceresoli 
18870985dd30SLeon Luo 	dev_dbg(&priv->client->dev,
18880985dd30SLeon Luo 		"%s : register HMAX = %d\n", __func__, hmax);
18890985dd30SLeon Luo 
18900985dd30SLeon Luo 	if (hmax == 0 || frame_interval.denominator == 0) {
18910985dd30SLeon Luo 		err = -EINVAL;
18920985dd30SLeon Luo 		goto fail;
18930985dd30SLeon Luo 	}
18940985dd30SLeon Luo 
18950985dd30SLeon Luo 	frame_length = IMX274_PIXCLK_CONST1 / (svr + 1) / hmax
18960985dd30SLeon Luo 					* frame_interval.numerator
18970985dd30SLeon Luo 					/ frame_interval.denominator;
18980985dd30SLeon Luo 
18990985dd30SLeon Luo 	err = imx274_set_frame_length(priv, frame_length);
19000985dd30SLeon Luo 	if (err)
19010985dd30SLeon Luo 		goto fail;
19020985dd30SLeon Luo 
19030985dd30SLeon Luo 	priv->frame_interval = frame_interval;
19040985dd30SLeon Luo 	return 0;
19050985dd30SLeon Luo 
19060985dd30SLeon Luo fail:
19070985dd30SLeon Luo 	dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
19080985dd30SLeon Luo 	return err;
19090985dd30SLeon Luo }
19100985dd30SLeon Luo 
imx274_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)19117218905aSEugen Hristev static int imx274_enum_mbus_code(struct v4l2_subdev *sd,
19127218905aSEugen Hristev 				 struct v4l2_subdev_state *sd_state,
19137218905aSEugen Hristev 				 struct v4l2_subdev_mbus_code_enum *code)
19147218905aSEugen Hristev {
19157218905aSEugen Hristev 	if (code->index > 0)
19167218905aSEugen Hristev 		return -EINVAL;
19177218905aSEugen Hristev 
19187218905aSEugen Hristev 	/* only supported format in the driver is Raw 10 bits SRGGB */
19197218905aSEugen Hristev 	code->code = MEDIA_BUS_FMT_SRGGB10_1X10;
19207218905aSEugen Hristev 
19217218905aSEugen Hristev 	return 0;
19227218905aSEugen Hristev }
19237218905aSEugen Hristev 
19240985dd30SLeon Luo static const struct v4l2_subdev_pad_ops imx274_pad_ops = {
19257218905aSEugen Hristev 	.enum_mbus_code = imx274_enum_mbus_code,
19260985dd30SLeon Luo 	.get_fmt = imx274_get_fmt,
19270985dd30SLeon Luo 	.set_fmt = imx274_set_fmt,
192839dd23dcSLuca Ceresoli 	.get_selection = imx274_get_selection,
192939dd23dcSLuca Ceresoli 	.set_selection = imx274_set_selection,
19300985dd30SLeon Luo };
19310985dd30SLeon Luo 
19320985dd30SLeon Luo static const struct v4l2_subdev_video_ops imx274_video_ops = {
19330985dd30SLeon Luo 	.g_frame_interval = imx274_g_frame_interval,
19340985dd30SLeon Luo 	.s_frame_interval = imx274_s_frame_interval,
19350985dd30SLeon Luo 	.s_stream = imx274_s_stream,
19360985dd30SLeon Luo };
19370985dd30SLeon Luo 
19380985dd30SLeon Luo static const struct v4l2_subdev_ops imx274_subdev_ops = {
19390985dd30SLeon Luo 	.pad = &imx274_pad_ops,
19400985dd30SLeon Luo 	.video = &imx274_video_ops,
19410985dd30SLeon Luo };
19420985dd30SLeon Luo 
19430985dd30SLeon Luo static const struct v4l2_ctrl_ops imx274_ctrl_ops = {
19440985dd30SLeon Luo 	.s_ctrl	= imx274_s_ctrl,
19450985dd30SLeon Luo };
19460985dd30SLeon Luo 
19470985dd30SLeon Luo static const struct of_device_id imx274_of_id_table[] = {
19480985dd30SLeon Luo 	{ .compatible = "sony,imx274" },
19490985dd30SLeon Luo 	{ }
19500985dd30SLeon Luo };
19510985dd30SLeon Luo MODULE_DEVICE_TABLE(of, imx274_of_id_table);
19520985dd30SLeon Luo 
19530985dd30SLeon Luo static const struct i2c_device_id imx274_id[] = {
19540985dd30SLeon Luo 	{ "IMX274", 0 },
19550985dd30SLeon Luo 	{ }
19560985dd30SLeon Luo };
19570985dd30SLeon Luo MODULE_DEVICE_TABLE(i2c, imx274_id);
19580985dd30SLeon Luo 
imx274_fwnode_parse(struct device * dev)19590abb8f90SEugen Hristev static int imx274_fwnode_parse(struct device *dev)
19600abb8f90SEugen Hristev {
19610abb8f90SEugen Hristev 	struct fwnode_handle *endpoint;
19620abb8f90SEugen Hristev 	/* Only CSI2 is supported */
19630abb8f90SEugen Hristev 	struct v4l2_fwnode_endpoint ep = {
19640abb8f90SEugen Hristev 		.bus_type = V4L2_MBUS_CSI2_DPHY
19650abb8f90SEugen Hristev 	};
19660abb8f90SEugen Hristev 	int ret;
19670abb8f90SEugen Hristev 
19680abb8f90SEugen Hristev 	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
19690abb8f90SEugen Hristev 	if (!endpoint) {
19700abb8f90SEugen Hristev 		dev_err(dev, "Endpoint node not found\n");
19710abb8f90SEugen Hristev 		return -EINVAL;
19720abb8f90SEugen Hristev 	}
19730abb8f90SEugen Hristev 
19740abb8f90SEugen Hristev 	ret = v4l2_fwnode_endpoint_parse(endpoint, &ep);
19750abb8f90SEugen Hristev 	fwnode_handle_put(endpoint);
19760abb8f90SEugen Hristev 	if (ret == -ENXIO) {
19770abb8f90SEugen Hristev 		dev_err(dev, "Unsupported bus type, should be CSI2\n");
19780abb8f90SEugen Hristev 		return ret;
19790abb8f90SEugen Hristev 	} else if (ret) {
19800abb8f90SEugen Hristev 		dev_err(dev, "Parsing endpoint node failed %d\n", ret);
19810abb8f90SEugen Hristev 		return ret;
19820abb8f90SEugen Hristev 	}
19830abb8f90SEugen Hristev 
19840abb8f90SEugen Hristev 	/* Check number of data lanes, only 4 lanes supported */
19850abb8f90SEugen Hristev 	if (ep.bus.mipi_csi2.num_data_lanes != 4) {
19860abb8f90SEugen Hristev 		dev_err(dev, "Invalid data lanes: %d\n",
19870abb8f90SEugen Hristev 			ep.bus.mipi_csi2.num_data_lanes);
19880abb8f90SEugen Hristev 		return -EINVAL;
19890abb8f90SEugen Hristev 	}
19900abb8f90SEugen Hristev 
19910abb8f90SEugen Hristev 	return 0;
19920abb8f90SEugen Hristev }
19930abb8f90SEugen Hristev 
imx274_probe(struct i2c_client * client)1994e6714993SKieran Bingham static int imx274_probe(struct i2c_client *client)
19950985dd30SLeon Luo {
19960985dd30SLeon Luo 	struct v4l2_subdev *sd;
19970985dd30SLeon Luo 	struct stimx274 *imx274;
199857de5bb2SEugen Hristev 	struct device *dev = &client->dev;
19990985dd30SLeon Luo 	int ret;
20000985dd30SLeon Luo 
20010985dd30SLeon Luo 	/* initialize imx274 */
200257de5bb2SEugen Hristev 	imx274 = devm_kzalloc(dev, sizeof(*imx274), GFP_KERNEL);
20030985dd30SLeon Luo 	if (!imx274)
20040985dd30SLeon Luo 		return -ENOMEM;
20050985dd30SLeon Luo 
20060985dd30SLeon Luo 	mutex_init(&imx274->lock);
20070985dd30SLeon Luo 
20080abb8f90SEugen Hristev 	ret = imx274_fwnode_parse(dev);
20090abb8f90SEugen Hristev 	if (ret)
20100abb8f90SEugen Hristev 		return ret;
20110abb8f90SEugen Hristev 
201257de5bb2SEugen Hristev 	imx274->inck = devm_clk_get_optional(dev, "inck");
2013ad97bc37SSowjanya Komatineni 	if (IS_ERR(imx274->inck))
2014ad97bc37SSowjanya Komatineni 		return PTR_ERR(imx274->inck);
2015ad97bc37SSowjanya Komatineni 
201657de5bb2SEugen Hristev 	ret = imx274_regulators_get(dev, imx274);
2017ad97bc37SSowjanya Komatineni 	if (ret) {
201857de5bb2SEugen Hristev 		dev_err(dev, "Failed to get power regulators, err: %d\n", ret);
2019ad97bc37SSowjanya Komatineni 		return ret;
2020ad97bc37SSowjanya Komatineni 	}
2021ad97bc37SSowjanya Komatineni 
2022438ac1fdSLuca Ceresoli 	/* initialize format */
2023e599fc86SEugen Hristev 	imx274->mode = &imx274_modes[0];
202439dd23dcSLuca Ceresoli 	imx274->crop.width = IMX274_MAX_WIDTH;
202539dd23dcSLuca Ceresoli 	imx274->crop.height = IMX274_MAX_HEIGHT;
2026f70ad2acSEugen Hristev 	imx274->format.width = imx274->crop.width / imx274->mode->wbin_ratio;
2027f70ad2acSEugen Hristev 	imx274->format.height = imx274->crop.height / imx274->mode->hbin_ratio;
2028438ac1fdSLuca Ceresoli 	imx274->format.field = V4L2_FIELD_NONE;
2029438ac1fdSLuca Ceresoli 	imx274->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
2030438ac1fdSLuca Ceresoli 	imx274->format.colorspace = V4L2_COLORSPACE_SRGB;
2031438ac1fdSLuca Ceresoli 	imx274->frame_interval.numerator = 1;
2032438ac1fdSLuca Ceresoli 	imx274->frame_interval.denominator = IMX274_DEF_FRAME_RATE;
2033438ac1fdSLuca Ceresoli 
20340985dd30SLeon Luo 	/* initialize regmap */
20350985dd30SLeon Luo 	imx274->regmap = devm_regmap_init_i2c(client, &imx274_regmap_config);
20360985dd30SLeon Luo 	if (IS_ERR(imx274->regmap)) {
203757de5bb2SEugen Hristev 		dev_err(dev,
20380985dd30SLeon Luo 			"regmap init failed: %ld\n", PTR_ERR(imx274->regmap));
20390985dd30SLeon Luo 		ret = -ENODEV;
20400985dd30SLeon Luo 		goto err_regmap;
20410985dd30SLeon Luo 	}
20420985dd30SLeon Luo 
20430985dd30SLeon Luo 	/* initialize subdevice */
20440985dd30SLeon Luo 	imx274->client = client;
20450985dd30SLeon Luo 	sd = &imx274->sd;
20460985dd30SLeon Luo 	v4l2_i2c_subdev_init(sd, client, &imx274_subdev_ops);
20470985dd30SLeon Luo 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
20480985dd30SLeon Luo 
20490985dd30SLeon Luo 	/* initialize subdev media pad */
20500985dd30SLeon Luo 	imx274->pad.flags = MEDIA_PAD_FL_SOURCE;
20510985dd30SLeon Luo 	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
20520985dd30SLeon Luo 	ret = media_entity_pads_init(&sd->entity, 1, &imx274->pad);
20530985dd30SLeon Luo 	if (ret < 0) {
205457de5bb2SEugen Hristev 		dev_err(dev,
20550985dd30SLeon Luo 			"%s : media entity init Failed %d\n", __func__, ret);
20560985dd30SLeon Luo 		goto err_regmap;
20570985dd30SLeon Luo 	}
20580985dd30SLeon Luo 
20590985dd30SLeon Luo 	/* initialize sensor reset gpio */
206057de5bb2SEugen Hristev 	imx274->reset_gpio = devm_gpiod_get_optional(dev, "reset",
20610985dd30SLeon Luo 						     GPIOD_OUT_HIGH);
20620985dd30SLeon Luo 	if (IS_ERR(imx274->reset_gpio)) {
20636cb7d1b3SYang Yingliang 		ret = dev_err_probe(dev, PTR_ERR(imx274->reset_gpio),
20646cb7d1b3SYang Yingliang 				    "Reset GPIO not setup in DT\n");
20650985dd30SLeon Luo 		goto err_me;
20660985dd30SLeon Luo 	}
20670985dd30SLeon Luo 
2068ad97bc37SSowjanya Komatineni 	/* power on the sensor */
206957de5bb2SEugen Hristev 	ret = imx274_power_on(dev);
2070ad97bc37SSowjanya Komatineni 	if (ret < 0) {
207157de5bb2SEugen Hristev 		dev_err(dev, "%s : imx274 power on failed\n", __func__);
2072ad97bc37SSowjanya Komatineni 		goto err_me;
2073ad97bc37SSowjanya Komatineni 	}
20740985dd30SLeon Luo 
20750985dd30SLeon Luo 	/* initialize controls */
207682f5b507SLuca Ceresoli 	ret = v4l2_ctrl_handler_init(&imx274->ctrls.handler, 4);
20770985dd30SLeon Luo 	if (ret < 0) {
207857de5bb2SEugen Hristev 		dev_err(dev, "%s : ctrl handler init Failed\n", __func__);
2079ad97bc37SSowjanya Komatineni 		goto err_power_off;
20800985dd30SLeon Luo 	}
20810985dd30SLeon Luo 
20820985dd30SLeon Luo 	imx274->ctrls.handler.lock = &imx274->lock;
20830985dd30SLeon Luo 
20840985dd30SLeon Luo 	/* add new controls */
20850985dd30SLeon Luo 	imx274->ctrls.test_pattern = v4l2_ctrl_new_std_menu_items(
20860985dd30SLeon Luo 		&imx274->ctrls.handler, &imx274_ctrl_ops,
20870985dd30SLeon Luo 		V4L2_CID_TEST_PATTERN,
20880985dd30SLeon Luo 		ARRAY_SIZE(tp_qmenu) - 1, 0, 0, tp_qmenu);
20890985dd30SLeon Luo 
20900985dd30SLeon Luo 	imx274->ctrls.gain = v4l2_ctrl_new_std(
20910985dd30SLeon Luo 		&imx274->ctrls.handler,
20920985dd30SLeon Luo 		&imx274_ctrl_ops,
20930985dd30SLeon Luo 		V4L2_CID_GAIN, IMX274_MIN_GAIN,
20940985dd30SLeon Luo 		IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN, 1,
20950985dd30SLeon Luo 		IMX274_DEF_GAIN);
20960985dd30SLeon Luo 
20970985dd30SLeon Luo 	imx274->ctrls.exposure = v4l2_ctrl_new_std(
20980985dd30SLeon Luo 		&imx274->ctrls.handler,
20990985dd30SLeon Luo 		&imx274_ctrl_ops,
21000985dd30SLeon Luo 		V4L2_CID_EXPOSURE, IMX274_MIN_EXPOSURE_TIME,
21010985dd30SLeon Luo 		1000000 / IMX274_DEF_FRAME_RATE, 1,
21020985dd30SLeon Luo 		IMX274_MIN_EXPOSURE_TIME);
21030985dd30SLeon Luo 
21040985dd30SLeon Luo 	imx274->ctrls.vflip = v4l2_ctrl_new_std(
21050985dd30SLeon Luo 		&imx274->ctrls.handler,
21060985dd30SLeon Luo 		&imx274_ctrl_ops,
21070985dd30SLeon Luo 		V4L2_CID_VFLIP, 0, 1, 1, 0);
21080985dd30SLeon Luo 
21090985dd30SLeon Luo 	imx274->sd.ctrl_handler = &imx274->ctrls.handler;
21100985dd30SLeon Luo 	if (imx274->ctrls.handler.error) {
21110985dd30SLeon Luo 		ret = imx274->ctrls.handler.error;
21120985dd30SLeon Luo 		goto err_ctrls;
21130985dd30SLeon Luo 	}
21140985dd30SLeon Luo 
21150985dd30SLeon Luo 	/* load default control values */
2116ad97bc37SSowjanya Komatineni 	imx274_load_default(imx274);
21170985dd30SLeon Luo 
21180985dd30SLeon Luo 	/* register subdevice */
21190985dd30SLeon Luo 	ret = v4l2_async_register_subdev(sd);
21200985dd30SLeon Luo 	if (ret < 0) {
212157de5bb2SEugen Hristev 		dev_err(dev, "%s : v4l2_async_register_subdev failed %d\n",
21220985dd30SLeon Luo 			__func__, ret);
21230985dd30SLeon Luo 		goto err_ctrls;
21240985dd30SLeon Luo 	}
21250985dd30SLeon Luo 
212657de5bb2SEugen Hristev 	pm_runtime_set_active(dev);
212757de5bb2SEugen Hristev 	pm_runtime_enable(dev);
212857de5bb2SEugen Hristev 	pm_runtime_idle(dev);
2129ad97bc37SSowjanya Komatineni 
213057de5bb2SEugen Hristev 	dev_info(dev, "imx274 : imx274 probe success !\n");
21310985dd30SLeon Luo 	return 0;
21320985dd30SLeon Luo 
21330985dd30SLeon Luo err_ctrls:
2134781b045bSSakari Ailus 	v4l2_ctrl_handler_free(&imx274->ctrls.handler);
2135ad97bc37SSowjanya Komatineni err_power_off:
213657de5bb2SEugen Hristev 	imx274_power_off(dev);
21370985dd30SLeon Luo err_me:
21380985dd30SLeon Luo 	media_entity_cleanup(&sd->entity);
21390985dd30SLeon Luo err_regmap:
21400985dd30SLeon Luo 	mutex_destroy(&imx274->lock);
21410985dd30SLeon Luo 	return ret;
21420985dd30SLeon Luo }
21430985dd30SLeon Luo 
imx274_remove(struct i2c_client * client)2144ed5c2f5fSUwe Kleine-König static void imx274_remove(struct i2c_client *client)
21450985dd30SLeon Luo {
21460985dd30SLeon Luo 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
21470985dd30SLeon Luo 	struct stimx274 *imx274 = to_imx274(sd);
21480985dd30SLeon Luo 
2149ad97bc37SSowjanya Komatineni 	pm_runtime_disable(&client->dev);
2150ad97bc37SSowjanya Komatineni 	if (!pm_runtime_status_suspended(&client->dev))
2151ad97bc37SSowjanya Komatineni 		imx274_power_off(&client->dev);
2152ad97bc37SSowjanya Komatineni 	pm_runtime_set_suspended(&client->dev);
2153ad97bc37SSowjanya Komatineni 
21540985dd30SLeon Luo 	v4l2_async_unregister_subdev(sd);
2155781b045bSSakari Ailus 	v4l2_ctrl_handler_free(&imx274->ctrls.handler);
2156ad97bc37SSowjanya Komatineni 
21570985dd30SLeon Luo 	media_entity_cleanup(&sd->entity);
21580985dd30SLeon Luo 	mutex_destroy(&imx274->lock);
21590985dd30SLeon Luo }
21600985dd30SLeon Luo 
2161ad97bc37SSowjanya Komatineni static const struct dev_pm_ops imx274_pm_ops = {
2162ad97bc37SSowjanya Komatineni 	SET_RUNTIME_PM_OPS(imx274_power_off, imx274_power_on, NULL)
2163ad97bc37SSowjanya Komatineni };
2164ad97bc37SSowjanya Komatineni 
21650985dd30SLeon Luo static struct i2c_driver imx274_i2c_driver = {
21660985dd30SLeon Luo 	.driver = {
21670985dd30SLeon Luo 		.name	= DRIVER_NAME,
2168ad97bc37SSowjanya Komatineni 		.pm = &imx274_pm_ops,
21690985dd30SLeon Luo 		.of_match_table	= imx274_of_id_table,
21700985dd30SLeon Luo 	},
2171*aaeb31c0SUwe Kleine-König 	.probe		= imx274_probe,
21720985dd30SLeon Luo 	.remove		= imx274_remove,
21730985dd30SLeon Luo 	.id_table	= imx274_id,
21740985dd30SLeon Luo };
21750985dd30SLeon Luo 
21760985dd30SLeon Luo module_i2c_driver(imx274_i2c_driver);
21770985dd30SLeon Luo 
21780985dd30SLeon Luo MODULE_AUTHOR("Leon Luo <leonl@leopardimaging.com>");
21790985dd30SLeon Luo MODULE_DESCRIPTION("IMX274 CMOS Image Sensor driver");
21800985dd30SLeon Luo MODULE_LICENSE("GPL v2");
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