| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | arm,gic-v3.yaml | 75 - GIC Distributor interface (GICD)
132 Address property. Base address of an alias of the GICD region containing
249 reg = <0x2f000000 0x10000>, // GICD
277 reg = <0x2c010000 0x10000>, // GICD
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | k3-am65-main.dtsi | 16 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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| H A D | fsl-ls1012a.dtsi | 23 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
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| H A D | hi6220.dtsi | 115 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
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| H A D | armada-37xx.dtsi | 282 reg = <0x1d00000 0x10000>, /* GICD */
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| H A D | fsl-ls1043a.dtsi | 27 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
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| H A D | thunderx-88xx.dtsi | 339 reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
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| H A D | fsl-ls1046a.dtsi | 27 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
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| /openbmc/linux/arch/arm64/boot/dts/intel/ |
| H A D | keembay-soc.dtsi | 57 reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */
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| /openbmc/qemu/include/hw/intc/ |
| H A D | arm_gic.h | 52 * - distributor registers (GICD*)
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| /openbmc/linux/arch/arm64/boot/dts/broadcom/bcmbca/ |
| H A D | bcm6856.dtsi | 87 reg = <0x1000 0x1000>, /* GICD */
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| H A D | bcm6858.dtsi | 105 reg = <0x1000 0x1000>, /* GICD */
|
| /openbmc/linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-ap810-ap0.dtsi | 51 reg = <0x3000000 0x10000>, /* GICD */
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| H A D | ac5-98dx25xx.dtsi | 314 reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
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| /openbmc/qemu/include/hw/arm/ |
| H A D | xlnx-zynqmp.h | 72 * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
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| /openbmc/linux/arch/arm64/boot/dts/cavium/ |
| H A D | thunder2-99xx.dtsi | 66 reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
|
| /openbmc/linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am62p-main.dtsi | 23 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | acpi.h | 65 #define CPUIDLE_GICD_CTXT BIT(3) /* GICD */
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| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3.c | 65 * + the GICD enable bit for its group is set in gicd_int_pending()
110 * + the GICD enable bit for its group is set in gicr_int_pending()
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| /openbmc/linux/arch/arm64/boot/dts/qcom/ |
| H A D | ipq5018.dtsi | 160 reg = <0x0b000000 0x1000>, /* GICD */
|
| /openbmc/linux/arch/arm64/boot/dts/nuvoton/ |
| H A D | ma35d1.dtsi | 55 reg = <0x0 0x50801000 0 0x1000>, /* GICD */
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-gic-v3.c | 1252 pr_crit_once("RSS is required but GICD doesn't support it\n"); in gic_cpu_sys_reg_init()
1839 /* Setup GICD alias regions */ in gic_enable_quirk_nvidia_t241()
2231 gicv_idx += 3; /* Also skip GICD, GICC, GICH */ in gic_of_setup_kvm_info()
2275 dist_base = gic_of_iomap(node, 0, "GICD", &res); in gic_of_init()
2602 pr_err("Unable to map GICD registers\n"); in gic_acpi_init()
2605 gic_request_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD"); in gic_acpi_init()
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt6779.dtsi | 125 reg = <0 0x0c000000 0 0x40000>, /* GICD */
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| /openbmc/linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hip05.dtsi | 246 reg = <0x0 0x8d000000 0 0x10000>, /* GICD */
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| /openbmc/linux/arch/arm64/boot/dts/arm/ |
| H A D | fvp-base-revc.dts | 195 reg = <0x0 0x2f000000 0 0x10000>, // GICD
|