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/openbmc/linux/include/linux/spi/
H A Dspi-mem.h77 * @cmd.dtr: whether the command opcode should be sent in DTR mode or not
81 * @addr.dtr: whether the address should be sent in DTR mode or not
89 * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
91 * @data.dtr: whether the data should be sent in DTR mode or not
103 u8 dtr : 1; member
111 u8 dtr : 1; member
119 u8 dtr : 1; member
125 u8 dtr : 1; member
296 * @dtr: Supports DTR operations
300 bool dtr; member
/openbmc/linux/arch/x86/include/asm/
H A Ddesc.h111 #define load_gdt(dtr) native_load_gdt(dtr) argument
112 #define load_idt(dtr) native_load_idt(dtr) argument
116 #define store_gdt(dtr) native_store_gdt(dtr) argument
208 static inline void native_load_gdt(const struct desc_ptr *dtr) in native_load_gdt() argument
210 asm volatile("lgdt %0"::"m" (*dtr)); in native_load_gdt()
213 static __always_inline void native_load_idt(const struct desc_ptr *dtr) in native_load_idt() argument
215 asm volatile("lidt %0"::"m" (*dtr)); in native_load_idt()
218 static inline void native_store_gdt(struct desc_ptr *dtr) in native_store_gdt() argument
220 asm volatile("sgdt %0":"=m" (*dtr)); in native_store_gdt()
223 static inline void store_idt(struct desc_ptr *dtr) in store_idt() argument
[all …]
/openbmc/qemu/target/openrisc/
H A Dmmu.c44 uint32_t dtr = cpu->env.tlb.dtlb[idx].tr; in get_phys_mmu() local
50 if (unlikely((itr ^ dtr) & TARGET_PAGE_MASK)) { in get_phys_mmu()
52 dmr = dtr = 0; in get_phys_mmu()
69 right |= dtr & (super ? SRE : URE) ? PAGE_READ : 0; in get_phys_mmu()
70 right |= dtr & (super ? SWE : UWE) ? PAGE_WRITE : 0; in get_phys_mmu()
73 /* Note that above we validated that itr and dtr match on page. in get_phys_mmu()
77 *phys_addr = ((itr | dtr) & TARGET_PAGE_MASK) | (addr & ~TARGET_PAGE_MASK); in get_phys_mmu()
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-netcom-plus-2xx.dts27 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */
40 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */
60 dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
71 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
H A Dam335x-baltos-ir3220.dts33 …XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
46 …XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
65 dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
76 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
H A Dam335x-baltos-ir5221.dts41 …XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
54 …XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
73 dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
84 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
H A Dam335x-baltos-ir2110.dts27 …XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
44 dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
/openbmc/linux/drivers/rtc/
H A Drtc-isl1208.c237 int dtr = i2c_smbus_read_byte_data(client, ISL1208_REG_DTR); in isl1208_i2c_get_dtr() local
238 if (dtr < 0) in isl1208_i2c_get_dtr()
241 /* dtr encodes adjustments of {-60,-40,-20,0,20,40,60} ppm */ in isl1208_i2c_get_dtr()
242 dtr = ((dtr & 0x3) * 20) * (dtr & (1 << 2) ? -1 : 1); in isl1208_i2c_get_dtr()
244 return dtr + 100; in isl1208_i2c_get_dtr()
301 int sr, dtr, atr, usr; in isl1208_rtc_proc() local
320 dtr = isl1208_i2c_get_dtr(client); in isl1208_rtc_proc()
321 if (dtr >= 0) in isl1208_rtc_proc()
322 seq_printf(seq, "digital_trim\t: %d ppm\n", dtr - 100); in isl1208_rtc_proc()
706 int dtr = isl1208_i2c_get_dtr(to_i2c_client(dev->parent)); in isl1208_sysfs_show_dtrim() local
[all …]
H A Drtc-x1205.c295 unsigned char dtr; in x1205_get_dtrim() local
304 { /* read dtr */ in x1205_get_dtrim()
308 .buf = &dtr in x1205_get_dtrim()
312 /* read dtr register */ in x1205_get_dtrim()
318 dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr); in x1205_get_dtrim()
322 if (dtr & X1205_DTR_DTR0) in x1205_get_dtrim()
325 if (dtr & X1205_DTR_DTR1) in x1205_get_dtrim()
328 if (dtr & X1205_DTR_DTR2) in x1205_get_dtrim()
/openbmc/linux/arch/m68k/include/asm/
H A Dnettel.h31 * NETtel/5307 based hardware first. DTR/DCD lines are wired to
48 * PPIO bits used for DTR/DCD.
77 * NETtel/5272 based hardware. DTR/DCD lines are wired to GPB lines.
82 #define MCFPP_DTR1 0x0000 /* Port 1 no DTR support */
87 * PPIO bits used for DTR/DCD.
/openbmc/linux/drivers/usb/serial/
H A Dbelkin_sa.c309 /* reassert DTR and (maybe) RTS on transition from B0 */ in belkin_sa_set_termios()
313 dev_err(&port->dev, "Set DTR error\n"); in belkin_sa_set_termios()
340 /* Drop RTS and DTR */ in belkin_sa_set_termios()
343 dev_err(&port->dev, "DTR LOW error\n"); in belkin_sa_set_termios()
441 int dtr = 0; in belkin_sa_tiocmset() local
452 dtr = 1; in belkin_sa_tiocmset()
460 dtr = 0; in belkin_sa_tiocmset()
472 retval = BSA_USB_CMD(BELKIN_SA_SET_DTR_REQUEST, dtr); in belkin_sa_tiocmset()
474 dev_err(&port->dev, "Set DTR error %d\n", retval); in belkin_sa_tiocmset()
H A Dkobil_sct.c258 /* FIXME: Add rts/dtr methods */ in kobil_close()
424 int dtr = 0; in kobil_tiocmset() local
438 dtr = 1; in kobil_tiocmset()
442 dtr = 0; in kobil_tiocmset()
445 if (dtr != 0) in kobil_tiocmset()
446 dev_dbg(dev, "%s - Setting DTR\n", __func__); in kobil_tiocmset()
448 dev_dbg(dev, "%s - Clearing DTR\n", __func__); in kobil_tiocmset()
453 ((dtr != 0) ? SUSBCR_SSL_SETDTR : SUSBCR_SSL_CLRDTR), in kobil_tiocmset()
H A Dftdi_sio.h92 * Clear DTR
230 * Also - you can not set DTR and RTS with one control message
242 * B0 DTR state
249 * B8 DTR state enable
251 * 1 = use DTR state
277 * B1 Output handshaking using DTR/DSR
H A Dupd78f0730.c18 * - signals: DTR, RTS and BREAK
42 * state of control signals (DTR, RTS and BREAK).
218 dev_dbg(dev, "%s - set DTR\n", __func__); in upd78f0730_tiocmset()
226 dev_dbg(dev, "%s - clear DTR\n", __func__); in upd78f0730_tiocmset()
H A Dmct_u232.h112 #define MCT_U232_MCR_NONE 0x8 /* Deactivate DTR and RTS */
114 #define MCT_U232_MCR_DTR 0x9 /* Activate DTR */
243 * modem control inputs. CTS is connected to RTS, DTR is connected to
253 * Bit 0: Data Terminal Ready (DTR). When set to "1", the output of the UART
254 * -DTR line is Low (Active).
366 * apart from DTR/RTS settings. Both signals are dropped for no flow control
/openbmc/linux/drivers/tty/hvc/
H A Dhvsi_lib.c287 int hvsilib_write_mctrl(struct hvsi_priv *pv, int dtr) in hvsilib_write_mctrl() argument
293 if (dtr) in hvsilib_write_mctrl()
301 pr_devel("HVSI@%x: %s DTR...\n", pv->termno, in hvsilib_write_mctrl()
302 dtr ? "Setting" : "Clearing"); in hvsilib_write_mctrl()
308 ctrl.word = cpu_to_be32(dtr ? HVSI_TSDTR : 0); in hvsilib_write_mctrl()
363 /* Set our own DTR */ in hvsilib_establish()
401 /* Clear our own DTR */ in hvsilib_close()
/openbmc/linux/drivers/spi/
H A Dspi-cadence-quadspi.c381 if (op->cmd.dtr) in cqspi_calc_dummy()
481 if (op->cmd.dtr) { in cqspi_enable_dtr()
524 if (op->cmd.dtr) in cqspi_command_read()
609 if (op->cmd.dtr) in cqspi_command_write()
665 if (op->cmd.dtr) in cqspi_read_setup()
967 if (op->cmd.dtr) in cqspi_write_setup()
984 * command in DTR mode. in cqspi_write_setup()
1271 * address (all 0s) with the read status register command in DTR mode. in cqspi_write()
1273 * the flash when it is polling the write completion register in DTR in cqspi_write()
1274 * mode. So, we can not use direct mode when in DTR mode for writing in cqspi_write()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dintel,ixp4xx-hss.yaml98 dtr-gpios:
100 description: Data Terminal Ready (DTR) GPIO line
120 - dtr-gpios
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dcirrus,clps711x-uart.txt11 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dsecureedge5410.h30 * D7 - DTR on ttySC1
32 * D9 - ttySC0 DTR (7100)
/openbmc/linux/drivers/tty/
H A Dtty_port.c358 * functioning). It lowers DTR/RTS (if @tty has HUPCL set) and invokes
370 * Drop DTR/RTS if HUPCL is set. This causes any attached in tty_port_shutdown()
454 * tty_port_raise_dtr_rts - Raise DTR/RTS
457 * Wrapper for the DTR/RTS raise logic. For the moment this is used to hide
469 * tty_port_lower_dtr_rts - Lower DTR/RTS
472 * Wrapper for the DTR/RTS raise logic. For the moment this is used to hide
494 * - rts/dtr/dcd
500 * software management of these lines. Note that the dtr/rts raise is done each
753 * DTR/CTS and waits for carrier).
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-eckelmann-ci4x10.dts240 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */
252 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */
334 dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
345 dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
/openbmc/linux/arch/x86/boot/compressed/
H A Didt_64.c25 static void load_boot_idt(const struct desc_ptr *dtr) in load_boot_idt() argument
27 asm volatile("lidt %0"::"m" (*dtr)); in load_boot_idt()
/openbmc/linux/drivers/net/hamradio/
H A Dz8530.h98 #define DTR 0x80 /* DTR */ macro
152 #define DTRREQ 4 /* DTR/Request function */
231 #define FASTDTR 0x10 /* Fast DTR/REQ Mode */
/openbmc/linux/drivers/tty/serial/
H A Dsunzilog.h126 #define DTR 0x80 /* DTR */ macro
137 #define nDTRnREQ 0x10 /* /DTR/REQ timing */
190 #define DTRREQ 4 /* DTR/Request function */

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