13c0f0f9fSAlexander Shiyan* Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
23c0f0f9fSAlexander Shiyan
33c0f0f9fSAlexander ShiyanRequired properties:
4d305345cSAlexander Shiyan- compatible: Should be "cirrus,ep7209-uart".
53c0f0f9fSAlexander Shiyan- reg: Address and length of the register set for the device.
63c0f0f9fSAlexander Shiyan- interrupts: Should contain UART TX and RX interrupt.
73c0f0f9fSAlexander Shiyan- clocks: Should contain UART core clock number.
83c0f0f9fSAlexander Shiyan- syscon: Phandle to SYSCON node, which contain UART control bits.
93c0f0f9fSAlexander Shiyan
103c0f0f9fSAlexander ShiyanOptional properties:
1162b0a1b3SAlexander Shiyan- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
1262b0a1b3SAlexander Shiyan  line respectively.
133c0f0f9fSAlexander Shiyan
143c0f0f9fSAlexander ShiyanNote: Each UART port should have an alias correctly numbered
153c0f0f9fSAlexander Shiyanin "aliases" node.
163c0f0f9fSAlexander Shiyan
173c0f0f9fSAlexander ShiyanExample:
183c0f0f9fSAlexander Shiyan	aliases {
193c0f0f9fSAlexander Shiyan		serial0 = &uart1;
203c0f0f9fSAlexander Shiyan	};
213c0f0f9fSAlexander Shiyan
223c0f0f9fSAlexander Shiyan	uart1: uart@80000480 {
23d305345cSAlexander Shiyan		compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart";
243c0f0f9fSAlexander Shiyan		reg = <0x80000480 0x80>;
253c0f0f9fSAlexander Shiyan		interrupts = <12 13>;
263c0f0f9fSAlexander Shiyan		clocks = <&clks 11>;
273c0f0f9fSAlexander Shiyan		syscon = <&syscon1>;
2862b0a1b3SAlexander Shiyan		cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>;
2962b0a1b3SAlexander Shiyan		dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>;
3062b0a1b3SAlexander Shiyan		dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>;
313c0f0f9fSAlexander Shiyan	};
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