Home
last modified time | relevance | path

Searched full:disp_cc_mdss_byte1_clk_src (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/drivers/clk/qcom/
H A Ddispcc-sdm845.c124 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { variable
130 .name = "disp_cc_mdss_byte1_clk_src",
431 &disp_cc_mdss_byte1_clk_src.clkr.hw,
449 &disp_cc_mdss_byte1_clk_src.clkr.hw,
780 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
H A Ddispcc-sm8250.c245 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { variable
251 .name = "disp_cc_mdss_byte1_clk_src",
661 &disp_cc_mdss_byte1_clk_src.clkr.hw,
761 &disp_cc_mdss_byte1_clk_src.clkr.hw,
1168 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1302 &disp_cc_mdss_byte1_clk_src, in disp_cc_sm8250_probe()
H A Ddispcc-sm8550.c318 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { variable
325 .name = "disp_cc_mdss_byte1_clk_src",
713 &disp_cc_mdss_byte1_clk_src.clkr.hw,
879 &disp_cc_mdss_byte1_clk_src.clkr.hw,
1636 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
H A Ddispcc-sm8450.c282 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { variable
289 .name = "disp_cc_mdss_byte1_clk_src",
700 &disp_cc_mdss_byte1_clk_src.clkr.hw,
848 &disp_cc_mdss_byte1_clk_src.clkr.hw,
1640 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
H A Ddispcc-sc8280xp.c2891 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp0_cc_mdss_byte1_clk_src.clkr,
2973 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp1_cc_mdss_byte1_clk_src.clkr,
/openbmc/linux/include/dt-bindings/clock/
H A Dqcom,dispcc-sdm845.h16 #define DISP_CC_MDSS_BYTE1_CLK_SRC 6 macro
H A Dqcom,dispcc-sm8150.h17 #define DISP_CC_MDSS_BYTE1_CLK_SRC 7 macro
H A Dqcom,dispcc-sm8250.h17 #define DISP_CC_MDSS_BYTE1_CLK_SRC 7 macro
H A Dqcom,dispcc-sm8350.h17 #define DISP_CC_MDSS_BYTE1_CLK_SRC 7 macro
H A Dqcom,sm8450-dispcc.h18 #define DISP_CC_MDSS_BYTE1_CLK_SRC 8 macro
H A Dqcom,dispcc-sc8280xp.h22 #define DISP_CC_MDSS_BYTE1_CLK_SRC 12 macro
H A Dqcom,sm8550-dispcc.h19 #define DISP_CC_MDSS_BYTE1_CLK_SRC 9 macro
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sdm845-mdss.yaml230 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dqcom,sm8550-mdss.yaml292 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dqcom,sm8250-mdss.yaml284 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dqcom,sm8150-mdss.yaml282 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dqcom,sm8450-mdss.yaml303 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm8350.dtsi2977 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dsm8150.dtsi3887 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dsm8550.dtsi2869 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
H A Dsm8450.dtsi3034 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
H A Dsdm845.dtsi4695 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
H A Dsm8250.dtsi4505 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;