| /openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/ |
| H A D | spl.c | 22 u32 clkenb, ddrpll; in ddr_clock_init() local
32 ddrpll = readl(&misc_p->pll_ctr_reg); in ddr_clock_init()
33 ddrpll &= ~MEM_CLK_SEL_MSK; in ddr_clock_init()
35 ddrpll |= MEM_CLK_HCLK; in ddr_clock_init()
37 ddrpll |= MEM_CLK_2HCLK; in ddr_clock_init()
39 ddrpll |= MEM_CLK_PLL2; in ddr_clock_init()
43 writel(ddrpll, &misc_p->pll_ctr_reg); in ddr_clock_init()
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | calxeda.yaml | 59 ddrpll: ddrpll@108 {
|
| H A D | zynq-7000.txt | 42 1: ddrpll
96 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
|
| H A D | nuvoton,ma35d1-clk.yaml | 36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
|
| H A D | keystone-pll.txt | 4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
|
| /openbmc/linux/drivers/clk/zynq/ |
| H A D | clkc.c | 51 armpll, ddrpll, iopll, enumerator
240 cpu_parents[2] = clk_output_name[ddrpll]; in zynq_clk_setup()
245 periph_parents[3] = clk_output_name[ddrpll]; in zynq_clk_setup()
266 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], in zynq_clk_setup()
325 clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, in zynq_clk_setup()
331 clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, in zynq_clk_setup()
338 clk_register_divider(NULL, "dci_div0", "ddrpll", 0, in zynq_clk_setup()
|
| /openbmc/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 261 u32 ctrl, cpu, cpupll, ddr, ddrpll; in ar934x_update_clock() local
273 ddrpll = ar934x_ddrpll_to_hz(ddr); in ar934x_update_clock()
280 cpuclk = ddrpll; in ar934x_update_clock()
285 ddrclk = ddrpll; in ar934x_update_clock()
292 busclk = ddrpll; in ar934x_update_clock()
|
| /openbmc/linux/drivers/clk/nuvoton/ |
| H A D | clk-ma35d1-pll.c | 235 case DDRPLL: in ma35d1_clk_pll_recalc_rate()
267 case DDRPLL: in ma35d1_clk_pll_round_rate()
347 if (id == CAPLL || id == DDRPLL) in ma35d1_reg_clk_pll()
|
| H A D | clk-ma35d1.c | 68 { .fw_name = "ddrpll", },
344 { .fw_name = "ddrpll", },
504 hws[DDRPLL] = ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", in ma35d1_clocks_probe()
551 hws[DDR0_GATE] = ma35d1_clk_gate(dev, "ddr0_gate", "ddrpll", in ma35d1_clocks_probe()
553 hws[DDR6_GATE] = ma35d1_clk_gate(dev, "ddr6_gate", "ddrpll", in ma35d1_clocks_probe()
897 hws[DDR_GATE] = ma35d1_clk_gate(dev, "ddr_gate", "ddrpll", in ma35d1_clocks_probe()
|
| /openbmc/linux/arch/arm/boot/dts/calxeda/ |
| H A D | ecx-common.dtsi | 145 ddrpll: ddrpll { label
|
| /openbmc/linux/drivers/gpu/drm/i915/soc/ |
| H A D | intel_dram.c | 86 u16 ddrpll, csipll; in ilk_detect_mem_freq() local
88 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); in ilk_detect_mem_freq()
89 switch (ddrpll & 0xff) { in ilk_detect_mem_freq()
104 ddrpll & 0xff); in ilk_detect_mem_freq()
|
| /openbmc/linux/arch/arm64/boot/dts/nuvoton/ |
| H A D | ma35d1-iot-512m.dts | 42 <&clk DDRPLL>,
|
| H A D | ma35d1-som-256m.dts | 42 <&clk DDRPLL>,
|
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | zynq-cse-nand.dts | 52 clock-output-names = "armpll", "ddrpll",
|
| H A D | zynq-cse-nor.dts | 59 clock-output-names = "armpll", "ddrpll",
|
| H A D | zynq-cse-qspi.dtsi | 105 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
|
| H A D | zynq-7000.dtsi | 270 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
|
| /openbmc/linux/drivers/clk/sifive/ |
| H A D | fu540-prci.h | 76 .name = "ddrpll",
|
| H A D | fu740-prci.h | 92 .name = "ddrpll",
|
| /openbmc/u-boot/arch/arm/mach-zynq/ |
| H A D | clk.c | 14 "armpll", "ddrpll", "iopll",
|
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | nuvoton,ma35d1-clk.h | 21 #define DDRPLL 10 macro
|
| /openbmc/u-boot/drivers/clk/sifive/ |
| H A D | fu540-prci.c | 511 .name = "ddrpll",
|
| /openbmc/linux/arch/arm/boot/dts/xilinx/ |
| H A D | zynq-7000.dtsi | 320 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
|