| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | sdhci-st.txt | 57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
109 sd-uhs-ddr50;
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| H A D | sdhci-am654.yaml | 103 ti,otap-del-sel-ddr50:
104 description: Output tap delay for SD UHS DDR50 timing
161 ti,itap-del-sel-ddr50:
162 description: Input tap delay for MMC DDR50 timing
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| H A D | sdhci-omap.txt | 19 "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
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| H A D | cdns,sdhci.yaml | 69 cdns,phy-input-delay-sd-uhs-ddr50:
70 description: Value of the delay in the input path for SD UHS DDR50 timing
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| H A D | mmc-controller.yaml | 160 sd-uhs-ddr50:
163 SD UHS DDR50 speed is supported.
348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
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| H A D | brcm,sdhci-brcmstb.yaml | 94 sd-uhs-ddr50;
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| H A D | samsung,exynos-dw-mshc.yaml | 159 sd-uhs-ddr50;
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| /openbmc/u-boot/doc/device-tree-bindings/misc/ |
| H A D | intel,baytrail-fsp.txt | 38 - fsp,emmc45-ddr50-enabled
131 fsp,emmc45-ddr50-enabled;
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | stih410-b2120.dts | 41 sd-uhs-ddr50;
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| H A D | stih418-b2199.dts | 94 sd-uhs-ddr50;
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | am572x-idk.dts | 23 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | am57xx-beagle-x15-revc.dts | 22 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | am57xx-beagle-x15-revb1.dts | 22 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | am57xx-beagle-x15.dts | 30 /delete-property/ sd-uhs-ddr50;
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| H A D | dra72-evm.dts | 59 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | am571x-idk.dts | 104 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | dra72-evm-revc.dts | 100 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | dra7-evm.dts | 338 …pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50"…
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| /openbmc/u-boot/board/rockchip/evb_rk3328/ |
| H A D | README | 8 * eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | dra72-evm.dts | 94 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | dra72x-mmc-iodelay.dtsi | 17 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
90 mmc1_pins_ddr50_rev10: mmc1-ddr50-rev10-pins {
101 mmc1_pins_ddr50_rev20: mmc1-ddr50-rev20-pins {
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| H A D | dra72-evm-revc.dts | 124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | dra76x-mmc-iodelay.dtsi | 15 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
63 mmc1_pins_ddr50: mmc1-ddr50-pins {
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | dw_mmc-k3.c | 84 {0}, /* 7: DDR50 */
96 {0}, /* 7: DDR50 */
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| /openbmc/u-boot/board/rockchip/evb_rk3399/ |
| H A D | README | 10 * eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
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