| /openbmc/u-boot/drivers/ram/aspeed/ |
| H A D | Kconfig | 5 prompt "DDR4 target data rate"
9 bool "DDR4 targets at 400Mbps"
12 select DDR4 target data rate at 400M
15 bool "DDR4 targets at 800Mbps"
18 select DDR4 target data rate at 800M
21 bool "DDR4 targets at 1333Mbps"
24 select DDR4 target data rate at 1333M
27 bool "DDR4 targets at 1600Mbps"
30 select DDR4 target data rate at 1600M
34 bool "dual X8 DDR4 die"
[all …]
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| /openbmc/openpower-vpd-parser/vpd-parser/ |
| H A D | isdimm_vpd_parser.cpp | 72 // NOTE: This calculation is Only for DDR4 in getDDR4DimmCapacity()
169 // This is applicable only for DDR4 specification in getDDR4FruNumber()
170 // 10 - DDR4-1600 in getDDR4FruNumber()
171 // 9 - DDR4-1866 in getDDR4FruNumber()
172 // 8 - DDR4-2133 in getDDR4FruNumber()
173 // 7 - DDR4-2400 in getDDR4FruNumber()
174 // 6 - DDR4-2666 in getDDR4FruNumber()
175 // 5 - DDR4-3200 in getDDR4FruNumber()
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
66 - 1 64-bit DDR4 SDRAM memory controller with ECC
93 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
94 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
178 - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
220 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
221 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
289 Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC.
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| /openbmc/u-boot/drivers/ddr/imx/imx8m/ |
| H A D | Kconfig | 11 bool "imx8m ddr4"
14 Select the i.MX8M DDR4 driver support on i.MX8M SOC.
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| /openbmc/u-boot/arch/arm/mach-aspeed/ast2500/ |
| H A D | platform.S | 16 * AST25x0 DDR3/DDR4 SDRAM controller initialization sequence
41 * V3 |2015.05.13 : 1.[P1] Modify DDR4 PHY Vref training algorithm
53 * | 4.[P2] Add DDR4 Vref trainig retry timeout
63 * |2016.07.12 : 2.[P1] Modify DDR4 read path ODT from 60 ohm to 48 ohm, at address 0x1e6e0204
64 …* | : 3.[P1] Modify DDR4 Ron calibration to manual mode to fix Vix issue, set Ron_pu …
65 …* | : 4.[P2] Modify read timing margin report policy, change DDR4 min value from 0.35…
70 * |2016.11.07 : 2.[P3] Add log information of DDR4 PHY Vref training
73 * V16|2017.06.15 : 1.[P1] Add margin check/retry for DDR4 Vref training margin.
74 * |2017.06.15 : 2.[P1] Add margin check/retry for DDR3/DDR4 read timing training margin.
78 * V17|2017.09.25 : 1.[P1] Modify DDR4 side ODT value from 60ohm to 48ohm.
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mm-ddr4-evk.dts | 11 model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board";
12 compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm";
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| H A D | imx8mn-ddr4-evk.dts | 12 model = "NXP i.MX8MNano DDR4 EVK board";
13 compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
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| /openbmc/bmcweb/redfish-core/include/generated/enums/ |
| H A D | processor.hpp | 46 DDR4, enumerator
132 {ProcessorMemoryType::DDR4, "DDR4"},
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| H A D | memory.hpp | 23 DDR4, enumerator
126 {MemoryDeviceType::DDR4, "DDR4"},
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| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | Kconfig | 104 Enable Freescale DDR4 controller.
126 bool "Freescale DDR4 controller"
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| H A D | ddr4_dimm_params.c | 122 * ddr_compute_dimm_parameters for DDR4 SPD
145 printf("Ctrl %u DIMM %u: is not a DDR4 SPD.\n", in ddr_compute_dimm_parameters()
262 * but DDR4 spec has nature BL8 and BC4, in ddr_compute_dimm_parameters()
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| /openbmc/u-boot/board/freescale/t102xqds/ |
| H A D | README | 24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
88 - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
90 - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
124 - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
215 or make T1024QDS_D4_defconfig (For DDR4)
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| /openbmc/linux/drivers/misc/eeprom/ |
| H A D | Kconfig | 124 tristate "SPD EEPROMs on DDR4 memory modules"
128 the JEDEC EE1004 standard. These are typically found on DDR4
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| H A D | ee1004.c | 3 * ee1004 - driver for DDR4 SPD EEPROMs
22 * DDR4 memory modules use special EEPROMs following the Jedec EE1004
286 MODULE_DESCRIPTION("Driver for EE1004-compliant DDR4 SPD EEPROMs");
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| /openbmc/u-boot/board/freescale/ls1088a/ |
| H A D | README | 48 - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
114 - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
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| /openbmc/linux/include/linux/ |
| H A D | edac.h | 179 * @MEM_DDR4: Unbuffered DDR4 RAM
180 * @MEM_RDDR4: Registered DDR4 RAM
181 * This is a variant of the DDR4 memories.
182 * @MEM_LRDDR4: Load-Reduced DDR4 memory.
183 * @MEM_LPDDR4: Low-Power DDR4 memory.
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| /openbmc/u-boot/board/freescale/ls2080ardb/ |
| H A D | README | 23 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
25 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
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| /openbmc/linux/Documentation/devicetree/bindings/edac/ |
| H A D | aspeed-sdram-edac.txt | 3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
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| /openbmc/u-boot/include/ |
| H A D | fsl_ddr_sdram.h | 190 #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
191 #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
367 unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nuvoton,npcm-memory-controller.yaml | 14 The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
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| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_common.c | 23 * Serial Presence Detect (SPD) for DDR4 SDRAM Modules
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| /openbmc/openpower-vpd-parser/ |
| H A D | const.hpp | 214 DDR4_DDIMM_MEMORY_VPD, /**< DDR4 DDIMM Memory VPD type */
216 DDR4_ISDIMM_MEMORY_VPD, /**< DDR4 ISDIMM Memory VPD type */
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| /openbmc/u-boot/board/freescale/t102xrdb/ |
| H A D | ddr.c | 149 /* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
205 const char dimm_model[] = "Fixed DDR4 on board"; in fsl_ddr_get_dimm_params()
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| /openbmc/u-boot/board/freescale/ls2080aqds/ |
| H A D | README | 24 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
26 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
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| /openbmc/u-boot/board/freescale/ls1043ardb/ |
| H A D | README | 22 - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
|