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/openbmc/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A D	other.json	9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol… 12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old… 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A D	pipeline.json	9 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt… 12 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt… 15 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt… 18 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt… 21 …tion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empt… 24 …tion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empt… 27 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal… 30 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal… 33 …eration issued due to the backend, interlock, AGU.This event counts every cycle that issue is stal… 36 …eration issued due to the backend, interlock, AGU.This event counts every cycle that issue is stal… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A D	pipeline.json	21 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc… 24 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc… 27 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr… 30 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr… 39 …No operation issued due to the backend interlock. This event counts every cycle where the issue of… 42 …No operation issued due to the backend interlock. This event counts every cycle where the issue of… 45 …ion issued due to the backend, address interlock. This event counts every cycle where the issue of… 48 …ion issued due to the backend, address interlock. This event counts every cycle where the issue of… 51 …, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a s… 54 …, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a s… [all …]
/openbmc/linux/include/linux/
H A D	timecounter.h	19 * Depending on which hardware it reads, the cycle counter may wrap 23 * @read: returns the current cycle value 27 * @mult: cycle to nanosecond multiplier 28 * @shift: cycle to nanosecond divisor (power of two) 40 * cycle counter wrap around. Initialize with 41 * timecounter_init(). Also used to convert cycle counts into the 44 * cycle counter hardware, locking issues and reading the time 45 * more often than the cycle counter wraps around. The nanosecond 48 * @cc: the cycle counter used by this instance 49 * @cycle_last: most recent cycle counter value seen by [all …]
/openbmc/linux/drivers/staging/vme_user/
H A D	vme_fake.c	49 u32 cycle; member 57 u32 cycle; member 156 dma_addr_t buf_base, u32 aspace, u32 cycle) in fake_slave_set() argument 213 bridge->slaves[i].cycle = cycle; in fake_slave_set() 225 dma_addr_t buf_base, u32 aspace, u32 cycle) in fake_slave_get() argument 241 cycle = bridge->slaves[i].cycle; in fake_slave_get() 253 u32 aspace, u32 cycle, u32 dwidth) in fake_master_set() argument 321 bridge->masters[i].cycle = cycle; in fake_master_set() 339 u32 aspace, u32 cycle, u32 dwidth) in __fake_master_get() argument 352 cycle = bridge->masters[i].cycle; in __fake_master_get() [all …]
H A D	vme_tsi148.c	468 dma_addr_t pci_base, u32 aspace, u32 cycle) in tsi148_slave_set() argument 554 switch (cycle & (VME_2eSST160 \| VME_2eSST267 \| VME_2eSST320)) { in tsi148_slave_set() 566 /* Setup cycle types */ in tsi148_slave_set() 568 if (cycle & VME_BLT) in tsi148_slave_set() 570 if (cycle & VME_MBLT) in tsi148_slave_set() 572 if (cycle & VME_2eVME) in tsi148_slave_set() 574 if (cycle & VME_2eSST) in tsi148_slave_set() 576 if (cycle & VME_2eSSTB) in tsi148_slave_set() 584 if (cycle & VME_SUPER) in tsi148_slave_set() 586 if (cycle & VME_USER) in tsi148_slave_set() [all …]
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/State/Boot/
H A D	PostCode.interface.yaml	2 Monitor Post code coming and buffer all of them based on boot cycle into 20 Method to get the cached post codes of the indicated boot cycle with 26 Index indicates which boot cycle of post codes is requested. 1 27 is for the most recent boot cycle. CurrentBootCycleCount is for 28 the oldest boot cycle. 36 Method to get the cached post codes of the indicated boot cycle. 41 Index indicates which boot cycle of post codes is requested. 1 42 is for the most recent boot cycle. CurrentBootCycleCount is for 43 the oldest boot cycle. 48 An array of post codes of one boot cycle.
/openbmc/openbmc-test-automation/extended/
H A D	test_bmc_reset_loop.robot	2 Documentation Power cycle loop. This is to test where network service 3 ... becomes unavailable during AC-Cycle stress test. 22 ${ERROR_REGEX} SEGV\|core-dump\|FAILURE\|Failed to start\|Found ordering cycle 26 Run Multiple Power Cycle 34 Repeat Keyword ${LOOP_COUNT} times Power Cycle System Via PDU 44 Repeat Keyword ${LOOP_COUNT} times BMC Redfish Reset Cycle 54 Repeat Keyword ${LOOP_COUNT} times BMC Reboot Cycle 64 Repeat Keyword ${LOOP_COUNT} times BMC Redfish Reset Runtime Cycle 68 Power Cycle System Via PDU 69 [Documentation] Power cycle system and wait for BMC to reach Ready state. [all …]
/openbmc/openbmc/meta-facebook/meta-minerva/recipes-phosphor/state/phosphor-state-manager/
H A D	chassis-powercycle	`6 # Minerva CMM Sled Power Cycle and Chassis Power Cycle 8 cmm-hsc-power-cycle() { 69 # CMM Sled Power Cycle 72 echo "Staring CMM Sled Power Cycle" 73 cmm-hsc-power-cycle 74 # CMM Chassis Power Cycle 77 echo "Staring CMM Chassis Power Cycle" 82 cmm-hsc-power-cycle 84 echo "Invalid CMM Cycle"`
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	floating-point.json	6 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 13 …X, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. Th… 20 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 27 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 34 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 40 …ent. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to… 46 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov… 52 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov… 58 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov… 64 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov…
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/state/phosphor-state-manager/
H A D	chassis-powercycle	`6 #Sled cycle 7 echo "Starting Chassis Power Cycle" 9 chassis-power-cycle() { 37 aegis-power-cycle() { 47 echo "Starting Chassis Power Cycle" 48 chassis-power-cycle 50 echo "Starting Aegis Power Cycle" 51 aegis-power-cycle`
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A D	floating-point.json	6 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 13 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 20 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 27 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 34 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 41 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 48 …X, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. Th… 55 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 62 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… 69 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th… [all …]
/openbmc/linux/scripts/
H A D	headerdep.pl	`114 # $cycle[n] includes $cycle[n + 1]; 115 # $cycle[-1] will be the culprit 116 my $cycle = shift; 119 for my $i (0 .. $#$cycle - 1) { 120 $cycle->[$i]->[0] = $cycle->[$i + 1]->[0]; 122 $cycle->[-1]->[0] = 0; 124 my $first = shift @$cycle; 125 my $last = pop @$cycle; 130 for my $header (reverse @$cycle) { 141 # Find and print the smallest cycle starting in the specified node. [all …]`
/openbmc/linux/drivers/ata/
H A D	libata-pata-timings.c	70 q->cycle = EZ(t->cycle, T); in ata_timing_quantize() 92 m->cycle = max(a->cycle, b->cycle); in ata_timing_merge() 133 * PIO/MW_DMA cycle timing. in ata_timing_compute() 141 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; in ata_timing_compute() 144 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; in ata_timing_compute() 146 p.cycle = id[ATA_ID_EIDE_DMA_MIN]; in ata_timing_compute() 160 * DMA cycle timing is slower/equal than the fastest PIO timing. in ata_timing_compute() 169 * Lengthen active & recovery time so that cycle time is correct. in ata_timing_compute() 177 if (t->active + t->recover < t->cycle) { in ata_timing_compute() 178 t->active += (t->cycle - (t->active + t->recover)) / 2; in ata_timing_compute() [all …]
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/state/phosphor-state-manager/
H A D	chassis-powercycle	`22 echo "Failed to check management board fru info, sled cycle keep default setting" 41 echo "Do 12V cycle disable i3c hub" 84 chassis-power-cycle() 129 # Check chassis status after doing 12V cycle 146 msg="Chassis$CHASSIS_ID cycle success" 153 msg="Chassis$CHASSIS_ID cycle failed, Chassis$CHASSIS_ID is power off" 166 sled-cycle() 179 echo "Starting sled cycle..." 180 if ! sled-cycle 182 echo "Failed to do sled cycle" [all …]`
/openbmc/linux/arch/alpha/lib/
H A D	ev6-csum_ipv6_magic.S	36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence) 116 cmpult $20,$3,$3 # E : (1 cycle stall on $20) 117 addq $20,$18,$20 # E : U L U L (1 cycle stall on $20) 120 addq $20,$19,$20 # E : (1 cycle stall on $20) 125 addq $18,$19,$18 # E : (1 cycle stall on $19) 128 /* (1 cycle stall on $18, 2 cycles on $20) */ 131 zapnot $0,15,$1 # U : Start folding output (1 cycle stall on $0) 133 srl $0,32,$0 # U : U L U L : (1 cycle stall on $0) 136 extwl $1,2,$2 # U : ushort[1] (1 cycle stall on $1) 137 zapnot $1,3,$0 # U : ushort[0] (1 cycle stall on $1) [all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A D	pwm-regulator.yaml	19 duty-cycle values must be provided via DT. Limitations are that the 21 Intermediary duty-cycle values which would normally allow finer grained 29 appropriate duty-cycle values. This allows for a much more fine grained 31 make an assumption that a %50 duty-cycle value will cause the regulator 49 description: Voltage and Duty-Cycle table. 54 - description: duty-cycle in percent (%) 63 Integer value encoding the duty cycle unit. If not 75 Duty cycle values are expressed in pwm-dutycycle-unit. 104 * Inverted PWM logic, and the duty cycle range is limited 119 /* Voltage Duty-Cycle */
/openbmc/openbmc/meta-fii/meta-kudo/recipes-kudo/hotswap-power-cycle/
H A D	hotswap-power-cycle.bb	`1 SUMMARY = "Power Cycle by Hotswap Controller" 2 DESCRIPTION = "Power Cycle by Hotswap Controller Daemon" 13 SRC_URI += " file://hotswap-power-cycle.service" 17 …install -m 0644 ${UNPACKDIR}/hotswap-power-cycle.service ${D}${systemd_unitdir}/system/hotswap-pow… 21 SYSTEMD_SERVICE:${PN} = " hotswap-power-cycle.service"`
/openbmc/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	floating-point.json	44 …tion": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", 47 …ion": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", 52 …tion": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", 55 …ion": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", 60 …tion": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", 68 …tion": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", 71 …ion": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", 76 …"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB… 120 … "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", 128 … "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
/openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	floating-point.json	44 …tion": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", 47 …ion": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", 52 …tion": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", 55 …ion": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", 60 …tion": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", 68 …tion": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", 71 …ion": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", 76 …"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB… 120 … "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", 128 … "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
/openbmc/linux/tools/testing/selftests/tc-testing/tc-tests/actions/
H A D	gate.json	52 "name": "Add gate action with cycle-time", 65 …"cmdUnderTest": "$TC action add action gate cycle-time 200000000000ns sched-entry close 100000000n… 68 "matchPattern": "action order [0-9]: .cycle-time 200s.index 1000 ref", 76 "name": "Add gate action with cycle-time-ext", 89 …"cmdUnderTest": "$TC action add action gate cycle-time-ext 20000000000ns sched-entry close 1000000… 92 "matchPattern": "action order [0-9]: .cycle-time-ext 20s.index 1000 ref", 203 …"$TC action add action gate cycle-time 600000000000ns sched-entry open 600000000ns -1 8000000b ind… 204 … "$TC action add action gate cycle-time-ext 400000000000ns sched-entry close 100000000ns index 103" 230 …"$TC action add action gate cycle-time 600000000000ns sched-entry open 600000000ns -1 8000000b ind… 231 … "$TC action add action gate cycle-time-ext 400000000000ns sched-entry close 100000000ns index 103" [all …]
/openbmc/linux/drivers/pwm/
H A D	pwm-sl28cpld.c	25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0. 30 * - The duty cycle will switch immediately and not after a complete cycle. 60 * We calculate the duty cycle like this: 130 unsigned int cycle, prescaler; in sl28cpld_pwm_apply() local 153 cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle); in sl28cpld_pwm_apply() 154 cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)); in sl28cpld_pwm_apply() 158 * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't in sl28cpld_pwm_apply() 164 if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) { in sl28cpld_pwm_apply() 167 cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1); in sl28cpld_pwm_apply() 172 * we have a valid duty cycle for the new mode. in sl28cpld_pwm_apply() [all …]
/openbmc/linux/Documentation/admin-guide/perf/
H A D	alibaba_pmu.rst	`26 - Group 0: PMU Cycle Counter. This group has one pair of counters 27 pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count 61 -e ali_drw_21000/cycle/ \ 65 -e ali_drw_21080/cycle/ \ 69 -e ali_drw_23000/cycle/ \ 73 -e ali_drw_23080/cycle/ \ 77 -e ali_drw_25000/cycle/ \ 81 -e ali_drw_25080/cycle/ \ 85 -e ali_drw_27000/cycle/ \ 89 -e ali_drw_27080/cycle/ -- sleep 10`
/openbmc/linux/drivers/net/dsa/sja1105/
H A D	sja1105_tas.c	88 dev_dbg(ds->dev, "longest cycle time %lld ns\n", max_cycle_time); in sja1105_tas_set_runtime_params() 101 * iterate cyclically through the "schedule". Each "cycle" has an entry point 103 * hardware calls each cycle a "subschedule". 105 * Subschedule (cycle) i starts when 123 * \|cycle 0\|cycle 1\| 151 * - cycle 0: iterates the schedule table from 0 to 2 (and back) 152 * - cycle 1: iterates the schedule table from 3 to 5 (and back) 174 int cycle = 0; in sja1105_init_scheduling() local 300 schedule_entry_points[cycle].subschindx = cycle; in sja1105_init_scheduling() 301 schedule_entry_points[cycle].delta = entry_point_delta; in sja1105_init_scheduling() [all …]
/openbmc/linux/Documentation/hwmon/
H A D	dme1737.rst	167 cycle) of the input. The chip adjusts the sampling rate based on this value. 178 manual mode, the fan speed is set by writing the duty-cycle value to the 180 current duty-cycle as set by the fan controller in the chip. All PWM outputs 198 pwm[1-3]_auto_point2_pwm full-speed duty-cycle (255, i.e., 100%) 199 pwm[1-3]_auto_point1_pwm low-speed duty-cycle 200 pwm[1-3]_auto_pwm_min min-speed duty-cycle 208 The chip adjusts the output duty-cycle linearly in the range of auto_point1_pwm 211 auto_point1_temp_hyst value, the output duty-cycle is set to the auto_pwm_min 214 duty-cycle. If any of the temperatures rise above the auto_point3_temp value, 215 all PWM outputs are set to 100% duty-cycle. [all …]

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