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/openbmc/openbmc/poky/meta/recipes-devtools/valgrind/valgrind/
H A D0001-makefiles-Drop-setting-mcpu-to-cortex-a8-on-arm-arch.patch4 Subject: [PATCH] makefiles: Drop setting -mcpu to cortex-a8 on arm
7 We can not assume that all arches armv7+ are cortex-a8 only
8 it fails to build for rpi which is armv7ve based (cortex-a8) cpu
11 | cc1: warning: switch -mcpu=cortex-a8 conflicts with -march=armv7ve switch
29 -annotate_hbefore_CFLAGS = $(AM_CFLAGS) -mcpu=cortex-a8
30 -tc07_hbl1_CFLAGS = $(AM_CFLAGS) -mcpu=cortex-a8
31 -tc08_hbl2_CFLAGS = $(AM_CFLAGS) -mcpu=cortex-a8
46 -v6intARM_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -marm
47 -v6intThumb_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
51 -v6media_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
[all …]
H A Duse-appropriate-march-mcpu-mfpu-for-ARM-test-apps.patch12 -march=armv7ve and -mcpu=cortex-a15 (since some TUNE_CCARGS may set
13 -march=armv7-a and adding -mcpu=cortex-a15 alone is not enough to
29 @@ -87,8 +87,10 @@ neon64_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
33 -intdiv_CFLAGS = $(AM_CFLAGS) -g -mcpu=cortex-a15 -mthumb
34 +intdiv_CFLAGS = $(AM_CFLAGS) -g -march=armv7ve -mcpu=cortex-a15 -mthumb
35 ldrt_CFLAGS = $(AM_CFLAGS) -g -mcpu=cortex-a8 -mthumb
36 ldrt_arm_CFLAGS = $(AM_CFLAGS) -g -mcpu=cortex-a8 -marm
38 -vfpv4_fma_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a15 -mfpu=vfpv4 -marm
39 +vcvt_fixed_float_VFP_CFLAGS = $(AM_CFLAGS) -g -mcpu=cortex-a8 -mfpu=vfpv3
41 +vfpv4_fma_CFLAGS = $(AM_CFLAGS) -g -O0 -march=armv7ve -mcpu=cortex-a15 -mfpu=vfpv4 -marm
/openbmc/qemu/docs/system/arm/
H A Draspi.rst10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU
H A Dmps2.rst19 Cortex-M3 as documented in Arm Application Note AN385
21 Cortex-M4 as documented in Arm Application Note AN386
23 Cortex-M7 as documented in Arm Application Note AN500
25 Cortex-M33 as documented in Arm Application Note AN505
27 Cortex-M3 'DesignStart' as documented in Arm Application Note AN511
29 Dual Cortex-M33 as documented in Arm Application Note AN521
31 Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524
33 Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
38 Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
65 of the way the real FPGA image usually runs with the second Cortex-R52
H A Dstm32.rst7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
21 The following machines are based on this ARM Cortex-M4F chip :
32 * ARM Cortex-M3, Cortex M4F
H A Dnuvoton.rst7 NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
8 while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
14 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
19 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
31 The NPCM8xx SoC is the successor of the NPCM7xx SoC. It has 4 Cortex-A35 cores.
39 * SMP (Dual Core Cortex-A9)
40 * Cortex-A9MPCore built-in peripherals: SCU, GIC, Global Timer, Private Timer
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8a/
H A Dtune-cortexa73-cortexa35.inc2 # Tune Settings for big.LITTLE Cortex-A73 - Cortex-A35
6 TUNEVALID[cortexa73-cortexa35] = "Enable big.LITTLE Cortex-A73.Cortex-A35 specific processor optimi…
8 …{@bb.utils.contains("TUNE_FEATURES", "cortexa73-cortexa35", " -mcpu=cortex-a73.cortex-a35", "", d)…
H A Dtune-cortexa57-cortexa53.inc3 TUNEVALID[cortexa57-cortexa53] = "Enable big.LITTLE Cortex-A57.Cortex-A53 specific processor optimi…
4 …{@bb.utils.contains("TUNE_FEATURES", "cortexa57-cortexa53", " -mcpu=cortex-a57.cortex-a53", "", d)…
H A Dtune-cortexa72-cortexa53.inc3 TUNEVALID[cortexa72-cortexa53] = "Enable big.LITTLE Cortex-A72.Cortex-A53 specific processor optimi…
4 …{@bb.utils.contains("TUNE_FEATURES", "cortexa72-cortexa53", " -mcpu=cortex-a72.cortex-a53", "", d)…
H A Dtune-cortexa73-cortexa53.inc3 TUNEVALID[cortexa73-cortexa53] = "Enable big.LITTLE Cortex-A73.Cortex-A53 specific processor optimi…
5 …{@bb.utils.contains("TUNE_FEATURES", "cortexa73-cortexa53", " -mcpu=cortex-a73.cortex-a53", "", d)…
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8-2a/
H A Dtune-cortexa75-cortexa55.inc2 # Tune Settings for big.LITTLE Cortex-A75 - Cortex-A55
6 TUNEVALID[cortexa75-cortexa55] = "Enable big.LITTLE Cortex-A75.Cortex-A55 specific processor optimi…
8 …{@bb.utils.contains("TUNE_FEATURES", "cortexa75-cortexa55", " -mcpu=cortex-a75.cortex-a55", "", d)…
H A Dtune-cortexa76-cortexa55.inc2 # Tune Settings for big.LITTLE Cortex-A76 - Cortex-A55
6 TUNEVALID[cortexa76-cortexa55] = "Enable big.LITTLE Cortex-A76.Cortex-A55 specific processor optimi…
8 …{@bb.utils.contains("TUNE_FEATURES", "cortexa76-cortexa55", " -mcpu=cortex-a76.cortex-a55", "", d)…
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-imx8-ca35.dtsi14 /* We have 1 clusters having 4 Cortex-A35 cores */
17 compatible = "arm,cortex-a35";
25 compatible = "arm,cortex-a35";
33 compatible = "arm,cortex-a35";
41 compatible = "arm,cortex-a35";
H A Dbcm2836.dtsi20 compatible = "arm,cortex-a7-pmu";
43 compatible = "arm,cortex-a7";
50 compatible = "arm,cortex-a7";
57 compatible = "arm,cortex-a7";
64 compatible = "arm,cortex-a7";
/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
89 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
108 into a big and little cluster with 4 cores each) Cortex-A53 including
142 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
143 and quad-core Cortex-A53.
153 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
/openbmc/u-boot/arch/arm/mach-exynos/
H A DKconfig14 Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
33 Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
34 Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
44 Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
45 Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
62 - 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
84 The LS2080A integrated multicore processor combines eight ARM Cortex-A57
91 - Eight 64-bit ARM Cortex-A57 CPUs
128 The LS1012A features an advanced 64-bit ARM v8 Cortex-
134 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
170 The LS1046A integrated multicore processor combines four ARM Cortex-A72
176 - Four 64-bit ARM Cortex-A72 CPUs
211 The LS2088A integrated multicore processor combines eight ARM Cortex-A72
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7m/
H A Dtune-cortexm4.inc2 # Tune Settings for Cortex-M4
6 TUNEVALID[cortexm4] = "Enable Cortex-M4 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexm4', ' -mcpu=cortex-m4', '', d)}"
H A Dtune-cortexm3.inc2 # Tune Settings for Cortex-M3
6 TUNEVALID[cortexm3] = "Enable Cortex-M3 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexm3', ' -mcpu=cortex-m3', '', d)}"
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv6m/
H A Dtune-cortexm1.inc2 # Tune Settings for Cortex-M1
6 TUNEVALID[cortexm1] = "Enable Cortex-M1 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexm1', ' -mcpu=cortex-m1', '', d)}"
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv9a/
H A Dtune-cortexa710.inc2 # Tune Settings for cortex-a710
6 TUNEVALID[cortexa710] = "Enable cortex-a710 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa710', ' -mcpu=cortex-a710', '', d)}"
H A Dtune-cortexa510.inc2 # Tune Settings for cortex-a510
6 TUNEVALID[cortexa510] = "Enable cortex-a510 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa510', ' -mcpu=cortex-a510', '', d)}"
H A Dtune-cortexx3.inc2 # Tune Settings for cortex-x3
6 TUNEVALID[cortexx3] = "Enable cortex-x3 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexx3', ' -mcpu=cortex-x3', '', d)}"
H A Dtune-cortexx2.inc2 # Tune Settings for cortex-x2
6 TUNEVALID[cortexx2] = "Enable cortex-x2 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexx2', ' -mcpu=cortex-x2', '', d)}"
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7r/
H A Dtune-cortexr4.inc2 # Tune Settings for Cortex-R4
6 TUNEVALID[cortexr4] = "Enable Cortex-R4 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexr4', ' -mcpu=cortex-r4', '', d)}"

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