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/openbmc/linux/arch/arm/mm/
H A Dproc-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
14 #include "proc-macros.S"
31 * - loc - location to jump to for soft reset
104 * This should be able to cover all ARMv7-M cores.
140 ldmia sp, {r0-r3, r12}
144 @ Special-purpose control register
150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
152 teq r8, #0 @ re-evalutae condition
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,corstone1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vishnu Banavath <vishnu.banavath@arm.com>
11 - Rui Miguel Silva <rui.silva@linaro.org>
14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
25 seamless integration of the optional CryptoCell™-312 cryptographic
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H A Dactions.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
19 - items:
20 - enum:
21 - allo,sparky # Allo.com Sparky
22 - cubietech,cubieboard6 # Cubietech CubieBoard6
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/openbmc/linux/Documentation/devicetree/bindings/arm/stm32/
H A Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AHB interconnect
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
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/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8-1m/
H A Dtune-cortexm55.inc2 # Tune Settings for Cortex-M55
6 TUNEVALID[cortexm55] = "Enable Cortex-M55 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexm55', ' -mcpu=cortex-m55', '', d)}"
9 require conf/machine/include/arm/arch-armv8-1m-main.inc
12 ARMPKGARCH:tune-cortexm55 = "cortexm55"
13 # We do not want -march since -mcpu is added above to cover for it
14 TUNE_FEATURES:tune-cortexm55 = "cortexm55"
15 PACKAGE_EXTRA_ARCHS:tune-cortexm55 = "${PACKAGE_EXTRA_ARCHS:tune-armv8-1m-main} cortexm55"
/openbmc/qemu/docs/system/arm/
H A Dmps2.rst1 …ards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521…
4 These board models use Arm M-profile or R-profile CPUs.
16 FPGA images using M-profile CPUs:
18 ``mps2-an385``
19 Cortex-M3 as documented in Arm Application Note AN385
20 ``mps2-an386``
21 Cortex-M4 as documented in Arm Application Note AN386
22 ``mps2-an500``
23 Cortex-M7 as documented in Arm Application Note AN500
24 ``mps2-an505``
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H A Dcpu-features.rst10 Cortex-A15 and the Cortex-A57, which respectively implement Arm
11 architecture reference manuals ARMv7-A and ARMv8-A, may both optionally
12 implement PMUs. For example, if a user wants to use a Cortex-A15 without
13 a PMU, then the ``-cpu`` parameter should contain ``pmu=off`` on the QEMU
14 command line, i.e. ``-cpu cortex-a15,pmu=off``.
18 that implement the ARMv8-A architecture reference manual may optionally
20 ``aarch64`` CPU property. A CPU type such as the Cortex-A15, which does
21 not implement ARMv8-A, will not have the ``aarch64`` CPU property.
30 prefixed with "kvm-" and are described in "KVM VCPU Features".
36 CPU type is possible with the ``query-cpu-model-expansion`` QMP command.
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H A Daspeed.rst1 …-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280…
6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
8 with dual cores ARM Cortex-A7 CPUs (1.2GHz) and more recently the AST2700
9 with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz)
16 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
17 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
18 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
19 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
23 - ``ast2500-evb`` Aspeed AST2500 Evaluation board
24 - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
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H A Dstm32.rst1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…
4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller
19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
20 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series.
21 The following machines are based on this ARM Cortex-M4F chip :
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H A Drealview.rst1 Arm Realview boards (``realview-eb``, ``realview-eb-mpcore``, ``realview-pb-a8``, ``realview-pbx-a9…
5 the EB, PB-A8 and PBX-A9. Due to interactions with the bootloader, only
8 Kernels for the PB-A8 board should have CONFIG_REALVIEW_HIGH_PHYS_OFFSET
9 enabled in the kernel, and expect 512M RAM. Kernels for The PBX-A9 board
11 disabled and expect 1024M RAM.
15 - ARM926E, ARM1136, ARM11MPCore, Cortex-A8 or Cortex-A9 MPCore CPU
17 - Arm AMBA Generic/Distributed Interrupt Controller
19 - Four PL011 UARTs
21 - SMC 91c111 or SMSC LAN9118 Ethernet adapter
23 - PL110 LCD controller
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H A Dxlnx-zynq.rst1 Xilinx Zynq board (``xilinx-zynq-a9``)
4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
10 QEMU xilinx-zynq-a9 board supports following devices:
11 - A9 MPCORE
12 - cortex-a9
13 - GIC v1
14 - Generic timer
15 - wdt
16 - OCM 256KB
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/openbmc/qemu/include/hw/watchdog/
H A Dcmsdk-apb-watchdog.h13 * This is a model of the "APB watchdog" which is part of the Cortex-M
14 * System Design Kit (CMSDK) and documented in the Cortex-M System
16 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
25 * (For instance the IoTKit does this with the non-secure watchdog, so that
26 * secure code can control whether non-secure code can perform a system
39 #define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"
44 * cmsdk-apb-watchdog device.
46 #define TYPE_LUMINARY_WATCHDOG "luminary-watchdog"
/openbmc/qemu/include/hw/timer/
H A Dcmsdk-apb-dualtimer.h2 * ARM CMSDK APB dual-timer emulation
13 * This is a model of the "APB dual-input timer" which is part of the Cortex-M
14 * System Design Kit (CMSDK) and documented in the Cortex-M System
16 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
34 #define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
38 /* One of the two identical timer modules in the dual-timer module */
/openbmc/openbmc/meta-arm/meta-arm-bsp/documentation/corstone1000/
H A Dsoftware-architecture.rst2 # Copyright (c) 2022-2024, Arm Limited.
4 # SPDX-License-Identifier: MIT
12 Arm Corstone-1000
15 Arm Corstone-1000 is a reference solution for IoT devices. It is part of
19 Corstone-1000 software plus hardware reference solution is PSA Level-2 ready
21 More information on the Corstone-1000 subsystem product and design can be
23 `Arm Corstone-1000 Software`_ and `Arm Corstone-1000 Technical Overview`_.
28 present in the user-guide document.
34 The software architecture of Corstone-1000 platform is a reference
49 cryptographic functions. It is based on an Cortex-M0+ processor,
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/openbmc/openbmc/meta-arm/meta-arm-bsp/conf/machine/
H A Dmusca-b1.conf1 # Configuration for Musca-B1 development board
4 #@NAME: Musca-B1 machine
5 #@DESCRIPTION: Machine configuration for Musca-B1
7 DEFAULTTUNE ?= "armv8m-main"
8 require conf/machine/include/arm/armv8-m/tune-cortexm33.inc
10 # GLIBC will not work with Cortex-M.
16 QB_SYSTEM_NAME = "qemu-system-arm"
17 QB_MACHINE = "-machine musca-b1"
18 QB_CPU = "-cpu cortex-m33"
19 QB_GRAPHICS = "-nographic -vga none"
H A Dmusca-s1.conf1 # Configuration for Musca-S1 development board
4 #@NAME: Musca-S1 machine
5 #@DESCRIPTION: Machine configuration for Musca-S1
7 require conf/machine/include/arm/armv8-m/tune-cortexm33.inc
9 # GLIBC will not work with Cortex-M.
15 QB_SYSTEM_NAME = "qemu-system-arm"
16 QB_MACHINE = "-machine musca-s1"
17 QB_CPU = "-cpu cortex-m33"
18 QB_GRAPHICS = "-nographic -vga none"
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,rpmsg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
14 are SAI, MICFIL, DMA controlled by Cortex M core. What we see from
18 Cortex-A and Cortex-M.
21 - $ref: sound-card-common.yaml#
26 - fsl,imx7ulp-rpmsg-audio
27 - fsl,imx8mn-rpmsg-audio
28 - fsl,imx8mm-rpmsg-audio
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/openbmc/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dsilicon-errata.txt1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
11 M: Will Deacon <will.deacon@arm.com>
15 ---------------------------------------------------------------------
16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
55 相應的內核配置（Kconfig）選項被加在 「內核特性（Kernel Features）」->
66 +----------------+-----------------+-----------------+-------------------------+
67 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
68 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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/openbmc/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dsilicon-errata.txt1 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
9 M: Will Deacon <will.deacon@arm.com>
12 ---------------------------------------------------------------------
13 Documentation/arch/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
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H A Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
51 compatible = "arm,cortex-a55";
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/openbmc/qemu/tests/functional/
H A Dtest_aarch64_tcg_plugins.py5 # These are a little more involved than the basic tests run by check-tcg.
12 # SPDX-License-Identifier: GPL-2.0-or-later
27 KERNEL_COMMON_COMMAND_LINE = 'printk.time=1 panic=-1 '
34 vm.add_args('-kernel', kernel_path,
35 '-append', kernel_command_line,
36 '-plugin', plugin,
37 '-d', 'plugin',
38 '-D', plugin_log,
39 '-net', 'none',
40 '-no-reboot')
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/openbmc/qemu/target/arm/tcg/
H A Dcpu-v7m.c2 * QEMU ARMv7-M TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "hw/core/tcg-cpu-ops.h"
24 CPUARMState *env = &cpu->env; in arm_v7m_cpu_exec_interrupt()
28 * ARMv7-M interrupt masking works differently than -A or -R. in arm_v7m_cpu_exec_interrupt()
36 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { in arm_v7m_cpu_exec_interrupt()
37 cs->exception_index = EXCP_IRQ; in arm_v7m_cpu_exec_interrupt()
38 cc->tcg_ops->do_interrupt(cs); in arm_v7m_cpu_exec_interrupt()
49 set_feature(&cpu->env, ARM_FEATURE_V6); in cortex_m0_initfn()
50 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m0_initfn()
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/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm4708.dtsi5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
39 secondary-boot-reg = <0xffff0400>;
/openbmc/qemu/docs/system/
H A Dtarget-arm.rst1 .. _ARM-System-emulator:
4 -------------------
6 QEMU can emulate both 32-bit and 64-bit Arm CPUs. Use the
7 ``qemu-system-aarch64`` executable to simulate a 64-bit Arm machine.
8 You can use either ``qemu-system-arm`` or ``qemu-system-aarch64``
9 to simulate a 32-bit Arm machine: in general, command lines that
10 work for ``qemu-system-arm`` will behave the same when used with
11 ``qemu-system-aarch64``.
16 are generally built into "system-on-chip" (SoC) designs created by
22 The situation for 64-bit Arm is fairly similar, except that we don't
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