Lines Matching +full:cortex +full:- +full:m
2 * QEMU ARMv7-M TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "hw/core/tcg-cpu-ops.h"
24 CPUARMState *env = &cpu->env; in arm_v7m_cpu_exec_interrupt()
28 * ARMv7-M interrupt masking works differently than -A or -R. in arm_v7m_cpu_exec_interrupt()
36 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { in arm_v7m_cpu_exec_interrupt()
37 cs->exception_index = EXCP_IRQ; in arm_v7m_cpu_exec_interrupt()
38 cc->tcg_ops->do_interrupt(cs); in arm_v7m_cpu_exec_interrupt()
49 set_feature(&cpu->env, ARM_FEATURE_V6); in cortex_m0_initfn()
50 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m0_initfn()
52 cpu->midr = 0x410cc200; in cortex_m0_initfn()
57 * to values corresponding to the Cortex-M0's implemented in cortex_m0_initfn()
62 cpu->isar.id_pfr0 = 0x00000030; in cortex_m0_initfn()
63 cpu->isar.id_pfr1 = 0x00000200; in cortex_m0_initfn()
64 cpu->isar.id_dfr0 = 0x00100000; in cortex_m0_initfn()
65 cpu->id_afr0 = 0x00000000; in cortex_m0_initfn()
66 cpu->isar.id_mmfr0 = 0x00000030; in cortex_m0_initfn()
67 cpu->isar.id_mmfr1 = 0x00000000; in cortex_m0_initfn()
68 cpu->isar.id_mmfr2 = 0x00000000; in cortex_m0_initfn()
69 cpu->isar.id_mmfr3 = 0x00000000; in cortex_m0_initfn()
70 cpu->isar.id_isar0 = 0x01141110; in cortex_m0_initfn()
71 cpu->isar.id_isar1 = 0x02111000; in cortex_m0_initfn()
72 cpu->isar.id_isar2 = 0x21112231; in cortex_m0_initfn()
73 cpu->isar.id_isar3 = 0x01111110; in cortex_m0_initfn()
74 cpu->isar.id_isar4 = 0x01310102; in cortex_m0_initfn()
75 cpu->isar.id_isar5 = 0x00000000; in cortex_m0_initfn()
76 cpu->isar.id_isar6 = 0x00000000; in cortex_m0_initfn()
82 set_feature(&cpu->env, ARM_FEATURE_V7); in cortex_m3_initfn()
83 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m3_initfn()
84 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); in cortex_m3_initfn()
85 cpu->midr = 0x410fc231; in cortex_m3_initfn()
86 cpu->pmsav7_dregion = 8; in cortex_m3_initfn()
87 cpu->isar.id_pfr0 = 0x00000030; in cortex_m3_initfn()
88 cpu->isar.id_pfr1 = 0x00000200; in cortex_m3_initfn()
89 cpu->isar.id_dfr0 = 0x00100000; in cortex_m3_initfn()
90 cpu->id_afr0 = 0x00000000; in cortex_m3_initfn()
91 cpu->isar.id_mmfr0 = 0x00000030; in cortex_m3_initfn()
92 cpu->isar.id_mmfr1 = 0x00000000; in cortex_m3_initfn()
93 cpu->isar.id_mmfr2 = 0x00000000; in cortex_m3_initfn()
94 cpu->isar.id_mmfr3 = 0x00000000; in cortex_m3_initfn()
95 cpu->isar.id_isar0 = 0x01141110; in cortex_m3_initfn()
96 cpu->isar.id_isar1 = 0x02111000; in cortex_m3_initfn()
97 cpu->isar.id_isar2 = 0x21112231; in cortex_m3_initfn()
98 cpu->isar.id_isar3 = 0x01111110; in cortex_m3_initfn()
99 cpu->isar.id_isar4 = 0x01310102; in cortex_m3_initfn()
100 cpu->isar.id_isar5 = 0x00000000; in cortex_m3_initfn()
101 cpu->isar.id_isar6 = 0x00000000; in cortex_m3_initfn()
108 set_feature(&cpu->env, ARM_FEATURE_V7); in cortex_m4_initfn()
109 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m4_initfn()
110 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); in cortex_m4_initfn()
111 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); in cortex_m4_initfn()
112 cpu->midr = 0x410fc240; /* r0p0 */ in cortex_m4_initfn()
113 cpu->pmsav7_dregion = 8; in cortex_m4_initfn()
114 cpu->isar.mvfr0 = 0x10110021; in cortex_m4_initfn()
115 cpu->isar.mvfr1 = 0x11000011; in cortex_m4_initfn()
116 cpu->isar.mvfr2 = 0x00000000; in cortex_m4_initfn()
117 cpu->isar.id_pfr0 = 0x00000030; in cortex_m4_initfn()
118 cpu->isar.id_pfr1 = 0x00000200; in cortex_m4_initfn()
119 cpu->isar.id_dfr0 = 0x00100000; in cortex_m4_initfn()
120 cpu->id_afr0 = 0x00000000; in cortex_m4_initfn()
121 cpu->isar.id_mmfr0 = 0x00000030; in cortex_m4_initfn()
122 cpu->isar.id_mmfr1 = 0x00000000; in cortex_m4_initfn()
123 cpu->isar.id_mmfr2 = 0x00000000; in cortex_m4_initfn()
124 cpu->isar.id_mmfr3 = 0x00000000; in cortex_m4_initfn()
125 cpu->isar.id_isar0 = 0x01141110; in cortex_m4_initfn()
126 cpu->isar.id_isar1 = 0x02111000; in cortex_m4_initfn()
127 cpu->isar.id_isar2 = 0x21112231; in cortex_m4_initfn()
128 cpu->isar.id_isar3 = 0x01111110; in cortex_m4_initfn()
129 cpu->isar.id_isar4 = 0x01310102; in cortex_m4_initfn()
130 cpu->isar.id_isar5 = 0x00000000; in cortex_m4_initfn()
131 cpu->isar.id_isar6 = 0x00000000; in cortex_m4_initfn()
138 set_feature(&cpu->env, ARM_FEATURE_V7); in cortex_m7_initfn()
139 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m7_initfn()
140 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); in cortex_m7_initfn()
141 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); in cortex_m7_initfn()
142 cpu->midr = 0x411fc272; /* r1p2 */ in cortex_m7_initfn()
143 cpu->pmsav7_dregion = 8; in cortex_m7_initfn()
144 cpu->isar.mvfr0 = 0x10110221; in cortex_m7_initfn()
145 cpu->isar.mvfr1 = 0x12000011; in cortex_m7_initfn()
146 cpu->isar.mvfr2 = 0x00000040; in cortex_m7_initfn()
147 cpu->isar.id_pfr0 = 0x00000030; in cortex_m7_initfn()
148 cpu->isar.id_pfr1 = 0x00000200; in cortex_m7_initfn()
149 cpu->isar.id_dfr0 = 0x00100000; in cortex_m7_initfn()
150 cpu->id_afr0 = 0x00000000; in cortex_m7_initfn()
151 cpu->isar.id_mmfr0 = 0x00100030; in cortex_m7_initfn()
152 cpu->isar.id_mmfr1 = 0x00000000; in cortex_m7_initfn()
153 cpu->isar.id_mmfr2 = 0x01000000; in cortex_m7_initfn()
154 cpu->isar.id_mmfr3 = 0x00000000; in cortex_m7_initfn()
155 cpu->isar.id_isar0 = 0x01101110; in cortex_m7_initfn()
156 cpu->isar.id_isar1 = 0x02112000; in cortex_m7_initfn()
157 cpu->isar.id_isar2 = 0x20232231; in cortex_m7_initfn()
158 cpu->isar.id_isar3 = 0x01111131; in cortex_m7_initfn()
159 cpu->isar.id_isar4 = 0x01310132; in cortex_m7_initfn()
160 cpu->isar.id_isar5 = 0x00000000; in cortex_m7_initfn()
161 cpu->isar.id_isar6 = 0x00000000; in cortex_m7_initfn()
168 set_feature(&cpu->env, ARM_FEATURE_V8); in cortex_m33_initfn()
169 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m33_initfn()
170 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); in cortex_m33_initfn()
171 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); in cortex_m33_initfn()
172 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); in cortex_m33_initfn()
173 cpu->midr = 0x410fd213; /* r0p3 */ in cortex_m33_initfn()
174 cpu->pmsav7_dregion = 16; in cortex_m33_initfn()
175 cpu->sau_sregion = 8; in cortex_m33_initfn()
176 cpu->isar.mvfr0 = 0x10110021; in cortex_m33_initfn()
177 cpu->isar.mvfr1 = 0x11000011; in cortex_m33_initfn()
178 cpu->isar.mvfr2 = 0x00000040; in cortex_m33_initfn()
179 cpu->isar.id_pfr0 = 0x00000030; in cortex_m33_initfn()
180 cpu->isar.id_pfr1 = 0x00000210; in cortex_m33_initfn()
181 cpu->isar.id_dfr0 = 0x00200000; in cortex_m33_initfn()
182 cpu->id_afr0 = 0x00000000; in cortex_m33_initfn()
183 cpu->isar.id_mmfr0 = 0x00101F40; in cortex_m33_initfn()
184 cpu->isar.id_mmfr1 = 0x00000000; in cortex_m33_initfn()
185 cpu->isar.id_mmfr2 = 0x01000000; in cortex_m33_initfn()
186 cpu->isar.id_mmfr3 = 0x00000000; in cortex_m33_initfn()
187 cpu->isar.id_isar0 = 0x01101110; in cortex_m33_initfn()
188 cpu->isar.id_isar1 = 0x02212000; in cortex_m33_initfn()
189 cpu->isar.id_isar2 = 0x20232232; in cortex_m33_initfn()
190 cpu->isar.id_isar3 = 0x01111131; in cortex_m33_initfn()
191 cpu->isar.id_isar4 = 0x01310132; in cortex_m33_initfn()
192 cpu->isar.id_isar5 = 0x00000000; in cortex_m33_initfn()
193 cpu->isar.id_isar6 = 0x00000000; in cortex_m33_initfn()
194 cpu->clidr = 0x00000000; in cortex_m33_initfn()
195 cpu->ctr = 0x8000c000; in cortex_m33_initfn()
202 set_feature(&cpu->env, ARM_FEATURE_V8); in cortex_m55_initfn()
203 set_feature(&cpu->env, ARM_FEATURE_V8_1M); in cortex_m55_initfn()
204 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m55_initfn()
205 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); in cortex_m55_initfn()
206 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); in cortex_m55_initfn()
207 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); in cortex_m55_initfn()
208 cpu->midr = 0x410fd221; /* r0p1 */ in cortex_m55_initfn()
209 cpu->revidr = 0; in cortex_m55_initfn()
210 cpu->pmsav7_dregion = 16; in cortex_m55_initfn()
211 cpu->sau_sregion = 8; in cortex_m55_initfn()
213 cpu->isar.mvfr0 = 0x10110221; in cortex_m55_initfn()
214 cpu->isar.mvfr1 = 0x12100211; in cortex_m55_initfn()
215 cpu->isar.mvfr2 = 0x00000040; in cortex_m55_initfn()
216 cpu->isar.id_pfr0 = 0x20000030; in cortex_m55_initfn()
217 cpu->isar.id_pfr1 = 0x00000230; in cortex_m55_initfn()
218 cpu->isar.id_dfr0 = 0x10200000; in cortex_m55_initfn()
219 cpu->id_afr0 = 0x00000000; in cortex_m55_initfn()
220 cpu->isar.id_mmfr0 = 0x00111040; in cortex_m55_initfn()
221 cpu->isar.id_mmfr1 = 0x00000000; in cortex_m55_initfn()
222 cpu->isar.id_mmfr2 = 0x01000000; in cortex_m55_initfn()
223 cpu->isar.id_mmfr3 = 0x00000011; in cortex_m55_initfn()
224 cpu->isar.id_isar0 = 0x01103110; in cortex_m55_initfn()
225 cpu->isar.id_isar1 = 0x02212000; in cortex_m55_initfn()
226 cpu->isar.id_isar2 = 0x20232232; in cortex_m55_initfn()
227 cpu->isar.id_isar3 = 0x01111131; in cortex_m55_initfn()
228 cpu->isar.id_isar4 = 0x01310132; in cortex_m55_initfn()
229 cpu->isar.id_isar5 = 0x00000000; in cortex_m55_initfn()
230 cpu->isar.id_isar6 = 0x00000000; in cortex_m55_initfn()
231 cpu->clidr = 0x00000000; /* caches not implemented */ in cortex_m55_initfn()
232 cpu->ctr = 0x8303c003; in cortex_m55_initfn()
262 acc->info = data; in arm_v7m_class_init()
263 cc->tcg_ops = &arm_v7m_tcg_ops; in arm_v7m_class_init()
264 cc->gdb_core_xml_file = "arm-m-profile.xml"; in arm_v7m_class_init()
268 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
270 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
272 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
274 { .name = "cortex-m7", .initfn = cortex_m7_initfn,
276 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
278 { .name = "cortex-m55", .initfn = cortex_m55_initfn,