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/openbmc/openbmc/poky/meta/recipes-devtools/valgrind/valgrind/
H A D0001-makefiles-Drop-setting-mcpu-to-cortex-a8-on-arm-arch.patch3 Date: Thu, 20 Apr 2017 10:11:16 -0700
4 Subject: [PATCH] makefiles: Drop setting -mcpu to cortex-a8 on arm
7 We can not assume that all arches armv7+ are cortex-a8 only
8 it fails to build for rpi which is armv7ve based (cortex-a8) cpu
11 | cc1: warning: switch -mcpu=cortex-a8 conflicts with -march=armv7ve switch
13 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
15 Signed-off-by: Khem Raj <raj.khem@gmail.com>
16 ---
17 Makefile.all.am | 6 +++---
18 helgrind/tests/Makefile.am | 6 +++---
[all …]
H A Duse-appropriate-march-mcpu-mfpu-for-ARM-test-apps.patch3 Date: Tue, 19 Jan 2016 16:00:00 -0800
4 Subject: [PATCH] use appropriate -march/-mcpu/-mfpu for ARM test apps
7 -march/-mcpu/-mfpu flags to support the instructions being tested.
12 -march=armv7ve and -mcpu=cortex-a15 (since some TUNE_CCARGS may set
13 -march=armv7-a and adding -mcpu=cortex-a15 alone is not enough to
14 over-ride that).
18 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
20 Signed-off-by: Andre McCurdy <armccurdy@gmail.com>
21 ---
22 none/tests/arm/Makefile.am | 6 ++++--
[all …]
H A D0001-configure-Drop-setting-mcpu-cortex-a8-on-arm.patch3 Date: Fri, 10 May 2024 16:27:34 -0700
4 Subject: [PATCH] configure: Drop setting mcpu=cortex-a8 on arm
6 The -march settings from environment expresses the flags
10 [1] https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=928224
12 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
13 Signed-off-by: Khem Raj <raj.khem@gmail.com>
14 ---
15 configure.ac | 4 ++--
16 1 file changed, 2 insertions(+), 2 deletions(-)
18 diff --git a/configure.ac b/configure.ac
[all …]
/openbmc/qemu/docs/system/arm/
H A Drealview.rst1 Arm Realview boards (``realview-eb``, ``realview-eb-mpcore``, ``realview-pb-a8``, ``realview-pbx-a9…
5 the EB, PB-A8 and PBX-A9. Due to interactions with the bootloader, only
8 Kernels for the PB-A8 board should have CONFIG_REALVIEW_HIGH_PHYS_OFFSET
9 enabled in the kernel, and expect 512M RAM. Kernels for The PBX-A9 board
15 - ARM926E, ARM1136, ARM11MPCore, Cortex-A8 or Cortex-A9 MPCore CPU
17 - Arm AMBA Generic/Distributed Interrupt Controller
19 - Four PL011 UARTs
21 - SMC 91c111 or SMSC LAN9118 Ethernet adapter
23 - PL110 LCD controller
25 - PL050 KMI with PS/2 keyboard and mouse
[all …]
H A Dcubieboard.rst5 which is a Cortex-A8 based single-board computer using
10 - Timer
11 - UART
12 - RTC
13 - EMAC
14 - SDHCI
15 - USB controller
16 - SATA controller
17 - TWI (I2C) controller
18 - SPI controller
[all …]
H A Dintegratorcp.rst6 - ARM926E, ARM1026E, ARM946E, ARM1136 or Cortex-A8 CPU
8 - Two PL011 UARTs
10 - SMC 91c111 Ethernet adapter
12 - PL110 LCD controller
14 - PL050 KMI with PS/2 keyboard and mouse.
16 - PL181 MultiMedia Card Interface with SD card.
H A Dversatile.rst6 - ARM926E, ARM1136 or Cortex-A8 CPU
8 - PL190 Vectored Interrupt Controller
10 - Four PL011 UARTs
12 - SMC 91c111 Ethernet adapter
14 - PL110 LCD controller
16 - PL050 KMI with PS/2 keyboard and mouse.
18 - PCI host bridge. Note the emulated PCI bridge only provides access
24 - PCI OHCI USB controller.
26 - LSI53C895A PCI SCSI Host Bus Adapter with hard disk and CD-ROM
29 - PL181 MultiMedia Card Interface with SD card.
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/
H A DKconfig82 The AM335x high performance SOC features a Cortex-A8
92 The AM335x high performance SOC features a Cortex-A8
112 The AM43xx high performance SOC features a Cortex-A9
113 ARM core, a quad core PRU-ICSS for industrial Ethernet
130 The AM335x high performance SOC features a Cortex-A8
131 ARM core, a dual core PRU-ICSS for industrial Ethernet
149 Reserved EMIF region start address. Set to "0" to auto-select
178 boot image. For non-XIP devices, the ROM then copies the image into
181 on the device type (secure/non-secure), boot media (xip/non-xip) and
185 source "arch/arm/mach-omap2/omap3/Kconfig"
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,realview.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
31 - const: arm,realview-pb1176
[all …]
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
[all …]
/openbmc/qemu/hw/arm/
H A Dcubieboard.c20 #include "qemu/error-report.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/arm/allwinner-a10.h"
43 if (machine->firmware) { in cubieboard_init()
49 if (machine->ram_size != 512 * MiB && in cubieboard_init()
50 machine->ram_size != 1 * GiB) { in cubieboard_init()
59 if (!object_property_set_int(OBJECT(&a10->emac), "phy-addr", 1, &err)) { in cubieboard_init()
64 if (!object_property_set_int(OBJECT(&a10->timer), "clk0-freq", 32768, in cubieboard_init()
70 if (!object_property_set_int(OBJECT(&a10->timer), "clk1-freq", 24000000, in cubieboard_init()
82 i2c = I2C_BUS(qdev_get_child_bus(DEVICE(&a10->i2c0), "i2c")); in cubieboard_init()
[all …]
H A Drealview.c4 * Copyright (c) 2006-2007 CodeSourcery.
16 #include "hw/core/split-irq.h"
20 #include "hw/qdev-core.h"
25 #include "qemu/error-report.h"
33 #include "target/arm/cpu-qom.h"
64 qdev_prop_set_uint32(splitter, "num-lines", 2); in split_irq_from_named()
91 unsigned int smp_cpus = machine->smp.cpus; in realview_init()
98 ram_addr_t ram_size = machine->ram_size; in realview_init()
119 Object *cpuobj = object_new(machine->cpu_type); in realview_init()
130 object_property_set_int(cpuobj, "reset-cbar", periphbase, in realview_init()
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-pba8.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
27 model = "ARM RealView Platform Baseboard for Cortex-A8";
28 compatible = "arm,realview-pba8";
32 #address-cells = <1>;
33 #size-cells = <0>;
34 enable-method = "arm,realview-smp";
38 compatible = "arm,cortex-a8";
44 compatible = "arm,cortex-a8-pmu";
45 interrupt-parent = <&intc>;
[all …]
/openbmc/u-boot/doc/
H A DREADME.s5pc1xx5 This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx
15 While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
16 with -march=armv5 to allow more compilers to work. For U-Boot code this has
48 gpio_cfg_pin(&gpio->gpio_a, 0, GPIO_IRQ);
51 gpio_direction_input(&gpio->gpio_a, 0);
54 gpio_direction_output(&gpio->gpio_a, 0, 1);
57 gpio_set_value(&gpio->gpio_a, 0, 0);
60 value = gpio_get_value(&gpio->gpio_a, 0);
H A DREADME.omap35 This README is about U-Boot support for TI's ARM Cortex-A8 based OMAP3 [1]
6 family of SoCs. TI's OMAP3 SoC family contains an ARM Cortex-A8. Additionally,
24 * CompuLab Ltd. CM-T35 [8]
59 * CM-T35:
68 To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot
81 is typically used to write 2nd stage bootloader (known as 'x-loader') which is
92 ----
121 ---
132 Wait for a transfer to end - this hast to be called before a channel
141 OMAP3 ROM code can only handle 1-bit hamming ECC for accessing first page
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7a/
H A Dtune-cortexa8.inc1 DEFAULTTUNE ?= "cortexa8thf-neon"
3 require conf/machine/include/arm/arch-armv7a.inc
5 TUNEVALID[cortexa8] = "Enable Cortex-A8 specific processor optimizations"
6 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa8', ' -mcpu=cortex-a8', '', d)}"
10 AVAILTUNES += "cortexa8 cortexa8t cortexa8-neon cortexa8t-neon"
11 ARMPKGARCH:tune-cortexa8 = "cortexa8"
12 ARMPKGARCH:tune-cortexa8t = "cortexa8"
13 ARMPKGARCH:tune-cortexa8-neon = "cortexa8"
14 ARMPKGARCH:tune-cortexa8t-neon = "cortexa8"
16 TUNE_FEATURES:tune-cortexa8 = "arm vfp cortexa8"
[all …]
/openbmc/linux/arch/arm/mm/
H A Dproc-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
19 #include "proc-macros.S"
22 #include "proc-v7-3level.S"
24 #include "proc-v7-2level.S"
27 .arch armv7-a
48 * - loc - location to jump to for soft reset
[all …]
/openbmc/linux/Documentation/arch/arm/
H A Dsunxi.rst10 ------------
11 Linux kernel mach directory: arch/arm/mach-sunxi
16 - Allwinner F20 (sun3i)
20 * ARM Cortex-A8 based SoCs
21 - Allwinner A10 (sun4i)
25 http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
28 …http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf
30 - Allwinner A10s (sun5i)
34 http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
36 - Allwinner A13 / R8 (sun5i)
[all …]
/openbmc/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
150 The ARM series is a line of low-power-consumption RISC chip designs
152 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
153 manufactured, but legacy ARM-based PC hardware remains popular in
164 supported in LLD until version 14. The combined range is -/+ 256 MiB,
257 Patch phys-to-virt and virt-to-phys translation functions at
261 This can only be used with non-XIP MMU kernels where the base
307 bool "MMU-based Paged Memory Management Support"
310 Select if you want MMU-based virtualised addressing space
350 # https://github.com/llvm/llvm-project/issues/50764
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dcpu-imx5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
19 static int mx5_cpu_rev = -1;
43 u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); in get_mx51_srev()
61 if (mx5_cpu_rev == -1) in mx51_revision()
72 * Dependent on link order - so the assumption is that vfp_init is called
89 u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); in get_mx53_srev()
109 if (mx5_cpu_rev == -1) in mx53_revision()
135 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); in imx5_pmu_init()
139 if (!of_property_read_bool(np, "secure-reg-access")) in imx5_pmu_init()
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dperf_event_v7.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
11 * Cortex-A8 has up to 4 configurable performance counters and
13 * Cortex-A9 has up to 31 configurable performance counters and
55 * - all (taken) branch instructions,
56 * - instructions that explicitly write the PC,
57 * - exception generating instructions.
82 /* ARMv7 Cortex-A8 specific event types */
88 /* ARMv7 Cortex-A9 specific event types */
93 /* ARMv7 Cortex-A5 specific event types */
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/valgrind/
H A Dvalgrind_3.23.0.bb5 LICENSE = "GPL-2.0-only & GPL-2.0-or-later & BSD-3-Clause"
15 SRC_URI = "https://sourceware.org/pub/valgrind/valgrind-${PV}.tar.bz2 \
16 file://fixed-perl-path.patch \
17 file://Added-support-for-PPC-instructions-mfatbu-mfatbl.patch \
18 file://run-ptest \
19 file://remove-for-aarch64 \
20 file://remove-for-all \
22 file://0005-Modify-vg_test-wrapper-to-support-PTEST-formats.patch \
23 file://use-appropriate-march-mcpu-mfpu-for-ARM-test-apps.patch \
24 file://avoid-neon-for-targets-which-don-t-support-it.patch \
[all …]
/openbmc/linux/arch/arm/boot/dts/cnxt/
H A Dcx92755.dtsi8 * This file is dual-licensed: you can use it either under the terms
48 #address-cells = <1>;
49 #size-cells = <1>;
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a8";
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <200000000>;
[all …]

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