| /openbmc/u-boot/board/freescale/mpc8572ds/ |
| H A D | README | 109 2. Build kernel image for core1:
118 set it to 0x20000000, assuming core1 will start from 512MB.
126 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
132 4. Create dtb for core1:
142 b. Bring up core1's kernel first:
145 => tftp 21000000 8572/uImage.core1
165 Please note only core0 will run U-Boot, core1 starts kernel directly after
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | qcom,sdm845-venus-v2.yaml | 67 video-core1:
84 - video-core1
119 video-core1 {
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| H A D | qcom,sdm845-venus.yaml | 64 video-core1:
94 - video-core1
124 video-core1 {
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| /openbmc/phosphor-inventory-manager/ |
| H A D | README.md | 151 "path": "system/chassis/motherboard/cpu0/core1",
166 `xyz/openbmc_project/system/chassis/motherboard/cpu0/core1` inventory object, it
171 /xyz/openbmc_project/inventory/system/chassis/motherboard/cpu0/core1/sensors
177 ['/xyz/openbmc_project/inventory/system/chassis/motherboard/cpu0/core1']
231 "path": "system/chassis/motherboard/cpu0/core1",
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| /openbmc/linux/arch/powerpc/boot/dts/fsl/ |
| H A D | mpc8572ds_camp_core1.dts | 3 * MPC8572 DS Core1 Device Tree Source in CAMP mode.
7 * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
9 * Please note to add "-b 1" for core1's dts compiling.
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| H A D | p1020rdb-pc_camp_core1.dts | 3 * P1020 RDB-PC Core1 Device Tree Source in CAMP mode.
7 * This dts allows core1 to have l2, eth0, crypto.
9 * Please note to add "-b 1" for core1's dts compiling.
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| /openbmc/linux/arch/arm/boot/dts/intel/axm/ |
| H A D | axm5516-cpus.dtsi | 18 core1 {
32 core1 {
46 core1 {
60 core1 {
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| /openbmc/linux/arch/arm64/boot/dts/amd/ |
| H A D | amd-seattle-cpus.dtsi | 13 core1 {
21 core1 {
29 core1 {
37 core1 {
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| /openbmc/linux/Documentation/devicetree/bindings/gpu/ |
| H A D | arm,mali-bifrost.yaml | 184 - const: core1
207 - const: core1
225 - const: core1
241 - const: core1
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| /openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/ |
| H A D | LWP0.interface.yaml | 19 The "21" keyword.Core1 L2 Line delete.
35 The "31" keyword.Core1 L2 Line delete.
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| H A D | LWP2.interface.yaml | 19 The "21" keyword.Core1 L2 Line delete.
35 The "31" keyword.Core1 L2 Line delete.
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| H A D | LWP5.interface.yaml | 19 The "21" keyword.Core1 L2 Line delete.
35 The "31" keyword.Core1 L2 Line delete.
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| H A D | LWP1.interface.yaml | 19 The "21" keyword.Core1 L2 Line delete.
35 The "31" keyword.Core1 L2 Line delete.
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| H A D | LWP6.interface.yaml | 19 The "21" keyword.Core1 L2 Line delete.
35 The "31" keyword.Core1 L2 Line delete.
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| H A D | LWP7.interface.yaml | 19 The "21" keyword.Core1 L2 Line delete.
35 The "31" keyword.Core1 L2 Line delete.
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| H A D | LWP3.interface.yaml | 19 The "21" keyword.Core1 L2 Line delete.
35 The "31" keyword.Core1 L2 Line delete.
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| H A D | LWP4.interface.yaml | 19 The "21" keyword.Core1 L2 Line delete.
35 The "31" keyword.Core1 L2 Line delete.
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| /openbmc/linux/Documentation/devicetree/bindings/cpu/ |
| H A D | cpu-topology.txt | 203 core1 {
223 core1 {
244 core1 {
263 core1 {
416 core1 {
431 core1 {
510 core1 {
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| /openbmc/linux/drivers/remoteproc/ |
| H A D | ti_k3_r5_remoteproc.c | 539 * unhalt both the cores to start the execution - Core1 needs to be unhalted
541 * always in a higher power state that Core1 (implying Core1 needs to be started
562 /* boot vector need not be programmed for Core1 in LockStep mode */ in k3_r5_rproc_start()
610 * performed first on Core0 followed by Core1. The Split-mode requires that
611 * Core0 to be maintained always in a higher power state that Core1 (implying
612 * Core1 needs to be stopped first before Core0).
632 struct k3_r5_core *core1, *core = kproc->core; in k3_r5_rproc_stop() local
646 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, in k3_r5_rproc_stop()
648 if (core != core1 && core1->rproc->state != RPROC_OFFLINE) { in k3_r5_rproc_stop()
1066 * leveraging the Core1 TCMs as well in certain modes where they would have
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hip05.dtsi | 30 core1 {
44 core1 {
58 core1 {
72 core1 {
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| /openbmc/qemu/hw/misc/ |
| H A D | imx7_src.c | 191 if (FIELD_EX32(change_mask, CORE1, RST)) { in imx7_src_write()
207 if (FIELD_EX32(change_mask, CORE1, ENABLE)) { in imx7_src_write()
208 if (FIELD_EX32(current_value, CORE1, ENABLE)) { in imx7_src_write()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | meson-gxm.dtsi | 18 core1 {
33 core1 {
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| H A D | k3-am654.dtsi | 20 core1 {
30 core1 {
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| /openbmc/u-boot/include/configs/ |
| H A D | p1_p2_rdb_pc.h | 49 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
50 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
51 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
52 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
53 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
54 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
55 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
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| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,k3-r5f-rproc.yaml | 22 Core1's TCMs as well.
145 # modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
146 # R5F Core1 in LockStep mode:
297 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|