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/openbmc/linux/Documentation/devicetree/bindings/net/pcs/
H A Dfsl,lynx-pcs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/fsl,lynx-pcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Lynx PCS
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 NXP Lynx 10G and 28G SerDes have Ethernet PCS devices which can be used as
19 const: fsl,lynx-pcs
25 - compatible
26 - reg
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H A Drenesas,rzn1-miic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 '#address-cells':
20 '#size-cells':
25 - enum:
26 - renesas,r9a06g032-miic
27 - const: renesas,rzn1-miic
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H A Dmediatek,sgmiisys.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
19 - enum:
20 - mediatek,mt7622-sgmiisys
21 - mediatek,mt7629-sgmiisys
22 - mediatek,mt7981-sgmiisys_0
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/openbmc/linux/drivers/hwmon/peci/
H A Dcputemp.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2021 Intel Corporation
11 #include <linux/peci-cpu.h>
64 struct peci_sensor_data core[CORE_NUMS_MAX]; member
90 u32 pcs; in update_temp_target() local
93 if (!peci_sensor_need_update(&priv->temp.target.state)) in update_temp_target()
96 ret = peci_pcs_read(priv->peci_dev, PECI_PCS_TEMP_TARGET, 0, &pcs); in update_temp_target()
100 priv->temp.target.tjmax = in update_temp_target()
101 FIELD_GET(TEMP_TARGET_REF_TEMP_MASK, pcs) * MILLIDEGREE_PER_DEGREE; in update_temp_target()
103 tcontrol_margin = FIELD_GET(TEMP_TARGET_FAN_TEMP_MASK, pcs); in update_temp_target()
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
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H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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H A Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
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H A Dfsl,qoriq-mc-dpmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: ethernet-controller.yaml#
21 const: fsl,qoriq-mc-dpmac
27 phy-handle: true
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H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
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/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6352 family SERDES PCS support
35 err = mdiodev_c45_read(&mpcs->mdio, MDIO_MMD_PHYXS, regnum); in mv88e639x_read()
46 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, val); in mv88e639x_write()
52 return mdiodev_c45_modify(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, mask, in mv88e639x_modify()
59 return mdiodev_c45_modify_changed(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, in mv88e639x_modify_changed()
73 mpcs->mdio.dev.parent = dev; in mv88e639x_pcs_alloc()
74 mpcs->mdio.bus = bus; in mv88e639x_pcs_alloc()
75 mpcs->mdio.addr = addr; in mv88e639x_pcs_alloc()
77 snprintf(mpcs->name, sizeof(mpcs->name), in mv88e639x_pcs_alloc()
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
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H A Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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/openbmc/linux/drivers/net/dsa/
H A Dmt7530-mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/pcs/pcs-mtk-lynxi.h>
31 ret = bus->write(bus, 0x1f, 0x1f, page); in mt7530_regmap_write()
35 ret = bus->write(bus, 0x1f, r, lo); in mt7530_regmap_write()
39 ret = bus->write(bus, 0x1f, 0x10, hi); in mt7530_regmap_write()
54 ret = bus->write(bus, 0x1f, 0x1f, page); in mt7530_regmap_read()
58 lo = bus->read(bus, 0x1f, r); in mt7530_regmap_read()
59 hi = bus->read(bus, 0x1f, 0x10); in mt7530_regmap_read()
87 struct phylink_pcs *pcs; in mt7531_create_sgmii() local
95 mt7531_pcs_config[i] = devm_kzalloc(priv->dev, in mt7531_create_sgmii()
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-socfpga.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Adopted from dwmac-sti.c
7 #include <linux/mfd/altera-sysmgr.h>
13 #include <linux/mdio/mdio-regmap.h>
14 #include <linux/pcs-lynx.h>
67 void __iomem *splitter_base = dwmac->splitter_base; in socfpga_dwmac_fix_mac_speed()
68 void __iomem *sgmii_adapter_base = dwmac->sgmii_adapter_base; in socfpga_dwmac_fix_mac_speed()
69 struct device *dev = dwmac->dev; in socfpga_dwmac_fix_mac_speed()
71 struct phy_device *phy_dev = ndev->phydev; in socfpga_dwmac_fix_mac_speed()
105 struct device_node *np = dev->of_node; in socfpga_dwmac_parse_data()
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H A Dcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
18 #include <linux/pcs/pcs-xpcs.h>
29 /* Synopsys Core versions */
57 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
190 /* PCS */
269 /* PCS defines */
275 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
280 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
284 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
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/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Drenesas,rzn1-a5psw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 - $ref: dsa.yaml#/$defs/ethernet-ports
22 - enum:
23 - renesas,r9a06g032-a5psw
24 - const: renesas,rzn1-a5psw
31 - description: Device Level Ring (DLR) interrupt
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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-single.c25 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_data/pinctrl-single.h>
32 #include "core.h"
37 #define DRIVER_NAME "pinctrl-single"
41 * struct pcs_func_vals - mux function register offset and value pair
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
102 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
116 * struct pcs_data - wrapper for data needed by pinctrl framework
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/openbmc/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_main.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
9 * Copyright (c) 2010 - 2011 PetaLogix
10 * Copyright (c) 2019 - 2022 Calian Advanced Technologies
11 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
17 * - Add Axi Fifo support.
18 * - Factor out Axi DMA code into separate driver.
19 * - Test and fix basic multicast filtering.
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H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
157 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
201 /* Transmit inter-frame gap adjustment value */
235 /* In-Band FCS enable (FCS not stripped) */
251 /* In-Band FCS enable (FCS not generated) */
255 /* Inter-frame gap adjustment enable */
277 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
343 /* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
15 - fsl,imx8mq-usb-phy
16 - fsl,imx8mp-usb-phy
21 "#phy-cells":
27 clock-names:
29 - const: phy
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H A Dqcom,msm8996-qmp-usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
17 qcom,sc8280xp-qmp-usb3-uni-phy.yaml.
22 - qcom,ipq6018-qmp-usb3-phy
23 - qcom,ipq8074-qmp-usb3-phy
24 - qcom,msm8996-qmp-usb3-phy
25 - qcom,msm8998-qmp-usb3-phy
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/openbmc/u-boot/drivers/net/phy/
H A Dxilinx_phy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx PCS/PMA Core phy driver
5 * Copyright (C) 2015 - 2016 Xilinx, Inc.
46 if (AUTONEG_ENABLE == phydev->autoneg) { in xilinxphy_startup()
51 phydev->duplex = DUPLEX_FULL; in xilinxphy_startup()
53 phydev->duplex = DUPLEX_HALF; in xilinxphy_startup()
57 phydev->speed = SPEED_1000; in xilinxphy_startup()
61 phydev->speed = SPEED_100; in xilinxphy_startup()
65 phydev->speed = SPEED_10; in xilinxphy_startup()
75 phydev->duplex = DUPLEX_FULL; in xilinxphy_startup()
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/openbmc/openbmc/poky/meta-yocto-bsp/
H A DREADME.hardware.md15 (BSP) Developer's Guide - documentation source is in documentation/bspguide or
18 Note that these reference BSPs use the linux-yocto kernel and in general don't
26 The following boards are supported by the meta-yocto-bsp layer:
28 * Texas Instruments Beaglebone (`beaglebone-yocto`)
29 * General 64-bit Arm SystemReady platforms (`genericarm64`)
30 * General IA platforms (`genericx86` and `genericx86-64`)
38 Please refer to our contributor guide here: https://docs.yoctoproject.org/dev/contributor-guide/
44 git send-email -M -1 --to poky@lists.yoctoproject.org
46 Send pull requests, patches, comments or questions about meta-yocto-bsp to
56 The following consumer devices are supported by the meta-yocto-bsp layer:
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/openbmc/openbmc/poky/
H A DREADME.hardware.md15 (BSP) Developer's Guide - documentation source is in documentation/bspguide or
18 Note that these reference BSPs use the linux-yocto kernel and in general don't
26 The following boards are supported by the meta-yocto-bsp layer:
28 * Texas Instruments Beaglebone (`beaglebone-yocto`)
29 * General 64-bit Arm SystemReady platforms (`genericarm64`)
30 * General IA platforms (`genericx86` and `genericx86-64`)
38 Please refer to our contributor guide here: https://docs.yoctoproject.org/dev/contributor-guide/
44 git send-email -M -1 --to poky@lists.yoctoproject.org
46 Send pull requests, patches, comments or questions about meta-yocto-bsp to
56 The following consumer devices are supported by the meta-yocto-bsp layer:
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