Searched full:clocking (Results 1 – 25 of 49) sorted by relevance
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176 * R512 (0x200) - AIF1 Clocking (1)187 * R517 (0x205) - AIF2 Clocking (2)193 * R520 (0x208) - Clocking (1)208 * R521 (0x209) - Clocking (2)
13 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
15 - spi-max-frequency: Maximum SPI clocking speed of device in Hz.
49 - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
28 * Mali clocking is provided by two identical clock paths
36 clockgen: clocking@1ee1000 {
28 clockgen: clocking@1300000 {
246 * Mali clocking is provided by two identical clock paths679 * VPU clocking is provided by two identical clock paths
40 clockgen: clocking@1ee1000 {
62 * line actually used for clocking all external PCI devices in TQM83xx. in pci_init_board()
83 * we can tell the clocking required by looking at the SOC sku_id, but
13 * Describes the physical PCM data formating and clocking. Add new formats
63 Following are the defines for PLL's index that provide the Clocking to
60 /* Clocking from MSI, in case MSI was not the default source */ in test_set_msi_as_sysclk()
115 The third option builds PCI support in, and leaves the clocking at the
47 * clocking SPI after reset. The exact clock speed is not strictly,
50 - Single source clocking implementation
14 /* Clocking and Power Control Registers */
4 IP block. The IP supports multiple options for bus type, clocking and reset
4 omap1_pwl_clocking_scheme(const char *scheme) "omap1 CLKM: clocking scheme set to %s"
31 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
279 /* Clocking */
39 The third option builds PCI support in, and leaves the clocking at the
100 clocking/reset structure, and feature list. This driver currently