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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,clocking-wizard.yaml4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
7 title: Xilinx clocking wizard
13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0
69 compatible = "xlnx,clocking-wizard";
H A Dmediatek,mt8186-fhctl.yaml7 title: MediaTek frequency hopping and spread spectrum clocking control
15 Spread spectrum clocking (SSC) is another function provided by this hardware.
35 description: The percentage of spread spectrum clocking for one PLL.
/openbmc/linux/drivers/clk/xilinx/
H A DKconfig21 tristate "Xilinx Clocking Wizard"
25 Support for the Xilinx Clocking Wizard IP core clock generator.
26 Adds support for clocking wizard and compatible.
27 This driver supports the Xilinx clocking wizard programmable clock
/openbmc/linux/include/media/i2c/
H A Dupd64083.h28 /* YCS mode: Y/C separation (burst locked clocking) */
30 /* YCS+ mode: 2D Y/C separation and YCNR (burst locked clocking) */
35 /* MNNR mode: frame comb type YNR+C delay (line locked clocking) */
37 /* YCNR mode: frame recursive YCNR (burst locked clocking) */
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt45 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
47 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
61 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
63 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
65 - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
/openbmc/linux/Documentation/sound/soc/
H A Dclocking.rst2 Audio Clocking
5 This text describes the audio clocking terms in ASoC and digital audio in
6 general. Note: Audio clocking can be complex!
H A Dindex.rst17 clocking
/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dclock.json7 "PublicDescription": "FSU clocking gated off cycle",
10 "BriefDescription": "FSU clocking gated off cycle"
/openbmc/linux/drivers/ata/
H A Dpata_ns87415.c59 u16 clocking; in ns87415_set_mode() local
68 clocking = 17 - clamp_val(t.active, 2, 17); in ns87415_set_mode()
69 clocking |= (16 - clamp_val(t.recover, 1, 16)) << 4; in ns87415_set_mode()
71 clocking |= (clocking << 8); in ns87415_set_mode()
72 pci_write_config_word(dev, timing, clocking); in ns87415_set_mode()
331 /* Select PIO0 8bit clocking */ in ns87415_fixup()
/openbmc/u-boot/drivers/sound/
H A Dwm8994_registers.h176 * R512 (0x200) - AIF1 Clocking (1)
187 * R517 (0x205) - AIF2 Clocking (2)
193 * R520 (0x208) - Clocking (1)
208 * R521 (0x209) - Clocking (2)
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mpc.yaml38 fsl,preserve-clocking:
86 fsl,preserve-clocking;
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dintel,ixp4xx-hss.yaml105 use internal clocking as opposed to external clocking
/openbmc/linux/Documentation/admin-guide/pm/
H A Dcpufreq_drivers.rst94 Processor Clocking Control Driver
113 Processor Clocking Control (PCC) is an interface between the platform
129 https://acpica.org/sites/acpica/files/Processor-Clocking-Control-v1p0.pdf
184 * assumes responsibility for managing the hardware clocking controls in order
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-audio.yaml23 Clocking setup for j721e:
32 Clocking setup for j7200:
H A Dti,j721e-cpb-ivi-audio.yaml30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
/openbmc/linux/arch/powerpc/boot/dts/
H A Dpdm360ng.dts94 fsl,preserve-clocking;
112 fsl,preserve-clocking;
/openbmc/linux/sound/soc/codecs/
H A Dcs35l35.h24 #define CS35L35_CLK_CTL1 0x0A /* Clocking Ctl 1 */
25 #define CS35L35_CLK_CTL2 0x0B /* Clocking Ctl 2 */
26 #define CS35L35_CLK_CTL3 0x0C /* Clocking Ctl 3 */
H A Dcs42l73.h28 #define CS42L73_XSPMMCC 0x0D /* XSP Master Mode Clocking Control. */
30 #define CS42L73_ASPMMCC 0x0F /* ASP Master Mode Clocking Control. */
32 #define CS42L73_VSPMMCC 0x11 /* VSP Master Mode Clocking Control. */
H A Dwm8737.c55 { 8, 0x0000 }, /* R8 - Clocking */
331 u16 clocking = 0; in wm8737_hw_params() local
342 clocking |= WM8737_CLKDIV2; in wm8737_hw_params()
353 clocking |= coeff_div[i].usb | (coeff_div[i].sr << WM8737_SR_SHIFT); in wm8737_hw_params()
374 clocking); in wm8737_hw_params()
/openbmc/linux/drivers/mfd/
H A Dwm8994-regmap.c73 { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
74 { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
75 { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
76 { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
77 { 0x0208, 0x0000 }, /* R520 - Clocking (1) */
78 { 0x0209, 0x0000 }, /* R521 - Clocking (2) */
302 { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
303 { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
304 { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
305 { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Darm,mps2-uart.txt8 Required clocking property:
/openbmc/linux/drivers/fsi/
H A Dcf-fsi-fw.h36 #define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */
42 #define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */
/openbmc/linux/include/dt-bindings/clock/
H A Dlochnagar.h3 * Device Tree defines for Lochnagar clocking
/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Dlwn-bk4.txt17 - spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,mps2-timer.txt10 Required clocking property, have to be one of:

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