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/openbmc/qemu/hw/ssi/
H A Dtrace-events3 …peed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PR…
4 aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" P…
5 aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x"
6 aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" …
7 aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
8 aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
9 …t flash_addr, uint64_t dram_addr, uint32_t size) "%s flash:@0x%08x dram:@0x%" PRIx64 " size:0x%08x"
10 aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
11 aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
18 npcm7xx_fiu_select(const char *id, int cs) "%s select CS%d"
[all …]
/openbmc/qemu/target/microblaze/
H A Dhelper.c5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
23 #include "exec/exec-all.h"
24 #include "exec/page-protection.h"
25 #include "qemu/host-utils.h"
33 return !cpu->ns_axi_ip; in mb_cpu_access_is_secure()
35 return !cpu->ns_axi_dp; in mb_cpu_access_is_secure()
39 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, in mb_cpu_tlb_fill() argument
43 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); in mb_cpu_tlb_fill()
44 CPUMBState *env = &cpu->env; in mb_cpu_tlb_fill()
56 tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, in mb_cpu_tlb_fill()
[all …]
/openbmc/linux/drivers/memory/
H A Dti-aemif.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
8 * Murali Karicheri <m-karicheri2@ti.com>
20 #include <linux/platform_data/ti-aemif.h>
32 #define TA(x) ((x) << TA_SHIFT) argument
33 #define RHOLD(x) ((x) << RHOLD_SHIFT) argument
34 #define RSTROBE(x) ((x) << RSTROBE_SHIFT) argument
35 #define RSETUP(x) ((x) << RSETUP_SHIFT) argument
36 #define WHOLD(x) ((x) << WHOLD_SHIFT) argument
37 #define WSTROBE(x) ((x) << WSTROBE_SHIFT) argument
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_lrc.c1 // SPDX-License-Identifier: MIT
26 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
35 return __vm_create_scratch_for_read_pinned(&gt->ggtt->vm, PAGE_SIZE); in create_scratch()
57 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
68 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
72 return -ETIME; in wait_for_submit()
81 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
84 u32 *cs; in emit_semaphore_signal() local
90 cs = intel_ring_begin(rq, 4); in emit_semaphore_signal()
91 if (IS_ERR(cs)) { in emit_semaphore_signal()
[all …]
H A Dselftest_workarounds.c1 // SPDX-License-Identifier: MIT
42 err = -EIO; in request_add_sync()
55 err = -ETIMEDOUT; in request_add_spin()
69 wa_init_start(&lists->gt_wa_list, gt, "GT_REF", "global"); in reference_lists_init()
70 gt_init_workarounds(gt, &lists->gt_wa_list); in reference_lists_init()
71 wa_init_finish(&lists->gt_wa_list); in reference_lists_init()
74 struct i915_wa_list *wal = &lists->engine[id].wa_list; in reference_lists_init()
76 wa_init_start(wal, gt, "REF", engine->name); in reference_lists_init()
81 &lists->engine[id].ctx_wa_list, in reference_lists_init()
93 intel_wa_list_free(&lists->engine[id].wa_list); in reference_lists_fini()
[all …]
H A Dintel_lrc.c1 // SPDX-License-Identifier: MIT
24 * The per-platform tables are u8-encoded in @data. Decode @data and set the
29 * [7]: create NOPs - number of NOPs are set in lower bits
51 #define NOP(x) (BIT(7) | (x)) in set_offsets() argument
54 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets() argument
55 #define REG16(x) \ in set_offsets() argument
56 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
57 (((x) >> 2) & 0x7f) in set_offsets()
60 const u32 base = engine->mmio_base; in set_offsets()
78 if (GRAPHICS_VER(engine->i915) >= 11) in set_offsets()
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H A Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
25 return *a - *b; in cmp_u64()
34 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
36 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
40 *cs++ = value; in emit_wait()
41 *cs++ = offset; in emit_wait()
42 *cs++ = 0; in emit_wait()
44 return cs; in emit_wait()
47 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
49 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; in emit_store()
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
16 * regs has the to-be-set values for DDR controller registers
36 int csn = -1; in fsl_ddr_set_memctl_regs()
69 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
70 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
74 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; in fsl_ddr_set_memctl_regs()
75 cs_ea = regs->cs[i].bnds & 0xfff; in fsl_ddr_set_memctl_regs()
78 csn_bnds_backup = regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
79 csn_bnds_t = (unsigned int *) &regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dfsl_espi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
42 #define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ argument
43 #define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ argument
45 #define ESPI_COM_CS(x) ((x) << 30) argument
46 #define ESPI_COM_TRANLEN(x) ((x) << 0) argument
52 #define ESPI_CSMODE_PM(x) ((x) << 24) argument
54 #define ESPI_CSMODE_LEN(x) ((x) << 16) argument
55 #define ESPI_CSMODE_CSBEF(x) ((x) << 12) argument
56 #define ESPI_CSMODE_CSAFT(x) ((x) << 8) argument
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H A Daspeed_spi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2015-2018, IBM Corporation.
32 u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */
113 /* Auto Soft-Reset Command Control */
121 * CE0 0x20000000 - 0x2fffffff 128MB
122 * CE1 0x28000000 - 0x29ffffff 32MB
123 * CE2 0x2a000000 - 0x2bffffff 32MB
126 * covered and CE0 start address and CE2 end addresses are read-only.
136 ((((start) & 0x0ff00000) >> 16) | (((end) - 0x100000) & 0xffff0000))
171 u8 cs; member
[all …]
H A Dmxc_spi.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
15 #include <asm/mach-imx/spi.h>
27 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) in board_spi_cs_gpio() argument
29 return -1; in board_spi_cs_gpio()
63 dm_gpio_set_value(&mxcs->ss, 1); in mxc_spi_cs_activate()
65 if (mxcs->gpio > 0) in mxc_spi_cs_activate()
66 gpio_set_value(mxcs->gpio, mxcs->ss_pol); in mxc_spi_cs_activate()
73 dm_gpio_set_value(&mxcs->ss, 0); in mxc_spi_cs_deactivate()
75 if (mxcs->gpio > 0) in mxc_spi_cs_deactivate()
[all …]
/openbmc/linux/drivers/net/slip/
H A Dslhc.c21 * - Initial distribution.
28 * - 01-31-90 initial adaptation (from 1.19)
29 * PPP.05 02-15-90 [ks]
30 * PPP.08 05-02-90 [ks] use PPP protocol field to signal compression
31 * PPP.15 09-90 [ks] improve mbuf handling
32 * PPP.16 11-02 [karn] substantially rewritten to use NOS facilities
34 * - Feb 1991 Bill_Simpson@um.cc.umich.edu
39 * - Jul 1994 Dmitry Gorodchanin
41 * - Oct 1994 Dmitry Gorodchanin
43 * - Jan 1995 Bjorn Ekwall
[all …]
/openbmc/qemu/target/avr/
H A Dcpu.c4 * Copyright (c) 2019-2020 Michael Rolnik
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
23 #include "qemu/qemu-print.h"
24 #include "exec/exec-all.h"
26 #include "disas/dis-asm.h"
27 #include "tcg/debug-assert.h"
28 #include "hw/qdev-properties.h"
30 static void avr_cpu_set_pc(CPUState *cs, vaddr value) in avr_cpu_set_pc() argument
32 AVRCPU *cpu = AVR_CPU(cs); in avr_cpu_set_pc()
34 cpu->env.pc_w = value / 2; /* internally PC points to words */ in avr_cpu_set_pc()
[all …]
/openbmc/qemu/target/xtensa/
H A Dexc_helper.c2 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.
30 #include "qemu/main-loop.h"
32 #include "exec/helper-proto.h"
33 #include "qemu/host-utils.h"
35 #include "exec/exec-all.h"
39 CPUState *cs = env_cpu(env); in HELPER() local
41 cs->exception_index = excp; in HELPER()
43 env->yield_needed = 0; in HELPER()
45 cpu_loop_exit(cs); in HELPER()
52 env->pc = pc; in HELPER()
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/openbmc/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_client_blt.c1 // SPDX-License-Identifier: MIT
30 static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) in linear_x_y_to_ftiled_pos() argument
53 x *= pixel_size; in linear_x_y_to_ftiled_pos()
56 * F so we can use the Y-tile algorithm to get to that point. in linear_x_y_to_ftiled_pos()
60 x / F_TILE_WIDTH * 4096; in linear_x_y_to_ftiled_pos()
63 tile_x = x % F_TILE_WIDTH; in linear_x_y_to_ftiled_pos()
115 /* XY_FAST_COPY_BLT does not exist on pre-gen9 platforms */ in fastblit_supports_x_tiling()
116 drm_WARN_ON(&i915->drm, gen < 9); in fastblit_supports_x_tiling()
129 /* XY_FAST_COPY_BLT does not exist on pre-gen9 platforms */ in fast_blit_ok()
130 if (GRAPHICS_VER(buf->vma->vm->i915) < 9) in fast_blit_ok()
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-aspeed-smc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2015-2022, IBM Corporation.
15 #include <linux/spi/spi-mem.h>
17 #define DEVICE_NAME "spi-aspeed-smc"
64 u32 cs; member
108 switch (op->data.buswidth) { in aspeed_spi_get_io_mode()
125 ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK; in aspeed_spi_set_io_mode()
127 writel(ctl, chip->ctl); in aspeed_spi_set_io_mode()
133 u32 ctl = chip->ctl_val[ASPEED_SPI_BASE]; in aspeed_spi_start_user()
136 writel(ctl, chip->ctl); in aspeed_spi_start_user()
[all …]
H A Dspi-fsl-espi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) argument
36 #define SPMODE_TXTHR(x) ((x) << 8) argument
37 #define SPMODE_RXTHR(x) ((x) << 0) argument
39 /* eSPI Controller CS mode register definitions */
44 #define CSMODE_PM(x) ((x) << 24) argument
46 #define CSMODE_LEN(x) ((x) << 16) argument
47 #define CSMODE_BEF(x) ((x) << 12) argument
48 #define CSMODE_AFT(x) ((x) << 8) argument
49 #define CSMODE_CG(x) ((x) << 3) argument
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Drenesas-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Evatronix/Renesas R-Car Gen3, RZ/N1D, RZ/N1S, RZ/N1L NAND controller driver
11 #include <linux/dma-mapping.h>
23 #define COMMAND_SEQ(x) FIELD_PREP(GENMASK(5, 0), (x)) argument
36 #define COMMAND_0(x) FIELD_PREP(GENMASK(15, 8), (x)) argument
37 #define COMMAND_1(x) FIELD_PREP(GENMASK(23, 16), (x)) argument
38 #define COMMAND_2(x) FIELD_PREP(GENMASK(31, 24), (x)) argument
42 #define CONTROL_ECC_BLOCK_SIZE(x) FIELD_PREP(GENMASK(2, 1), (x)) argument
48 #define CONTROL_BLOCK_SIZE(x) FIELD_PREP(GENMASK(7, 6), (x)) argument
55 #define MEM_RDY(cs, reg) (FIELD_GET(GENMASK(3, 0), (reg)) & BIT(cs)) argument
[all …]
/openbmc/linux/include/linux/mfd/syscon/
H A Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]
/openbmc/qemu/monitor/
H A Dhmp-cmds-target.c2 * Miscellaneous target-dependent HMP commands
4 * Copyright (c) 2003-2004 Fabrice Bellard
27 #include "exec/address-spaces.h"
29 #include "monitor/hmp-target.h"
30 #include "monitor/monitor-internal.h"
42 return -1; in monitor_set_cpu()
44 g_free(mon->mon_cpu_path); in monitor_set_cpu()
45 mon->mon_cpu_path = object_get_canonical_path(OBJECT(cpu)); in monitor_set_cpu()
54 if (mon->mon_cpu_path) { in mon_get_cpu_sync()
55 cpu = (CPUState *) object_resolve_path_type(mon->mon_cpu_path, in mon_get_cpu_sync()
[all …]
/openbmc/linux/drivers/scsi/
H A Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
[all …]
/openbmc/qemu/linux-user/ppc/
H A Dcpu_loop.c4 * Copyright (c) 2003-2008 Fabrice Bellard
23 #include "user-internals.h"
24 #include "cpu_loop-common.h"
25 #include "signal-common.h"
60 return -1; in ppc_dcr_read()
65 return -1; in ppc_dcr_write()
70 CPUState *cs = env_cpu(env); in cpu_loop() local
77 cpu_exec_start(cs); in cpu_loop()
78 trapnr = cpu_exec(cs); in cpu_loop()
79 cpu_exec_end(cs); in cpu_loop()
[all …]
/openbmc/qemu/semihosting/
H A Dsyscalls.c6 * SPDX-License-Identifier: GPL-2.0-or-later
25 static int validate_strlen(CPUState *cs, target_ulong str, target_ulong tlen) in validate_strlen() argument
27 CPUArchState *env G_GNUC_UNUSED = cpu_env(cs); in validate_strlen()
34 return -EFAULT; in validate_strlen()
37 return -ENAMETOOLONG; in validate_strlen()
42 return -ENAMETOOLONG; in validate_strlen()
44 if (get_user_u8(c, str + tlen - 1)) { in validate_strlen()
45 return -EFAULT; in validate_strlen()
48 return -EINVAL; in validate_strlen()
53 static int validate_lock_user_string(char **pstr, CPUState *cs, in validate_lock_user_string() argument
[all …]
/openbmc/qemu/linux-user/aarch64/
H A Dcpu_loop.c4 * Copyright (c) 2003-2008 Fabrice Bellard
22 #include "user-internals.h"
23 #include "cpu_loop-common.h"
24 #include "signal-common.h"
25 #include "qemu/guest-random.h"
26 #include "semihosting/common-semi.h"
28 #include "target/arm/cpu-features.h"
30 #define get_user_code_u32(x, gaddr, env) \ argument
31 ({ abi_long __r = get_user_u32((x), (gaddr)); \
33 (x) = bswap32(x); \
[all …]
/openbmc/qemu/linux-user/
H A Dvm86.c22 #include "user-internals.h"
33 #define set_flags(X,new,mask) \ argument
34 ((X) = ((X) & ~(mask)) | ((new) & (mask)))
52 CPUState *cs = env_cpu(env); in save_v86_state() local
53 TaskState *ts = get_task_state(cs); in save_v86_state()
56 if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0)) in save_v86_state()
57 /* FIXME - should return an error */ in save_v86_state()
60 target_v86->regs.eax = tswap32(env->regs[R_EAX]); in save_v86_state()
61 target_v86->regs.ebx = tswap32(env->regs[R_EBX]); in save_v86_state()
62 target_v86->regs.ecx = tswap32(env->regs[R_ECX]); in save_v86_state()
[all …]

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