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/openbmc/qemu/target/i386/tcg/sysemu/
H A Dsmm_helper.c2 * x86 SMM helpers (sysemu-only)
22 #include "exec/helper-proto.h"
24 #include "tcg/helper-tcg.h"
30 #define SMM_REVISION_ID 0x00020064
32 #define SMM_REVISION_ID 0x00020000
37 CPUX86State *env = &cpu->env; in do_smm_enter()
38 CPUState *cs = CPU(cpu); in do_smm_enter() local
46 env->msr_smi_count++; in do_smm_enter()
47 env->hflags |= HF_SMM_MASK; in do_smm_enter()
48 if (env->hflags2 & HF2_NMI_MASK) { in do_smm_enter()
[all …]
H A Dsvm_helper.c23 #include "exec/helper-proto.h"
24 #include "exec/exec-all.h"
26 #include "tcg/helper-tcg.h"
34 sc->selector, mmu_idx, 0); in svm_save_seg()
36 sc->base, mmu_idx, 0); in svm_save_seg()
38 sc->limit, mmu_idx, 0); in svm_save_seg()
40 ((sc->flags >> 8) & 0xff) in svm_save_seg()
41 | ((sc->flags >> 12) & 0x0f00), in svm_save_seg()
42 mmu_idx, 0); in svm_save_seg()
46 * VMRUN and VMLOAD canonicalizes (i.e., sign-extend to bit 63) all base
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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dgen8_engine_cs.c1 // SPDX-License-Identifier: MIT
16 u32 *cs, flags = 0; in gen8_emit_flush_rcs() local
42 if (GRAPHICS_VER(rq->i915) == 9) in gen8_emit_flush_rcs()
46 if (IS_KABYLAKE(rq->i915) && IS_GRAPHICS_STEP(rq->i915, 0, STEP_C0)) in gen8_emit_flush_rcs()
58 cs = intel_ring_begin(rq, len); in gen8_emit_flush_rcs()
59 if (IS_ERR(cs)) in gen8_emit_flush_rcs()
60 return PTR_ERR(cs); in gen8_emit_flush_rcs()
63 cs = gen8_emit_pipe_control(cs, 0, 0); in gen8_emit_flush_rcs()
66 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, in gen8_emit_flush_rcs()
67 0); in gen8_emit_flush_rcs()
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H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
25 * 0.
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
[all …]
H A Dgen7_renderclear.c1 // SPDX-License-Identifier: MIT
11 #define GT3_INLINE_DATA_DELAYS 0x1E00
12 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
48 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
52 return bv->max_threads; in num_primitives()
59 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
62 bv->max_threads = 70; in batch_get_defaults()
65 bv->max_threads = 140; in batch_get_defaults()
68 bv->max_threads = 280; in batch_get_defaults()
71 bv->surface_height = 16 * 16; in batch_get_defaults()
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H A Dgen2_engine_cs.c1 // SPDX-License-Identifier: MIT
19 u32 cmd, *cs; in gen2_emit_flush() local
25 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
26 if (IS_ERR(cs)) in gen2_emit_flush()
27 return PTR_ERR(cs); in gen2_emit_flush()
29 *cs++ = cmd; in gen2_emit_flush()
30 while (num_store_dw--) { in gen2_emit_flush()
31 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
32 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
33 *cs++ = 0; in gen2_emit_flush()
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/openbmc/qemu/target/loongarch/kvm/
H A Dkvm.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #include "qemu/error-report.h"
15 #include "qemu/main-loop.h"
21 #include "exec/address-spaces.h"
27 #include "cpu-csr.h"
37 static int kvm_get_stealtime(CPUState *cs) in kvm_get_stealtime() argument
39 CPULoongArchState *env = cpu_env(cs); in kvm_get_stealtime()
44 .addr = (uint64_t)&env->stealtime.guest_addr, in kvm_get_stealtime()
47 err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); in kvm_get_stealtime()
49 return 0; in kvm_get_stealtime()
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/openbmc/qemu/semihosting/
H A Dsyscalls.c6 * SPDX-License-Identifier: GPL-2.0-or-later
25 static int validate_strlen(CPUState *cs, target_ulong str, target_ulong tlen) in validate_strlen() argument
27 CPUArchState *env G_GNUC_UNUSED = cpu_env(cs); in validate_strlen()
30 if (tlen == 0) { in validate_strlen()
33 if (slen < 0) { in validate_strlen()
34 return -EFAULT; in validate_strlen()
37 return -ENAMETOOLONG; in validate_strlen()
42 return -ENAMETOOLONG; in validate_strlen()
44 if (get_user_u8(c, str + tlen - 1)) { in validate_strlen()
45 return -EFAULT; in validate_strlen()
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H A Darm-compat-semi.c3 * semihosting syscalls design. This includes Arm and RISC-V processors
10 * Adapted for systems other than ARM, including RISC-V, by Keith Packard
27 * https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst
29 * RISC-V Semihosting is documented in:
30 * RISC-V Semihosting
31 * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
40 #include "semihosting/common-semi.h"
54 #define TARGET_SYS_OPEN 0x01
55 #define TARGET_SYS_CLOSE 0x02
56 #define TARGET_SYS_WRITEC 0x03
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c1 // SPDX-License-Identifier: GPL-2.0
43 #define WL_SUP_EXPECTED_DATA 0x21
44 #define WL_SUP_READ_DRAM_ENTRY 0x8
46 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
59 * Args: freq - current sequence frequency
60 * dram_info - main struct
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
68 int dpde_flag = 0; in ddr3_write_leveling_hw()
70 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
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H A Dddr3_read_leveling.c1 // SPDX-License-Identifier: GPL-2.0
44 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
48 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
56 * Args: dram_info - main struct
57 * freq - current sequence frequency
65 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
73 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
[all …]
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c18 #include "qemu/main-loop.h"
24 #include "target/arm/cpu-features.h"
36 return env->gicv3state; in icc_cs_from_env()
50 static inline int icv_min_vbpr(GICv3CPUState *cs) in icv_min_vbpr() argument
52 return 7 - cs->vprebits; in icv_min_vbpr()
55 static inline int ich_num_aprs(GICv3CPUState *cs) in ich_num_aprs() argument
58 int aprmax = 1 << (cs->vprebits - 5); in ich_num_aprs()
59 assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); in ich_num_aprs()
94 * all ICV regs with '0' in their name in icv_access()
107 static int read_vbpr(GICv3CPUState *cs, int grp) in read_vbpr() argument
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H A Darm_gicv3_redist.c17 static uint32_t mask_group(GICv3CPUState *cs, MemTxAttrs attrs) in mask_group() argument
19 /* Return a 32-bit mask which should be applied for this set of 32 in mask_group()
24 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in mask_group()
25 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI */ in mask_group()
26 return cs->gicr_igroupr0; in mask_group()
28 return 0xFFFFFFFFU; in mask_group()
31 static int gicr_ns_access(GICv3CPUState *cs, int irq) in gicr_ns_access() argument
35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
38 static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, in gicr_write_bitmap_reg() argument
42 val &= mask_group(cs, attrs); in gicr_write_bitmap_reg()
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H A Darm_gicv3.c24 static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool nmi) in irqbetter() argument
33 if (prio != cs->hppi.prio) { in irqbetter()
34 return prio < cs->hppi.prio; in irqbetter()
38 * The same priority IRQ with non-maskable property should signal to in irqbetter()
39 * the CPU as it have the priority higher than the labelled 0x80 or 0x00. in irqbetter()
41 if (nmi != cs->hppi.nmi) { in irqbetter()
49 if (irq <= cs->hppi.irq) { in irqbetter()
59 * of 32), and return a 32-bit integer which has a bit set for each in gicd_int_pending()
67 * Conveniently we can bulk-calculate this with bitwise operations. in gicd_int_pending()
70 uint32_t pending = *gic_bmp_ptr32(s->pending, irq); in gicd_int_pending()
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/openbmc/linux/drivers/scsi/
H A Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
52 for (i = 0; i < ARRAY_SIZE(myrs_devstate_name_list); i++) { in myrs_devstate_name()
83 for (i = 0; i < ARRAY_SIZE(myrs_raid_level_name_list); i++) { in myrs_raid_level_name()
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
97 memset(mbox, 0, sizeof(union myrs_cmd_mbox)); in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
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/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
9 #define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
10 #define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
11 #define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
12 #define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
13 #define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
14 #define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
15 #define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
16 #define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
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/openbmc/linux/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
23 static noinline u64 cycles_to_nsec_safe(struct clocksource *cs, u64 start, u64 end) in cycles_to_nsec_safe() argument
25 u64 delta = clocksource_delta(end, start, cs->mask); in cycles_to_nsec_safe()
27 if (likely(delta < cs->max_cycles)) in cycles_to_nsec_safe()
28 return clocksource_cyc2ns(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
30 return mul_u64_u32_shr(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
34 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
69 sftacc--; in clocks_calc_mult_shift()
76 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
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/openbmc/qemu/target/mips/
H A Dkvm.c8 * Copyright (C) 2012-2014 Imagination Technologies Ltd.
19 #include "qemu/error-report.h"
20 #include "qemu/main-loop.h"
28 #define DEBUG_KVM 0
31 do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
42 unsigned long kvm_arch_vcpu_id(CPUState *cs) in kvm_arch_vcpu_id() argument
44 return cs->cpu_index; in kvm_arch_vcpu_id()
56 return 0; in kvm_arch_init()
61 return 0; in kvm_arch_irqchip_create()
64 int kvm_arch_init_vcpu(CPUState *cs) in kvm_arch_init_vcpu() argument
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/openbmc/linux/drivers/memory/
H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
18 #define FMC2_BCR1 0x0
19 #define FMC2_BTR1 0x4
20 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
21 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
22 #define FMC2_PCSCNTR 0x20
23 #define FMC2_BWTR1 0x104
24 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
31 #define FMC2_BCR_MBKEN BIT(0)
48 #define FMC2_BXTR_ADDSET GENMASK(3, 0)
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/openbmc/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_cmd.c1 // SPDX-License-Identifier: MIT
23 static u32 *pxp_emit_session_selection(u32 *cs, u32 idx) in pxp_emit_session_selection() argument
25 *cs++ = MFX_WAIT_PXP; in pxp_emit_session_selection()
28 *cs++ = MI_FLUSH_DW; in pxp_emit_session_selection()
29 *cs++ = 0; in pxp_emit_session_selection()
30 *cs++ = 0; in pxp_emit_session_selection()
33 *cs++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx); in pxp_emit_session_selection()
35 *cs++ = MFX_WAIT_PXP; in pxp_emit_session_selection()
38 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_PROTECTED_MEM_EN | in pxp_emit_session_selection()
40 *cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT; in pxp_emit_session_selection()
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/openbmc/qemu/target/i386/hvf/
H A Dx86hvf.c2 * Copyright (c) 2003-2008 Fabrice Bellard
35 void hvf_set_segment(CPUState *cs, struct vmx_segment *vmx_seg, in hvf_set_segment() argument
38 vmx_seg->sel = qseg->selector; in hvf_set_segment()
39 vmx_seg->base = qseg->base; in hvf_set_segment()
40 vmx_seg->limit = qseg->limit; in hvf_set_segment()
42 if (!qseg->selector && !x86_is_real(cs) && !is_tr) { in hvf_set_segment()
45 vmx_seg->ar = 1 << 16; in hvf_set_segment()
48 vmx_seg->ar = (qseg->flags >> DESC_TYPE_SHIFT) & 0xf; in hvf_set_segment()
49 vmx_seg->ar |= ((qseg->flags >> DESC_G_SHIFT) & 1) << 15; in hvf_set_segment()
50 vmx_seg->ar |= ((qseg->flags >> DESC_B_SHIFT) & 1) << 14; in hvf_set_segment()
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/openbmc/linux/drivers/accel/habanalabs/common/
H A Dcommand_submission.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2021 HabanaLabs, Ltd.
23 * enum hl_cs_wait_status - cs wait status
24 * @CS_WAIT_STATUS_BUSY: cs was not completed yet
25 * @CS_WAIT_STATUS_COMPLETED: cs completed
26 * @CS_WAIT_STATUS_GONE: cs completed but fence is already gone
47 * CS outcome store supports the following operations: in hl_push_cs_outcome()
48 * push outcome - store a recent CS outcome in the store in hl_push_cs_outcome()
49 * pop outcome - retrieve a SPECIFIC (by seq) CS outcome from the store in hl_push_cs_outcome()
51 * It has a pre-allocated amount of nodes, each node stores in hl_push_cs_outcome()
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/openbmc/qemu/target/s390x/
H A Dgdbstub.c4 * Copyright (c) 2003-2005 Fabrice Bellard
23 #include "s390x-internal.h"
24 #include "exec/exec-all.h"
31 int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) in s390_cpu_gdb_read_register() argument
33 CPUS390XState *env = cpu_env(cs); in s390_cpu_gdb_read_register()
39 return gdb_get_regl(mem_buf, env->psw.addr); in s390_cpu_gdb_read_register()
41 return gdb_get_regl(mem_buf, env->regs[n - S390_R0_REGNUM]); in s390_cpu_gdb_read_register()
43 return 0; in s390_cpu_gdb_read_register()
46 int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) in s390_cpu_gdb_write_register() argument
48 CPUS390XState *env = cpu_env(cs); in s390_cpu_gdb_write_register()
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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/openbmc/qemu/target/i386/kvm/
H A Dxen-emu.c8 * See the COPYING file in the top-level directory.
14 #include "qemu/main-loop.h"
15 #include "qemu/error-report.h"
20 #include "exec/address-spaces.h"
21 #include "xen-emu.h"
26 #include "hw/i386/apic-msidef.h"
43 #include "xen-compat.h"
47 static int vcpuop_stop_singleshot_timer(CPUState *cs);
55 static bool kvm_gva_to_gpa(CPUState *cs, uint64_t gva, uint64_t *gpa, in kvm_gva_to_gpa() argument
63 *len = TARGET_PAGE_SIZE - (gva & ~TARGET_PAGE_MASK); in kvm_gva_to_gpa()
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