Lines Matching +full:cs +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
44 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
48 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
56 * Args: dram_info - main struct
57 * freq - current sequence frequency
65 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
73 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
86 } while (reg); /* Wait for '0' */ in ddr3_read_leveling_hw()
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
93 dram_info->rl_max_phase = 0; in ddr3_read_leveling_hw()
94 dram_info->rl_min_phase = 10; in ddr3_read_leveling_hw()
97 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
98 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
99 for (pup = 0; in ddr3_read_leveling_hw()
100 pup < dram_info->num_of_total_pups; in ddr3_read_leveling_hw()
102 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
103 && dram_info->ecc_ena) in ddr3_read_leveling_hw()
106 ddr3_read_pup_reg(PUP_RL_MODE, cs, in ddr3_read_leveling_hw()
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
112 if (phase > dram_info->rl_max_phase) in ddr3_read_leveling_hw()
113 dram_info->rl_max_phase = phase; in ddr3_read_leveling_hw()
114 if (phase < dram_info->rl_min_phase) in ddr3_read_leveling_hw()
115 dram_info->rl_min_phase = phase; in ddr3_read_leveling_hw()
116 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
120 ddr3_read_pup_reg(PUP_RL_MODE + 0x1, in ddr3_read_leveling_hw()
121 cs, pup); in ddr3_read_leveling_hw()
122 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
123 (reg & 0x3F); in ddr3_read_leveling_hw()
127 DEBUG_RL_C("DDR3 - Read Leveling - Results for CS - ", in ddr3_read_leveling_hw()
128 (u32) cs, 1); in ddr3_read_leveling_hw()
130 for (pup = 0; in ddr3_read_leveling_hw()
131 pup < (dram_info->num_of_total_pups); in ddr3_read_leveling_hw()
133 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
134 && dram_info->ecc_ena) in ddr3_read_leveling_hw()
136 DEBUG_RL_S("DDR3 - Read Leveling - PUP: "); in ddr3_read_leveling_hw()
139 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw()
140 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
142 DEBUG_RL_D((u32) dram_info-> in ddr3_read_leveling_hw()
143 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
150 dram_info->rd_rdy_dly = in ddr3_read_leveling_hw()
153 dram_info->rd_smpl_dly = in ddr3_read_leveling_hw()
157 DEBUG_RL_C("DDR3 - Read Leveling - Read Sample Delay: ", in ddr3_read_leveling_hw()
158 dram_info->rd_smpl_dly, 2); in ddr3_read_leveling_hw()
159 DEBUG_RL_C("DDR3 - Read Leveling - Read Ready Delay: ", in ddr3_read_leveling_hw()
160 dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_hw()
161 DEBUG_RL_S("DDR3 - Read Leveling - HW RL Ended Successfully\n"); in ddr3_read_leveling_hw()
166 DEBUG_RL_S("DDR3 - Read Leveling - HW RL Error\n"); in ddr3_read_leveling_hw()
174 * Args: dram_info - main struct
175 * freq - current sequence frequency
181 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
184 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_sw()
185 DEBUG_RL_S("DDR3 - Read Leveling - Starting SW RL procedure\n"); in ddr3_read_leveling_sw()
191 /* [0]=1 - Enable SW override */ in ddr3_read_leveling_sw()
192 /* 0x15B8 - Training SW 2 Register */ in ddr3_read_leveling_sw()
196 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_read_leveling_sw()
198 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_sw()
201 /* Loop for each CS */ in ddr3_read_leveling_sw()
202 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_sw()
203 DEBUG_RL_C("DDR3 - Read Leveling - CS - ", (u32) cs, 1); in ddr3_read_leveling_sw()
205 for (ecc = 0; ecc <= (dram_info->ecc_ena); ecc++) { in ddr3_read_leveling_sw()
206 /* ECC Support - Switch ECC Mux on ecc=1 */ in ddr3_read_leveling_sw()
209 reg |= (dram_info->ecc_ena * in ddr3_read_leveling_sw()
214 DEBUG_RL_S("DDR3 - Read Leveling - ECC Mux Enabled\n"); in ddr3_read_leveling_sw()
216 DEBUG_RL_S("DDR3 - Read Leveling - ECC Mux Disabled\n"); in ddr3_read_leveling_sw()
221 (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
222 reg |= (dram_info->cl << in ddr3_read_leveling_sw()
223 (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
229 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
232 reg |= ((dram_info->cl + 1) << in ddr3_read_leveling_sw()
233 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
236 reg |= ((dram_info->cl + 2) << in ddr3_read_leveling_sw()
237 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
241 /* Read leveling Single CS[cs] */ in ddr3_read_leveling_sw()
244 ddr3_read_leveling_single_cs_rl_mode(cs, freq, in ddr3_read_leveling_sw()
252 ddr3_read_leveling_single_cs_window_mode(cs, freq, in ddr3_read_leveling_sw()
262 DEBUG_RL_C("DDR3 - Read Leveling - Results for CS - ", (u32) cs, in ddr3_read_leveling_sw()
265 for (pup = 0; in ddr3_read_leveling_sw()
266 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
268 DEBUG_RL_S("DDR3 - Read Leveling - PUP: "); in ddr3_read_leveling_sw()
271 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw()
273 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw()
277 DEBUG_RL_C("DDR3 - Read Leveling - Read Sample Delay: ", in ddr3_read_leveling_sw()
278 dram_info->rd_smpl_dly, 2); in ddr3_read_leveling_sw()
279 DEBUG_RL_C("DDR3 - Read Leveling - Read Ready Delay: ", in ddr3_read_leveling_sw()
280 dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_sw()
283 for (pup = 0; in ddr3_read_leveling_sw()
284 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
286 /* ECC support - bit 8 */ in ddr3_read_leveling_sw()
287 pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup; in ddr3_read_leveling_sw()
290 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
291 delay = dram_info->rl_val[cs][pup][D]; in ddr3_read_leveling_sw()
292 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase, in ddr3_read_leveling_sw()
300 /* 0x15B8 - Training SW 2 Register */ in ddr3_read_leveling_sw()
306 } while (reg); /* Wait for '0' */ in ddr3_read_leveling_sw()
308 /* ECC Support - Switch ECC Mux off ecc=0 */ in ddr3_read_leveling_sw()
314 reg_write(REG_DRAM_TRAINING_ADDR, 0); /* 0x15B0 - Training Register */ in ddr3_read_leveling_sw()
320 /* [0] = 0 - Disable SW override */ in ddr3_read_leveling_sw()
321 reg = (reg | (0x1 << REG_DRAM_TRAINING_2_RL_MODE_OFFS)); in ddr3_read_leveling_sw()
322 /* [3] = 1 - Disable RL MODE */ in ddr3_read_leveling_sw()
323 /* 0x15B8 - Training SW 2 Register */ in ddr3_read_leveling_sw()
326 DEBUG_RL_S("DDR3 - Read Leveling - Finished RL procedure for all CS\n"); in ddr3_read_leveling_sw()
335 static void overrun(u32 cs, MV_DRAM_INFO *info, u32 pup, u32 locked_pups, in overrun() argument
341 if (((~locked_pups >> pup) & 0x1) && (final_delay == 0)) { in overrun()
347 if (info->rl_val[cs][idx][S] == RL_UNLOCK_STATE) { in overrun()
349 /* Match expected value ? - Update State Machine */ in overrun()
350 if (info->rl_val[cs][idx][C] < RL_RETRY_COUNT) { in overrun()
351 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We have no overrun and a match on pup: ", in overrun()
353 info->rl_val[cs][idx][C]++; in overrun()
355 /* If pup got to last state - lock the delays */ in overrun()
356 if (info->rl_val[cs][idx][C] == RL_RETRY_COUNT) { in overrun()
357 info->rl_val[cs][idx][C] = 0; in overrun()
358 info->rl_val[cs][idx][DS] = delay; in overrun()
359 info->rl_val[cs][idx][PS] = phase; in overrun()
362 info->rl_val[cs][idx][S] = RL_FINAL_STATE; in overrun()
364 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We have locked pup: ", in overrun()
368 * If first lock - need to lock delays in overrun()
370 if (*first_octet_locked == 0) { in overrun()
371 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We got first lock on pup: ", in overrun()
378 * there was match - dont increment in overrun()
392 * Args: cs - current chip select
393 * freq - current sequence frequency
394 * ecc - ecc iteration indication
395 * dram_info - main struct
399 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq, in ddr3_read_leveling_single_cs_rl_mode() argument
407 int final_delay = 0; in ddr3_read_leveling_single_cs_rl_mode()
409 DEBUG_RL_FULL_C("DDR3 - Read Leveling - Single CS - ", (u32) cs, 1); in ddr3_read_leveling_single_cs_rl_mode()
412 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
413 delay = 0; in ddr3_read_leveling_single_cs_rl_mode()
414 rd_sample_delay = dram_info->cl; in ddr3_read_leveling_single_cs_rl_mode()
415 all_locked = 0; in ddr3_read_leveling_single_cs_rl_mode()
416 first_octet_locked = 0; in ddr3_read_leveling_single_cs_rl_mode()
417 repeat_max_cnt = 0; in ddr3_read_leveling_single_cs_rl_mode()
418 locked_sum = 0; in ddr3_read_leveling_single_cs_rl_mode()
420 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_rl_mode()
422 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_rl_mode()
426 counter_in_progress = 0; in ddr3_read_leveling_single_cs_rl_mode()
428 DEBUG_RL_FULL_S("DDR3 - Read Leveling - RdSmplDly = "); in ddr3_read_leveling_single_cs_rl_mode()
431 DEBUG_RL_FULL_D(dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_single_cs_rl_mode()
442 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_rl_mode()
447 /* 0x15B8 - Training SW 2 Register */ in ddr3_read_leveling_single_cs_rl_mode()
453 } while (reg); /* Wait for '0' */ in ddr3_read_leveling_single_cs_rl_mode()
456 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS; in ddr3_read_leveling_single_cs_rl_mode()
457 locked_pups = 0; in ddr3_read_leveling_single_cs_rl_mode()
459 ddr3_sdram_compare(dram_info, 0xFF, &locked_pups, in ddr3_read_leveling_single_cs_rl_mode()
461 sdram_offset, 0, 0, NULL, 0)) in ddr3_read_leveling_single_cs_rl_mode()
466 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
469 (REG_DRAM_TRAINING_2_OVERRUN_OFFS + pup)) & 0x1)) { in ddr3_read_leveling_single_cs_rl_mode()
470 overrun(cs, dram_info, pup, locked_pups, in ddr3_read_leveling_single_cs_rl_mode()
475 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We got overrun on pup: ", in ddr3_read_leveling_single_cs_rl_mode()
480 if (locked_sum == (dram_info->num_of_std_pups * in ddr3_read_leveling_single_cs_rl_mode()
481 (1 - ecc) + ecc)) { in ddr3_read_leveling_single_cs_rl_mode()
483 DEBUG_RL_FULL_S("DDR3 - Read Leveling - Single Cs - All pups locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
499 DEBUG_RL_FULL_S("DDR3 - Read Leveling - Counter is >=1 and <3\n"); in ddr3_read_leveling_single_cs_rl_mode()
500 …DEBUG_RL_FULL_S("DDR3 - Read Leveling - So we will not increment the delay to see if locked again\… in ddr3_read_leveling_single_cs_rl_mode()
502 …DEBUG_RL_FULL_S("DDR3 - Read Leveling - repeat_max_cnt reached max so now we will increment the de… in ddr3_read_leveling_single_cs_rl_mode()
503 counter_in_progress = 0; in ddr3_read_leveling_single_cs_rl_mode()
516 repeat_max_cnt = 0; in ddr3_read_leveling_single_cs_rl_mode()
518 if ((!ratio_2to1) && ((phase == 0) || (phase == 4))) in ddr3_read_leveling_single_cs_rl_mode()
539 delay = 0; in ddr3_read_leveling_single_cs_rl_mode()
553 DEBUG_RL_FULL_S("DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
554 DEBUG_RL_S("1)DDR3 - Read Leveling - ERROR - NOT all PUPs Locked n"); in ddr3_read_leveling_single_cs_rl_mode()
564 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
574 DEBUG_RL_FULL_S("DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
575 DEBUG_RL_S("2)DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
576 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
578 if (dram_info->rl_val[cs][idx][S] in ddr3_read_leveling_single_cs_rl_mode()
579 == 0) { in ddr3_read_leveling_single_cs_rl_mode()
591 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
597 * phase = 0, need to increment rd_sample_dly in ddr3_read_leveling_single_cs_rl_mode()
599 if (phase == 0 && first_octet_locked == 0) { in ddr3_read_leveling_single_cs_rl_mode()
601 if (rd_sample_delay == 0x10) { in ddr3_read_leveling_single_cs_rl_mode()
602 DEBUG_RL_FULL_S("DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
603 DEBUG_RL_S("3)DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_rl_mode()
604 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
606 if (dram_info-> in ddr3_read_leveling_single_cs_rl_mode()
607 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
619 * cs)); in ddr3_read_leveling_single_cs_rl_mode()
622 cs)); in ddr3_read_leveling_single_cs_rl_mode()
636 case 0: in ddr3_read_leveling_single_cs_rl_mode()
668 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
670 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
672 dram_info->rd_smpl_dly = rd_sample_delay; in ddr3_read_leveling_single_cs_rl_mode()
673 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_rl_mode()
677 for (pup = 0; pup < in ddr3_read_leveling_single_cs_rl_mode()
678 (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_rl_mode()
680 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_rl_mode()
681 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_rl_mode()
688 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
689 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
690 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
701 case 0: in ddr3_read_leveling_single_cs_rl_mode()
724 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
725 reg |= ((rd_sample_delay + add) << (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
727 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_rl_mode()
729 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_rl_mode()
730 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_rl_mode()
731 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_rl_mode()
732 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_rl_mode()
744 * Args: cs - current chip select
745 * freq - current sequence frequency
746 * ecc - ecc iteration indication
747 * dram_info - main struct
751 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq, in ddr3_read_leveling_single_cs_window_mode() argument
759 int final_delay = 0; in ddr3_read_leveling_single_cs_window_mode()
761 DEBUG_RL_FULL_C("DDR3 - Read Leveling - Single CS - ", (u32) cs, 1); in ddr3_read_leveling_single_cs_window_mode()
764 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
765 delay = 0; in ddr3_read_leveling_single_cs_window_mode()
766 rd_sample_delay = dram_info->cl; in ddr3_read_leveling_single_cs_window_mode()
767 all_locked = 0; in ddr3_read_leveling_single_cs_window_mode()
768 first_octet_locked = 0; in ddr3_read_leveling_single_cs_window_mode()
769 repeat_max_cnt = 0; in ddr3_read_leveling_single_cs_window_mode()
770 sum = 0; in ddr3_read_leveling_single_cs_window_mode()
771 final_sum = 0; in ddr3_read_leveling_single_cs_window_mode()
772 locked_sum = 0; in ddr3_read_leveling_single_cs_window_mode()
774 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
776 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_window_mode()
780 counter_in_progress = 0; in ddr3_read_leveling_single_cs_window_mode()
782 DEBUG_RL_FULL_S("DDR3 - Read Leveling - RdSmplDly = "); in ddr3_read_leveling_single_cs_window_mode()
785 DEBUG_RL_FULL_D(dram_info->rd_rdy_dly, 2); in ddr3_read_leveling_single_cs_window_mode()
796 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_window_mode()
801 /* 0x15B8 - Training SW 2 Register */ in ddr3_read_leveling_single_cs_window_mode()
807 } while (reg); /* Wait for '0' */ in ddr3_read_leveling_single_cs_window_mode()
810 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS; in ddr3_read_leveling_single_cs_window_mode()
811 locked_pups = 0; in ddr3_read_leveling_single_cs_window_mode()
813 ddr3_sdram_compare(dram_info, 0xFF, &locked_pups, in ddr3_read_leveling_single_cs_window_mode()
815 sdram_offset, 0, 0, NULL, 0)) in ddr3_read_leveling_single_cs_window_mode()
819 for (pup = 0; pup < (dram_info->num_of_std_pups * in ddr3_read_leveling_single_cs_window_mode()
820 (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_window_mode()
829 pup)) & 0x1)) { in ddr3_read_leveling_single_cs_window_mode()
833 if (dram_info->rl_val[cs][idx][S] == RL_WINDOW_STATE) { in ddr3_read_leveling_single_cs_window_mode()
835 * Match expected value ? - Update in ddr3_read_leveling_single_cs_window_mode()
838 if (((~locked_pups >> pup) & 0x1) in ddr3_read_leveling_single_cs_window_mode()
839 && (final_delay == 0)) { in ddr3_read_leveling_single_cs_window_mode()
840 /* Match - Still inside the Window */ in ddr3_read_leveling_single_cs_window_mode()
841 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We got another match inside the window for pup: ", in ddr3_read_leveling_single_cs_window_mode()
845 /* We got fail -> this is the end of the window */ in ddr3_read_leveling_single_cs_window_mode()
846 dram_info->rl_val[cs][idx][DE] = delay; in ddr3_read_leveling_single_cs_window_mode()
847 dram_info->rl_val[cs][idx][PE] = phase; in ddr3_read_leveling_single_cs_window_mode()
849 dram_info->rl_val[cs][idx][S]++; in ddr3_read_leveling_single_cs_window_mode()
851 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We finished the window for pup: ", in ddr3_read_leveling_single_cs_window_mode()
856 } else if (dram_info->rl_val[cs][idx][S] == in ddr3_read_leveling_single_cs_window_mode()
860 * Match expected value ? - Update in ddr3_read_leveling_single_cs_window_mode()
863 if (dram_info->rl_val[cs][idx][C] < in ddr3_read_leveling_single_cs_window_mode()
865 if (((~locked_pups >> pup) & 0x1)) { in ddr3_read_leveling_single_cs_window_mode()
867 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We have no overrun and a match on pup: ", in ddr3_read_leveling_single_cs_window_mode()
869 dram_info->rl_val[cs][idx][C]++; in ddr3_read_leveling_single_cs_window_mode()
871 /* If pup got to last state - lock the delays */ in ddr3_read_leveling_single_cs_window_mode()
872 if (dram_info->rl_val[cs][idx][C] == in ddr3_read_leveling_single_cs_window_mode()
874 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
875 dram_info->rl_val[cs][idx][DS] = in ddr3_read_leveling_single_cs_window_mode()
877 dram_info->rl_val[cs][idx][PS] = in ddr3_read_leveling_single_cs_window_mode()
879 dram_info->rl_val[cs][idx][S]++; /* Go to Window State */ in ddr3_read_leveling_single_cs_window_mode()
883 /* IF First lock - need to lock delays */ in ddr3_read_leveling_single_cs_window_mode()
884 if (first_octet_locked == 0) { in ddr3_read_leveling_single_cs_window_mode()
885 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We got first lock on pup: ", in ddr3_read_leveling_single_cs_window_mode()
893 /* if pup is in not in final state but there was match - dont increment counter */ in ddr3_read_leveling_single_cs_window_mode()
902 DEBUG_RL_FULL_C("DDR3 - Read Leveling - We got overrun on pup: ", in ddr3_read_leveling_single_cs_window_mode()
908 if (final_sum == (dram_info->num_of_std_pups * (1 - ecc) + ecc)) { in ddr3_read_leveling_single_cs_window_mode()
910 DEBUG_RL_FULL_S("DDR3 - Read Leveling - Single Cs - All pups locked\n"); in ddr3_read_leveling_single_cs_window_mode()
926 DEBUG_RL_FULL_S("DDR3 - Read Leveling - Counter is >=1 and <3\n"); in ddr3_read_leveling_single_cs_window_mode()
927 …DEBUG_RL_FULL_S("DDR3 - Read Leveling - So we will not increment the delay to see if locked again\… in ddr3_read_leveling_single_cs_window_mode()
929 …DEBUG_RL_FULL_S("DDR3 - Read Leveling - repeat_max_cnt reached max so now we will increment the de… in ddr3_read_leveling_single_cs_window_mode()
930 counter_in_progress = 0; in ddr3_read_leveling_single_cs_window_mode()
939 repeat_max_cnt = 0; in ddr3_read_leveling_single_cs_window_mode()
963 delay = 0; in ddr3_read_leveling_single_cs_window_mode()
970 if (phase == 0) in ddr3_read_leveling_single_cs_window_mode()
978 DEBUG_RL_FULL_S("DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_window_mode()
985 if (phase == 0) in ddr3_read_leveling_single_cs_window_mode()
991 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
1000 DEBUG_RL_FULL_S("DDR3 - Read Leveling - ERROR - NOT all PUPs Locked\n"); in ddr3_read_leveling_single_cs_window_mode()
1008 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
1014 * now phase = 0, need to increment in ddr3_read_leveling_single_cs_window_mode()
1017 if (phase == 0 && first_octet_locked == 0) { in ddr3_read_leveling_single_cs_window_mode()
1024 * cs)); in ddr3_read_leveling_single_cs_window_mode()
1027 cs)); in ddr3_read_leveling_single_cs_window_mode()
1041 case 0: in ddr3_read_leveling_single_cs_window_mode()
1070 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1072 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1074 dram_info->rd_smpl_dly = rd_sample_delay; in ddr3_read_leveling_single_cs_window_mode()
1075 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_window_mode()
1079 for (pup = 0; in ddr3_read_leveling_single_cs_window_mode()
1081 (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
1083 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_window_mode()
1084 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
1091 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_window_mode()
1092 DEBUG_RL_S("DDR3 - Read Leveling - Window info - PUP: "); in ddr3_read_leveling_single_cs_window_mode()
1095 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PS], 1); in ddr3_read_leveling_single_cs_window_mode()
1097 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DS], 2); in ddr3_read_leveling_single_cs_window_mode()
1099 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PE], 1); in ddr3_read_leveling_single_cs_window_mode()
1101 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DE], 2); in ddr3_read_leveling_single_cs_window_mode()
1106 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
1110 if (dram_info->rl_val[cs][idx][PS] == 4) in ddr3_read_leveling_single_cs_window_mode()
1111 dram_info->rl_val[cs][idx][PS] = 1; in ddr3_read_leveling_single_cs_window_mode()
1112 if (dram_info->rl_val[cs][idx][PE] == 4) in ddr3_read_leveling_single_cs_window_mode()
1113 dram_info->rl_val[cs][idx][PE] = 1; in ddr3_read_leveling_single_cs_window_mode()
1115 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1116 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1117 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1118 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1120 tmp = (delay_e - delay_s) / 2 + delay_s; in ddr3_read_leveling_single_cs_window_mode()
1128 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1129 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY_INV; in ddr3_read_leveling_single_cs_window_mode()
1132 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1133 MAX_DELAY + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1134 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1135 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1137 tmp = (delay_e - delay_s) / 2 + delay_s; in ddr3_read_leveling_single_cs_window_mode()
1143 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1144 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1148 if (dram_info->rl_val[cs][idx][PS] > 1) in ddr3_read_leveling_single_cs_window_mode()
1149 dram_info->rl_val[cs][idx][PS] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1150 if (dram_info->rl_val[cs][idx][PE] > 1) in ddr3_read_leveling_single_cs_window_mode()
1151 dram_info->rl_val[cs][idx][PE] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1154 delay_s = dram_info->rl_val[cs][idx][PS] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1155 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1156 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1157 dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1159 tmp = (delay_e - delay_s) / 2 + delay_s; in ddr3_read_leveling_single_cs_window_mode()
1167 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1168 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1176 case 0: in ddr3_read_leveling_single_cs_window_mode()
1198 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1200 ((rd_sample_delay + add) << (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1202 dram_info->rd_rdy_dly = rd_sample_delay + add; in ddr3_read_leveling_single_cs_window_mode()
1204 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_window_mode()
1205 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_window_mode()
1206 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_window_mode()
1207 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_window_mode()