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/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Dmarvell-cn10k-tad.yaml4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
7 title: Marvell CN10K LLC-TAD performance monitor
13 The Tag-and-Data units (TADs) maintain coherence and contain CN10K
23 const: marvell,cn10k-tad-pmu
57 compatible = "marvell,cn10k-tad-pmu";
H A Dmarvell-cn10k-ddr.yaml4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
7 title: Marvell CN10K DDR performance monitor
16 - marvell,cn10k-ddr-pmu
34 compatible = "marvell,cn10k-ddr-pmu";
/openbmc/linux/drivers/char/hw_random/
H A Dcn10k-rng.c2 /* Marvell CN10K RVU Hardware Random Number Generator.
34 /* Octeon CN10K-A A0/A1, CNF10K-A A0/A1 and CNF10K-B A0/B0
48 /* CN10K-A A0/A1 */ in cn10k_is_extended_trng_regs_supported()
194 "cn10k-rng-%s", dev_name(&pdev->dev)); in cn10k_rng_probe()
227 MODULE_DESCRIPTION("Marvell CN10K HW RNG Driver");
H A DMakefile49 obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
H A DKconfig556 tristate "Marvell CN10K Random Number Generator support"
561 generator available in Marvell CN10K SoCs.
/openbmc/linux/drivers/perf/
H A DKconfig191 tristate "Marvell CN10K LLC-TAD PMU"
195 performance monitors on CN10K family silicons.
214 tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
218 event on CN10K platform.
H A Dmarvell_cn10k_tad_pmu.c2 /* Marvell CN10K LLC-TAD perf driver
367 { .compatible = "marvell,cn10k-tad-pmu", },
414 "perf/cn10k/tadpmu:online", in tad_pmu_init()
436 MODULE_DESCRIPTION("Marvell CN10K LLC-TAD Perf driver");
H A Dmarvell_cn10k_ddr_pmu.c2 /* Marvell CN10K DRAM Subsystem (DSS) Performance Monitor Driver
691 pr_info("CN10K DDR PMU Driver for ddrc@%llx\n", res->start); in cn10k_ddr_perf_probe()
714 { .compatible = "marvell,cn10k-ddr-pmu", },
730 .name = "cn10k-ddr-pmu",
745 "perf/marvell/cn10k/ddr:online", NULL, in cn10k_ddr_pmu_init()
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dlmac_common.h2 /* Marvell CN10K RPM driver
79 /* Unlike CN10K which shares same CSR offset with CGX
H A Dcommon.h146 #define CN10K_MAX_DWRR_WEIGHT 16384 /* Weight is 14bit on CN10K */
148 /* Don't change the order as on CN10K (except CN10KB)
H A Dmcs.h2 /* Marvell CN10K MCS driver
212 /* CN10K-B APIs */
H A Dmbox.h900 /* CN10K NIX AQ enqueue msg */
2119 u64 pkt_ctl_cnt; /* CN10K-B */
2139 /* Only for CN10K-B */
2164 u64 octet_decrypt_cnt; /* CN10K-B */
2165 u64 octet_validate_cnt; /* CN10K-B */
2169 u64 octet_encrypt_cnt; /* CN10K-B */
2170 u64 octet_protected_cnt; /* CN10K-B */
H A Drvu.h938 /* CN10K RVU */
942 /* CN10K NIX */
945 /* CN10K RVU - LMT*/
968 /* CN10K MCS */
H A Drpm.h2 /* Marvell CN10K RPM driver
H A Dmcs_rvu_if.c2 /* Marvell CN10K MCS driver
471 /* CN10K-B has only one mcs block */ in rvu_mcs_flr_handler()
881 /* Needed only for CN10K-B */ in rvu_mcs_init()
H A Drvu_struct.h370 /* CN10K NIX Receive queue context structure */
458 /* CN10K NIX Send queue context structure */
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A DMakefile10 otx2_flows.o otx2_tc.o cn10k.o otx2_dmac_flt.o \
H A Dotx2_vf.c16 #include "cn10k.h"
317 /* For cn10k platform, VF mailbox region is in its BAR2 in otx2vf_vfaf_mbox_init()
H A Dqos_sq.c11 #include "cn10k.h"
H A Dotx2_common.c17 #include "cn10k.h"
635 /* Set link type for DWRR MTU selection on CN10K silicons */ in otx2_txschq_config()
692 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will in otx2_txschq_config()
694 * will work on both OTx2 and CN10K. in otx2_txschq_config()
H A Dcn10k.c8 #include "cn10k.h"
/openbmc/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptpf_ucode.h26 /* Maximum number of supported engines/cores on OcteonTX2/CN10K platform */
H A Dotx2_cptvf_main.c85 /* For cn10k platform, VF mailbox region is in its BAR2 in cptvf_pfvf_mbox_init()
H A Dotx2_cpt_hw_types.h287 } cn10k; member
/openbmc/linux/Documentation/networking/device_drivers/ethernet/marvell/
H A Docteontx2.rst300 octeontx2 silicon and CN10K transmit interface consists of five transmit levels

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