143ac0b82SSrujana Challa /* SPDX-License-Identifier: GPL-2.0-only 243ac0b82SSrujana Challa * Copyright (C) 2020 Marvell. 343ac0b82SSrujana Challa */ 443ac0b82SSrujana Challa 543ac0b82SSrujana Challa #ifndef __OTX2_CPTPF_UCODE_H 643ac0b82SSrujana Challa #define __OTX2_CPTPF_UCODE_H 743ac0b82SSrujana Challa 843ac0b82SSrujana Challa #include <linux/pci.h> 943ac0b82SSrujana Challa #include <linux/types.h> 1043ac0b82SSrujana Challa #include <linux/module.h> 1143ac0b82SSrujana Challa #include "otx2_cpt_hw_types.h" 1243ac0b82SSrujana Challa #include "otx2_cpt_common.h" 1343ac0b82SSrujana Challa 1443ac0b82SSrujana Challa /* 1543ac0b82SSrujana Challa * On OcteonTX2 platform IPSec ucode can use both IE and SE engines therefore 1643ac0b82SSrujana Challa * IE and SE engines can be attached to the same engine group. 1743ac0b82SSrujana Challa */ 1843ac0b82SSrujana Challa #define OTX2_CPT_MAX_ETYPES_PER_GRP 2 1943ac0b82SSrujana Challa 2043ac0b82SSrujana Challa /* CPT ucode signature size */ 2143ac0b82SSrujana Challa #define OTX2_CPT_UCODE_SIGN_LEN 256 2243ac0b82SSrujana Challa 2343ac0b82SSrujana Challa /* Microcode version string length */ 2443ac0b82SSrujana Challa #define OTX2_CPT_UCODE_VER_STR_SZ 44 2543ac0b82SSrujana Challa 2640a645f7SSrujana Challa /* Maximum number of supported engines/cores on OcteonTX2/CN10K platform */ 2740a645f7SSrujana Challa #define OTX2_CPT_MAX_ENGINES 144 2843ac0b82SSrujana Challa 2943ac0b82SSrujana Challa #define OTX2_CPT_ENGS_BITMASK_LEN BITS_TO_LONGS(OTX2_CPT_MAX_ENGINES) 3043ac0b82SSrujana Challa 3140a645f7SSrujana Challa #define OTX2_CPT_UCODE_SZ (64 * 1024) 3240a645f7SSrujana Challa 3343ac0b82SSrujana Challa /* Microcode types */ 3443ac0b82SSrujana Challa enum otx2_cpt_ucode_type { 3543ac0b82SSrujana Challa OTX2_CPT_AE_UC_TYPE = 1, /* AE-MAIN */ 3643ac0b82SSrujana Challa OTX2_CPT_SE_UC_TYPE1 = 20,/* SE-MAIN - combination of 21 and 22 */ 3743ac0b82SSrujana Challa OTX2_CPT_SE_UC_TYPE2 = 21,/* Fast Path IPSec + AirCrypto */ 3843ac0b82SSrujana Challa OTX2_CPT_SE_UC_TYPE3 = 22,/* 3943ac0b82SSrujana Challa * Hash + HMAC + FlexiCrypto + RNG + 4043ac0b82SSrujana Challa * Full Feature IPSec + AirCrypto + Kasumi 4143ac0b82SSrujana Challa */ 4243ac0b82SSrujana Challa OTX2_CPT_IE_UC_TYPE1 = 30, /* IE-MAIN - combination of 31 and 32 */ 4343ac0b82SSrujana Challa OTX2_CPT_IE_UC_TYPE2 = 31, /* Fast Path IPSec */ 4443ac0b82SSrujana Challa OTX2_CPT_IE_UC_TYPE3 = 32, /* 4543ac0b82SSrujana Challa * Hash + HMAC + FlexiCrypto + RNG + 4643ac0b82SSrujana Challa * Full Future IPSec 4743ac0b82SSrujana Challa */ 4843ac0b82SSrujana Challa }; 4943ac0b82SSrujana Challa 5043ac0b82SSrujana Challa struct otx2_cpt_bitmap { 5143ac0b82SSrujana Challa unsigned long bits[OTX2_CPT_ENGS_BITMASK_LEN]; 5243ac0b82SSrujana Challa int size; 5343ac0b82SSrujana Challa }; 5443ac0b82SSrujana Challa 5543ac0b82SSrujana Challa struct otx2_cpt_engines { 5643ac0b82SSrujana Challa int type; 5743ac0b82SSrujana Challa int count; 5843ac0b82SSrujana Challa }; 5943ac0b82SSrujana Challa 6043ac0b82SSrujana Challa /* Microcode version number */ 6143ac0b82SSrujana Challa struct otx2_cpt_ucode_ver_num { 6243ac0b82SSrujana Challa u8 nn; 6343ac0b82SSrujana Challa u8 xx; 6443ac0b82SSrujana Challa u8 yy; 6543ac0b82SSrujana Challa u8 zz; 6643ac0b82SSrujana Challa }; 6743ac0b82SSrujana Challa 6843ac0b82SSrujana Challa struct otx2_cpt_ucode_hdr { 6943ac0b82SSrujana Challa struct otx2_cpt_ucode_ver_num ver_num; 7043ac0b82SSrujana Challa u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ]; 7143ac0b82SSrujana Challa __be32 code_length; 7243ac0b82SSrujana Challa u32 padding[3]; 7343ac0b82SSrujana Challa }; 7443ac0b82SSrujana Challa 7543ac0b82SSrujana Challa struct otx2_cpt_ucode { 7643ac0b82SSrujana Challa u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];/* 7743ac0b82SSrujana Challa * ucode version in readable 7843ac0b82SSrujana Challa * format 7943ac0b82SSrujana Challa */ 8043ac0b82SSrujana Challa struct otx2_cpt_ucode_ver_num ver_num;/* ucode version number */ 8143ac0b82SSrujana Challa char filename[OTX2_CPT_NAME_LENGTH];/* ucode filename */ 8243ac0b82SSrujana Challa dma_addr_t dma; /* phys address of ucode image */ 8343ac0b82SSrujana Challa void *va; /* virt address of ucode image */ 8443ac0b82SSrujana Challa u32 size; /* ucode image size */ 8543ac0b82SSrujana Challa int type; /* ucode image type SE, IE, AE or SE+IE */ 8643ac0b82SSrujana Challa }; 8743ac0b82SSrujana Challa 8843ac0b82SSrujana Challa struct otx2_cpt_uc_info_t { 8943ac0b82SSrujana Challa struct list_head list; 9043ac0b82SSrujana Challa struct otx2_cpt_ucode ucode;/* microcode information */ 9143ac0b82SSrujana Challa const struct firmware *fw; 9243ac0b82SSrujana Challa }; 9343ac0b82SSrujana Challa 9443ac0b82SSrujana Challa /* Maximum and current number of engines available for all engine groups */ 9543ac0b82SSrujana Challa struct otx2_cpt_engs_available { 9643ac0b82SSrujana Challa int max_se_cnt; 9743ac0b82SSrujana Challa int max_ie_cnt; 9843ac0b82SSrujana Challa int max_ae_cnt; 9943ac0b82SSrujana Challa int se_cnt; 10043ac0b82SSrujana Challa int ie_cnt; 10143ac0b82SSrujana Challa int ae_cnt; 10243ac0b82SSrujana Challa }; 10343ac0b82SSrujana Challa 10443ac0b82SSrujana Challa /* Engines reserved to an engine group */ 10543ac0b82SSrujana Challa struct otx2_cpt_engs_rsvd { 10643ac0b82SSrujana Challa int type; /* engine type */ 10743ac0b82SSrujana Challa int count; /* number of engines attached */ 10843ac0b82SSrujana Challa int offset; /* constant offset of engine type in the bitmap */ 10943ac0b82SSrujana Challa unsigned long *bmap; /* attached engines bitmap */ 11043ac0b82SSrujana Challa struct otx2_cpt_ucode *ucode; /* ucode used by these engines */ 11143ac0b82SSrujana Challa }; 11243ac0b82SSrujana Challa 11343ac0b82SSrujana Challa struct otx2_cpt_mirror_info { 11443ac0b82SSrujana Challa int is_ena; /* 11543ac0b82SSrujana Challa * is mirroring enabled, it is set only for engine 11643ac0b82SSrujana Challa * group which mirrors another engine group 11743ac0b82SSrujana Challa */ 11843ac0b82SSrujana Challa int idx; /* 11943ac0b82SSrujana Challa * index of engine group which is mirrored by this 12043ac0b82SSrujana Challa * group, set only for engine group which mirrors 12143ac0b82SSrujana Challa * another group 12243ac0b82SSrujana Challa */ 12343ac0b82SSrujana Challa int ref_count; /* 12443ac0b82SSrujana Challa * number of times this engine group is mirrored by 12543ac0b82SSrujana Challa * other groups, this is set only for engine group 12643ac0b82SSrujana Challa * which is mirrored by other group(s) 12743ac0b82SSrujana Challa */ 12843ac0b82SSrujana Challa }; 12943ac0b82SSrujana Challa 13043ac0b82SSrujana Challa struct otx2_cpt_eng_grp_info { 13143ac0b82SSrujana Challa struct otx2_cpt_eng_grps *g; /* pointer to engine_groups structure */ 13243ac0b82SSrujana Challa /* engines attached */ 13343ac0b82SSrujana Challa struct otx2_cpt_engs_rsvd engs[OTX2_CPT_MAX_ETYPES_PER_GRP]; 13443ac0b82SSrujana Challa /* ucodes information */ 13543ac0b82SSrujana Challa struct otx2_cpt_ucode ucode[OTX2_CPT_MAX_ETYPES_PER_GRP]; 13643ac0b82SSrujana Challa /* engine group mirroring information */ 13743ac0b82SSrujana Challa struct otx2_cpt_mirror_info mirror; 13843ac0b82SSrujana Challa int idx; /* engine group index */ 13943ac0b82SSrujana Challa bool is_enabled; /* 14043ac0b82SSrujana Challa * is engine group enabled, engine group is enabled 14143ac0b82SSrujana Challa * when it has engines attached and ucode loaded 14243ac0b82SSrujana Challa */ 14343ac0b82SSrujana Challa }; 14443ac0b82SSrujana Challa 14543ac0b82SSrujana Challa struct otx2_cpt_eng_grps { 146d9d77497SSrujana Challa struct mutex lock; 14743ac0b82SSrujana Challa struct otx2_cpt_eng_grp_info grp[OTX2_CPT_MAX_ENGINE_GROUPS]; 14843ac0b82SSrujana Challa struct otx2_cpt_engs_available avail; 14943ac0b82SSrujana Challa void *obj; /* device specific data */ 15043ac0b82SSrujana Challa int engs_num; /* total number of engines supported */ 15143ac0b82SSrujana Challa u8 eng_ref_cnt[OTX2_CPT_MAX_ENGINES];/* engines reference count */ 15243ac0b82SSrujana Challa bool is_grps_created; /* Is the engine groups are already created */ 15343ac0b82SSrujana Challa }; 15443ac0b82SSrujana Challa struct otx2_cptpf_dev; 15543ac0b82SSrujana Challa int otx2_cpt_init_eng_grps(struct pci_dev *pdev, 15643ac0b82SSrujana Challa struct otx2_cpt_eng_grps *eng_grps); 15743ac0b82SSrujana Challa void otx2_cpt_cleanup_eng_grps(struct pci_dev *pdev, 15843ac0b82SSrujana Challa struct otx2_cpt_eng_grps *eng_grps); 15940a645f7SSrujana Challa int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf, 16043ac0b82SSrujana Challa struct otx2_cpt_eng_grps *eng_grps); 16143ac0b82SSrujana Challa int otx2_cpt_disable_all_cores(struct otx2_cptpf_dev *cptpf); 16243ac0b82SSrujana Challa int otx2_cpt_get_eng_grp(struct otx2_cpt_eng_grps *eng_grps, int eng_type); 16378506c2aSSrujana Challa int otx2_cpt_discover_eng_capabilities(struct otx2_cptpf_dev *cptpf); 164d9d77497SSrujana Challa int otx2_cpt_dl_custom_egrp_create(struct otx2_cptpf_dev *cptpf, 165d9d77497SSrujana Challa struct devlink_param_gset_ctx *ctx); 166d9d77497SSrujana Challa int otx2_cpt_dl_custom_egrp_delete(struct otx2_cptpf_dev *cptpf, 167d9d77497SSrujana Challa struct devlink_param_gset_ctx *ctx); 168d9d77497SSrujana Challa void otx2_cpt_print_uc_dbg_info(struct otx2_cptpf_dev *cptpf); 169*4ad28689SShijith Thotton struct otx2_cpt_engs_rsvd *find_engines_by_type( 170*4ad28689SShijith Thotton struct otx2_cpt_eng_grp_info *eng_grp, 171*4ad28689SShijith Thotton int eng_type); 17243ac0b82SSrujana Challa #endif /* __OTX2_CPTPF_UCODE_H */ 173