| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | Makefile | 2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
6 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
7 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
8 obj-$(CONFIG_COMMON_CLK_MT6765_IMGSYS) += clk-mt6765-img.o
9 obj-$(CONFIG_COMMON_CLK_MT6765_MIPI0ASYS) += clk-mt6765-mipi0a.o
10 obj-$(CONFIG_COMMON_CLK_MT6765_MMSYS) += clk-mt6765-mm.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_VCODECSYS) += clk-mt6765-vcodec.o
12 obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
[all …]
|
| /openbmc/linux/drivers/clk/imx/ |
| H A D | Makefile | 3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
12 mxc-clk-objs += clk-fixup-mux.o
[all …]
|
| H A D | clk-imx5.c | 7 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
19 #include "clk.h"
128 static struct clk *clk[IMX5_CLK_END]; variable
133 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in mx5_clocks_common_init()
134 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in mx5_clocks_common_init()
135 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in mx5_clocks_common_init()
136 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0); in mx5_clocks_common_init()
137 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0); in mx5_clocks_common_init()
139 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, in mx5_clocks_common_init()
[all …]
|
| H A D | clk-vf610.c | 8 #include <linux/clk.h>
12 #include "clk.h"
113 static struct clk *clk[VF610_CLK_END]; variable
131 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
134 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
137 if (IS_ERR(clk)) in vf610_get_fixed_clock()
138 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
139 return clk; in vf610_get_fixed_clock()
184 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in vf610_clocks_init()
185 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); in vf610_clocks_init()
[all …]
|
| H A D | clk-imx27.c | 2 #include <linux/clk.h>
3 #include <linux/clk-provider.h>
13 #include "clk.h"
48 static struct clk *clk[IMX27_CLK_MAX]; variable
55 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
56 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); in _mx27_clocks_init()
57 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); in _mx27_clocks_init()
58 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); in _mx27_clocks_init()
59 clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); in _mx27_clocks_init()
60 clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); in _mx27_clocks_init()
[all …]
|
| H A D | clk-imx25.c | 9 #include <linux/clk.h>
18 #include "clk.h"
75 static struct clk *clk[clk_max]; variable
81 clk[dummy] = imx_clk_fixed("dummy", 0); in __mx25_clocks_init()
82 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
83 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); in __mx25_clocks_init()
84 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); in __mx25_clocks_init()
85 …clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)… in __mx25_clocks_init()
86 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); in __mx25_clocks_init()
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
[all …]
|
| H A D | clk-imx35.c | 7 #include <linux/clk.h>
15 #include "clk.h"
82 static struct clk *clk[clk_max]; variable
98 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); in _mx35_clocks_init()
106 clk[ckih] = imx_clk_fixed("ckih", 24000000); in _mx35_clocks_init()
107 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx35_clocks_init()
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
111 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in _mx35_clocks_init()
114 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); in _mx35_clocks_init()
[all …]
|
| /openbmc/linux/drivers/sh/clk/ |
| H A D | cpg.c | 11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
32 iowrite8(value, clk->mapped_reg); in sh_clk_write()
[all …]
|
| H A D | core.c | 29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, in clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, in clk_rate_table_round()
149 if (clk->nr_freqs < 1) in clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, in clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), in clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, in clk_rate_mult_range_round() argument
[all …]
|
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | stih410-clock.dtsi | 15 compatible = "st,stih410-clk", "simple-bus";
20 clk_sysin: clk-sysin {
30 arm_periph_clk: clk-m-a9-periphs {
58 clk_m_a9: clk-m-a9@92b0000 {
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
78 clock-output-names = "clk-m-a9-ext2f-div2";
92 clock-output-names = "clk-s-icn-reg-0";
99 clk_s_a0_pll: clk-s-a0-pll {
105 clock-output-names = "clk-s-a0-pll-ofd-0";
106 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
[all …]
|
| H A D | stih407-clock.dtsi | 18 clk_sysin: clk-sysin {
27 arm_periph_clk: clk-m-a9-periphs {
56 clk_m_a9: clk-m-a9@92b0000 {
70 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
76 clock-output-names = "clk-m-a9-ext2f-div2";
90 clock-output-names = "clk-s-icn-reg-0";
97 clk_s_a0_pll: clk-s-a0-pll {
103 clock-output-names = "clk-s-a0-pll-ofd-0";
106 clk_s_a0_flexgen: clk-s-a0-flexgen {
114 clock-output-names = "clk-ic-lmi0";
[all …]
|
| /openbmc/linux/arch/mips/lantiq/ |
| H A D | clk.c | 12 #include <linux/clk.h>
23 #include "clk.h"
27 static struct clk cpu_clk_generic[4];
38 struct clk *clk_get_cpu(void) in clk_get_cpu()
43 struct clk *clk_get_fpi(void) in clk_get_fpi()
49 struct clk *clk_get_io(void) in clk_get_io()
55 struct clk *clk_get_ppe(void) in clk_get_ppe()
61 static inline int clk_good(struct clk *clk) in clk_good() argument
63 return clk && !IS_ERR(clk); in clk_good()
66 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
[all …]
|
| /openbmc/linux/drivers/clk/spear/ |
| H A D | spear3xx_clock.c | 9 #include <linux/clk.h>
11 #include <linux/clk/spear.h>
16 #include "clk.h"
30 /* CORE CLK CFG register masks */
141 struct clk *clk; in spear300_clk_init() local
143 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, in spear300_clk_init()
145 clk_register_clkdev(clk, NULL, "60000000.clcd"); in spear300_clk_init()
147 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
149 clk_register_clkdev(clk, NULL, "94000000.flash"); in spear300_clk_init()
151 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
[all …]
|
| H A D | spear1310_clock.c | 12 #include <linux/clk/spear.h>
16 #include "clk.h"
262 /* For gmac phy input clk */
310 /* For parent clk = 49.152 MHz */
317 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
318 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
322 /* For parent clk = 49.152 MHz */
384 struct clk *clk, *clk1; in spear1310_clk_init() local
386 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear1310_clk_init()
387 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1310_clk_init()
[all …]
|
| H A D | spear6xx_clock.c | 10 #include <linux/clk/spear.h>
13 #include "clk.h"
27 /* CORE CLK CFG register masks */
116 struct clk *clk, *clk1; in spear6xx_clk_init() local
118 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear6xx_clk_init()
119 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear6xx_clk_init()
121 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); in spear6xx_clk_init()
122 clk_register_clkdev(clk, "osc_30m_clk", NULL); in spear6xx_clk_init()
124 /* clock derived from 32 KHz osc clk */ in spear6xx_clk_init()
125 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, in spear6xx_clk_init()
[all …]
|
| /openbmc/qemu/hw/core/ |
| H A D | clock.c | 23 void clock_setup_canonical_path(Clock *clk) in clock_setup_canonical_path() argument
25 g_free(clk->canonical_path); in clock_setup_canonical_path()
26 clk->canonical_path = object_get_canonical_path(OBJECT(clk)); in clock_setup_canonical_path()
32 Clock *clk; in clock_new() local
38 clk = CLOCK(obj); in clock_new()
39 clock_setup_canonical_path(clk); in clock_new()
41 return clk; in clock_new()
44 void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque, in clock_set_callback() argument
47 clk->callback = cb; in clock_set_callback()
48 clk->callback_opaque = opaque; in clock_set_callback()
[all …]
|
| /openbmc/linux/include/linux/ |
| H A D | clk.h | 3 * linux/include/linux/clk.h
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
46 * @notifier_head: a blocking_notifier_head for this clk
51 * particular @clk. Future notifiers on that @clk are added to the
[all …]
|
| /openbmc/linux/drivers/clk/st/ |
| H A D | clk-flexgen.c | 3 * clk-flexgen.c
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
206 static struct clk *clk_register_flexgen(const char *name, in clk_register_flexgen()
211 struct clk *clk; in clk_register_flexgen() local
267 clk = clk_register(NULL, &fgxbar->hw); in clk_register_flexgen()
268 if (IS_ERR(clk)) in clk_register_flexgen()
272 __clk_get_name(clk), in clk_register_flexgen()
273 __clk_get_name(clk_get_parent(clk)), in clk_register_flexgen()
274 (unsigned int)clk_get_rate(clk)); in clk_register_flexgen()
[all …]
|
| /openbmc/linux/arch/m68k/coldfire/ |
| H A D | clk.c | 5 * clk.c -- general ColdFire CPU kernel clk handling
16 #include <linux/clk.h>
31 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument
33 clk->enabled = 1; in __clk_init_enabled()
34 clk->clk_ops->enable(clk); in __clk_init_enabled()
37 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument
39 clk->enabled = 0; in __clk_init_disabled()
40 clk->clk_ops->disable(clk); in __clk_init_disabled()
43 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument
45 __raw_writeb(clk->slot, MCFPM_PPMCR0); in __clk_enable0()
[all …]
|
| /openbmc/linux/drivers/clk/ |
| H A D | Makefile | 3 obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
6 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
7 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
8 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
9 obj-$(CONFIG_COMMON_CLK) += clk-gate.o
10 obj-$(CONFIG_CLK_GATE_KUNIT_TEST) += clk-gate_test.o
11 obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o
12 obj-$(CONFIG_COMMON_CLK) += clk-mux.o
13 obj-$(CONFIG_COMMON_CLK) += clk-composite.o
[all …]
|
| /openbmc/linux/kernel/time/ |
| H A D | posix-clock.c | 22 struct posix_clock *clk = fp->private_data; in get_posix_clock() local
24 down_read(&clk->rwsem); in get_posix_clock()
26 if (!clk->zombie) in get_posix_clock()
27 return clk; in get_posix_clock()
29 up_read(&clk->rwsem); in get_posix_clock()
34 static void put_posix_clock(struct posix_clock *clk) in put_posix_clock() argument
36 up_read(&clk->rwsem); in put_posix_clock()
42 struct posix_clock *clk = get_posix_clock(fp); in posix_clock_read() local
45 if (!clk) in posix_clock_read()
48 if (clk->ops.read) in posix_clock_read()
[all …]
|
| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos5.c | 11 #include <asm/arch/clk.h>
549 struct exynos5_clock *clk = in exynos5250_system_clock_init() local
558 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); in exynos5250_system_clock_init()
560 val = readl(&clk->mux_stat_cpu); in exynos5250_system_clock_init()
563 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); in exynos5250_system_clock_init()
565 val = readl(&clk->mux_stat_core1); in exynos5250_system_clock_init()
568 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); in exynos5250_system_clock_init()
569 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); in exynos5250_system_clock_init()
570 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); in exynos5250_system_clock_init()
571 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); in exynos5250_system_clock_init()
[all …]
|
| /openbmc/linux/drivers/clk/ux500/ |
| H A D | u8500_of_clk.c | 11 #include <linux/clk-provider.h>
14 #include "clk.h"
18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
24 #define PRCC_PCLK_STORE(clk, base, bit) \ argument
25 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
26 #define PRCC_KCLK_STORE(clk, base, bit) \ argument
27 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
[all …]
|
| /openbmc/u-boot/drivers/clk/tegra/ |
| H A D | tegra-car-clk.c | 7 #include <clk-uclass.h>
12 static int tegra_car_clk_request(struct clk *clk) in tegra_car_clk_request() argument
14 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_request()
15 clk->id); in tegra_car_clk_request()
25 if (clk->id >= PERIPH_ID_COUNT) in tegra_car_clk_request()
31 static int tegra_car_clk_free(struct clk *clk) in tegra_car_clk_free() argument
33 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_free()
34 clk->id); in tegra_car_clk_free()
39 static ulong tegra_car_clk_get_rate(struct clk *clk) in tegra_car_clk_get_rate() argument
43 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_get_rate()
[all …]
|
| /openbmc/qemu/hw/misc/ |
| H A D | omap_clk.c | 27 struct clk { struct
30 struct clk *parent; argument
31 struct clk *child1; argument
32 struct clk *sibling; argument
42 int enabled; /* Is enabled, regardless of its input clk */ argument
50 static struct clk xtal_osc12m = { argument
56 static struct clk xtal_osc32k = {
62 static struct clk ck_ref = {
71 static struct clk dpll1 = {
78 static struct clk dpll2 = {
[all …]
|