| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | mpc52xx.h | 197 u32 jtag_id; /* CDM + 0x00 reg0 read only */
198 u32 rstcfg; /* CDM + 0x04 reg1 read only */
199 u32 breadcrumb; /* CDM + 0x08 reg2 */
201 u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
202 u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
203 u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
204 u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
206 u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
207 u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
208 u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
[all …]
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| /openbmc/linux/arch/powerpc/platforms/52xx/ |
| H A D | lite5200_pm.c | 14 static struct mpc52xx_cdm __iomem *cdm; variable
77 cdm = mbar + 0x200; in lite5200_pm_prepare()
102 _memcpy_fromio(&scdm, cdm, sizeof(*cdm)); in lite5200_save_regs()
137 /* CDM - Clock Distribution Module */ in lite5200_restore_regs()
138 out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel); in lite5200_restore_regs()
139 out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel); in lite5200_restore_regs()
141 out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en); in lite5200_restore_regs()
142 out_8(&cdm->fd_enable, scdm.fd_enable); in lite5200_restore_regs()
143 out_be16(&cdm->fd_counters, scdm.fd_counters); in lite5200_restore_regs()
145 out_be32(&cdm->clk_enables, scdm.clk_enables); in lite5200_restore_regs()
[all …]
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| H A D | lite5200.c | 34 { .compatible = "fsl,mpc5200-cdm", },
35 { .compatible = "mpc5200-cdm", },
56 struct mpc52xx_cdm __iomem *cdm; in lite5200_fix_clock_config() local
59 cdm = of_iomap(np, 0); in lite5200_fix_clock_config()
61 if (!cdm) { in lite5200_fix_clock_config()
68 out_8(&cdm->ext_48mhz_en, 0x00); in lite5200_fix_clock_config()
69 out_8(&cdm->fd_enable, 0x01); in lite5200_fix_clock_config()
70 if (in_be32(&cdm->rstcfg) & 0x40) /* Assumes 33Mhz clock */ in lite5200_fix_clock_config()
71 out_be16(&cdm->fd_counters, 0x0001); in lite5200_fix_clock_config()
73 out_be16(&cdm->fd_counters, 0x5555); in lite5200_fix_clock_config()
[all …]
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| H A D | mpc52xx_pm.c | 21 static struct mpc52xx_cdm __iomem *cdm; variable
90 cdm = mbar + 0x200; in mpc52xx_pm_prepare()
140 out_8(&cdm->ccs_sleep_enable, 1); in mpc52xx_pm_enter()
141 out_8(&cdm->osc_sleep_enable, 1); in mpc52xx_pm_enter()
142 out_8(&cdm->ccs_qreq_test, 1); in mpc52xx_pm_enter()
145 clk_enables = in_be32(&cdm->clk_enables); in mpc52xx_pm_enter()
146 out_be32(&cdm->clk_enables, clk_enables & 0x00088000); in mpc52xx_pm_enter()
162 mpc52xx_deep_sleep(sram, sdram, cdm, intr); in mpc52xx_pm_enter()
173 out_be32(&cdm->clk_enables, clk_enables); in mpc52xx_pm_enter()
174 out_8(&cdm->ccs_sleep_enable, 0); in mpc52xx_pm_enter()
[all …]
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| H A D | mpc52xx_common.c | 117 { .compatible = "fsl,mpc5200-cdm", },
118 { .compatible = "mpc5200-cdm", }, /* old */
169 * mpc52xx_set_psc_clkdiv: Set clock divider in the CDM for PSC ports
172 * @clkdiv: clock divider value to put into CDM PSC register.
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| H A D | mpc52xx_sleep.S | 10 mpc52xx_deep_sleep: /* args r3-r6: SRAM, SDRAM regs, CDM regs, INTR regs */
90 lwz r8, 0x14(r5) /* cdm->clkenable */
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| H A D | Kconfig | 18 - CDM configuration (clocking) is setup correctly by firmware,
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| H A D | mpc5200_simple.c | 14 * - CDM configuration (clocking) is setup correctly by firmware,
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| /openbmc/linux/drivers/spi/ |
| H A D | spi-ppc4xx.c | 100 * SCPClkOut = OPBCLK/(4(CDM + 1))
102 * CDM = (OPBCLK/4*SCPClkOut) - 1
105 u8 cdm; member
166 u8 cdm = 0; in spi_ppc4xx_setupxfer() local
193 cdm = min(scr, 0xff); in spi_ppc4xx_setupxfer()
195 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed); in spi_ppc4xx_setupxfer()
197 if (in_8(&hw->regs->cdm) != cdm) in spi_ppc4xx_setupxfer()
198 out_8(&hw->regs->cdm, cdm); in spi_ppc4xx_setupxfer()
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie-common.yaml | 24 configuration space belongs to the Configuration-Dependent Module (CDM)
28 CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such
254 snps,enable-cdm-check:
257 Enable automatic checking of CDM (Configuration Dependent Module)
258 registers for data corruption. CDM registers include standard PCIe
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| H A D | snps,dw-pcie-ep.yaml | 46 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
53 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
63 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
70 Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
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| H A D | snps,dw-pcie.yaml | 55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
79 Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
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| /openbmc/linux/drivers/net/can/mscan/ |
| H A D | mpc5xxx_can.c | 38 { .compatible = "fsl,mpc5200-cdm", },
46 struct mpc52xx_cdm __iomem *cdm; in mpc52xx_can_get_clock() local
79 cdm = of_iomap(np_cdm, 0); in mpc52xx_can_get_clock()
80 if (!cdm) { in mpc52xx_can_get_clock()
86 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
88 val = in_be32(&cdm->rstcfg); in mpc52xx_can_get_clock()
94 iounmap(cdm); in mpc52xx_can_get_clock()
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| /openbmc/linux/arch/powerpc/boot/dts/ |
| H A D | mpc5200b.dtsi | 50 cdm@200 {
51 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
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| H A D | tqm5200.dts | 49 cdm@200 {
50 compatible = "fsl,mpc5200-cdm";
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| H A D | charon.dts | 52 cdm@200 {
53 compatible = "fsl,mpc5200-cdm";
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| H A D | lite5200.dts | 49 cdm@200 {
50 compatible = "fsl,mpc5200-cdm";
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| H A D | a4m072.dts | 32 cdm@200 {
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| /openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_cfg.h | 100 struct mdp5_sub_block cdm; member
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| H A D | mdp5_cfg.c | 714 .cdm = {
909 .cdm = {
1000 .cdm = {
1102 .cdm = {
1200 .cdm = {
1298 .cdm = {
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| /openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpc5200.txt | 76 cdm@<addr> fsl,mpc5200-cdm Clock Distribution
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| /openbmc/linux/drivers/pci/controller/dwc/ |
| H A D | pcie-tegra194.c | 428 dev_info(pci->dev, "CDM check complete\n"); in tegra_pcie_rp_irq_handler()
432 dev_err(pci->dev, "CDM comparison mismatch\n"); in tegra_pcie_rp_irq_handler()
436 dev_err(pci->dev, "CDM Logic error\n"); in tegra_pcie_rp_irq_handler()
441 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", val); in tegra_pcie_rp_irq_handler()
1172 of_property_read_bool(np, "snps,enable-cdm-check"); in tegra_pcie_dw_parse_dt()
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| H A D | pcie-designware.c | 174 if (of_property_read_bool(np, "snps,enable-cdm-check")) in dw_pcie_get_resources()
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| /openbmc/linux/drivers/net/ethernet/mediatek/ |
| H A D | mtk_eth_soc.h | 160 /* GDM and CDM Threshold */
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| H A D | mtk_eth_soc.c | 3924 /* Indicates CDM to parse the MTK special tag from CPU in mtk_hw_init()
3955 /* GDM and CDM Threshold */ in mtk_hw_init()
3998 /* GDM and CDM Threshold */ in mtk_hw_init()
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