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/openbmc/linux/arch/arm/mm/
H A Dproc-arm1020.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
H A Dproc-arm926.S69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
134 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
H A Dproc-mohawk.S62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
63 mcr p15, 0, ip, c7, c10, 4 @ drain WB
64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
117 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer
138 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
[all …]
H A Dproc-arm925.S109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
110 mcr p15, 0, ip, c7, c10, 4 @ drain WB
112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
170 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
H A Dcache-fa.S44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
65 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
69 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
91 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
97 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
[all …]
H A Dproc-arm946.S57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
115 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
H A Dproc-arm920.S77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
78 mcr p15, 0, ip, c7, c10, 4 @ drain WB
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
H A Dproc-arm922.S79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
80 mcr p15, 0, ip, c7, c10, 4 @ drain WB
82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
H A Dcache-v6.S42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
66 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
136 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
143 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
[all …]
H A Dproc-fa526.S58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
110 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
[all …]
H A Dproc-feroceon.S73 mcr p15, 0, r0, c7, c10, 4 @ drain WB
95 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
96 mcr p15, 0, ip, c7, c10, 4 @ drain WB
98 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
116 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
127 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
153 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
161 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
162 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
H A Dproc-arm1022.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
H A Dproc-arm1026.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
146 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
148 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
H A Dproc-xsc3.S68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
137 mcr p14, 0, r0, c7, c0, 0 @ go to idle
149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
174 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
[all …]
H A Dproc-arm1020e.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
154 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
H A Dproc-xscale.S91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
156 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
160 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
179 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
191 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
215 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
216 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
[all …]
H A Dproc-arm940.S50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
52 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
112 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
120 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
162 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
[all …]
H A Dcache-v4wb.S58 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
77 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
94 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
111 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
116 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
117 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
122 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
163 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
164 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
169 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
H A Dcopypage-feroceon.c29 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
33 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
37 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
41 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
45 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
49 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
53 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
57 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_copy_user_page()
60 mcr p15, 0, %2, c7, c10, 4 @ drain WB" in feroceon_copy_user_page()
94 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ in feroceon_clear_user_highpage()
[all …]
H A Dproc-sa1100.S73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
74 mcr p15, 0, ip, c7, c10, 4 @ drain WB
76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
127 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
165 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
166 mcr p15, 0, r0, c7, c10, 4 @ drain WB
185 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
186 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
H A Dproc-arm720.S66 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
68 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
93 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
95 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
108 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
110 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
136 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
138 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
/openbmc/u-boot/arch/arm/cpu/arm11/
H A Dcpu.c47 asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i)); in cache_flush()
49 asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i)); in cache_flush()
51 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i)); in cache_flush()
57 asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); in invalidate_dcache_all()
62 asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0)); in flush_dcache_all()
63 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); in flush_dcache_all()
72 asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); in invalidate_dcache_range()
83 asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start)); in flush_dcache_range()
87 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); in flush_dcache_range()
/openbmc/linux/arch/arm/include/asm/hardware/
H A Dcp14.h49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
64 #define RCP14_DBGBVR7() MRC14(0, c0, c7, 4)
80 #define RCP14_DBGBCR7() MRC14(0, c0, c7, 5)
96 #define RCP14_DBGWVR7() MRC14(0, c0, c7, 6)
112 #define RCP14_DBGWCR7() MRC14(0, c0, c7, 7)
129 #define RCP14_DBGBXVR7() MRC14(0, c1, c7, 1)
144 #define RCP14_DBGITCTRL() MRC14(0, c7, c0, 4)
145 #define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6)
146 #define RCP14_DBGCLAIMCLR() MRC14(0, c7, c9, 6)
147 #define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6)
[all …]
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead.S731 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
732 mcr p15, 0, r0, c6, c7, 1
744 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
745 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
746 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
755 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
756 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
761 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
771 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
784 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/
H A Dcache.c12 asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); in invalidate_dcache_all()
19 "mrc p15, 0, r15, c7, c14, 3\n" in flush_dcache_all()
21 "mcr p15, 0, %0, c7, c10, 4\n" in flush_dcache_all()
32 asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start)); in invalidate_dcache_range()
43 asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start)); in flush_dcache_range()
47 asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0)); in flush_dcache_range()
75 asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i)); in invalidate_icache_all()

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