arm/mm/proc-feroceon.S

73 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
95 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
96 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
98 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
116 	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
117 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
127 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
153 2:	mcr	p15, 0, ip, c7, c14, 2		@ clean + invalidate D set/way
161 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
162 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
181 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
182 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
184 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
185 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
191 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
220 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
221 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
225 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
241 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
246 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
247 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
260 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
261 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
281 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
283 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
284 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
288 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
295 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
297 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
320 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
324 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
337 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
351 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
355 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
368 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
443 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
454 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
479 	mcreq	p15, 0, ip, c7, c5, 0		@ invalidate I cache
480 	mcreq	p15, 0, ip, c7, c10, 4		@ drain WB
483 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
499 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
504 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
523 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs
524 	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches
537 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
538 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
540 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4