1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2004 Texas Insturments
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2002
10 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
11 */
12
13 /*
14 * CPU specific code
15 */
16
17 #include <common.h>
18 #include <command.h>
19 #include <asm/system.h>
20
21 static void cache_flush(void);
22
cleanup_before_linux(void)23 int cleanup_before_linux (void)
24 {
25 /*
26 * this function is called just before we call linux
27 * it prepares the processor for linux
28 *
29 * we turn off caches etc ...
30 */
31
32 disable_interrupts ();
33
34 /* turn off I/D-cache */
35 icache_disable();
36 dcache_disable();
37 /* flush I/D-cache */
38 cache_flush();
39
40 return 0;
41 }
42
cache_flush(void)43 static void cache_flush(void)
44 {
45 unsigned long i = 0;
46 /* clean entire data cache */
47 asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
48 /* invalidate both caches and flush btb */
49 asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
50 /* mem barrier to sync things */
51 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
52 }
53
54 #ifndef CONFIG_SYS_DCACHE_OFF
invalidate_dcache_all(void)55 void invalidate_dcache_all(void)
56 {
57 asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
58 }
59
flush_dcache_all(void)60 void flush_dcache_all(void)
61 {
62 asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
63 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
64 }
65
invalidate_dcache_range(unsigned long start,unsigned long stop)66 void invalidate_dcache_range(unsigned long start, unsigned long stop)
67 {
68 if (!check_cache_range(start, stop))
69 return;
70
71 while (start < stop) {
72 asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
73 start += CONFIG_SYS_CACHELINE_SIZE;
74 }
75 }
76
flush_dcache_range(unsigned long start,unsigned long stop)77 void flush_dcache_range(unsigned long start, unsigned long stop)
78 {
79 if (!check_cache_range(start, stop))
80 return;
81
82 while (start < stop) {
83 asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
84 start += CONFIG_SYS_CACHELINE_SIZE;
85 }
86
87 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
88 }
89
90 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
invalidate_dcache_all(void)91 void invalidate_dcache_all(void)
92 {
93 }
94
flush_dcache_all(void)95 void flush_dcache_all(void)
96 {
97 }
98 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
99
100 #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
enable_caches(void)101 void enable_caches(void)
102 {
103 #ifndef CONFIG_SYS_ICACHE_OFF
104 icache_enable();
105 #endif
106 #ifndef CONFIG_SYS_DCACHE_OFF
107 dcache_enable();
108 #endif
109 }
110 #endif
111