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Searched full:ax45mp (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dandestech,ax45mp-cache.yaml5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
8 title: Andestech AX45MP L2 Cache Controller
23 - andestech,ax45mp-cache
31 - const: andestech,ax45mp-cache
73 compatible = "andestech,ax45mp-cache", "cache";
/openbmc/linux/drivers/cache/
H A DKconfig5 bool "Andes Technology AX45MP L2 Cache controller"
9 Support for the L2 cache controller on Andes Technology AX45MP platforms.
H A Dax45mp_cache.c3 * non-coherent cache functions for Andes AX45MP
175 { .compatible = "andestech,ax45mp-cache" },
194 * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size in ax45mp_cache_init()
/openbmc/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
/openbmc/linux/arch/riscv/
H A DKconfig.errata4 bool "Andes AX45MP errata"
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml35 - andestech,ax45mp
/openbmc/linux/
H A Dopengrok0.0.log[all...]