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/openbmc/linux/arch/x86/kvm/
H A Dlapic.c4 * Local APIC virtualization
69 static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);
70 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data);
77 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) in kvm_lapic_set_reg() argument
79 __kvm_lapic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
88 static __always_inline u64 kvm_lapic_get_reg64(struct kvm_lapic *apic, int reg) in kvm_lapic_get_reg64() argument
90 return __kvm_lapic_get_reg64(apic->regs, reg); in kvm_lapic_get_reg64()
99 static __always_inline void kvm_lapic_set_reg64(struct kvm_lapic *apic, in kvm_lapic_set_reg64() argument
102 __kvm_lapic_set_reg64(apic->regs, reg, val); in kvm_lapic_set_reg64()
112 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_pending_eoi() local
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H A Dlapic.h74 * APIC register page. The layout matches the register layout seen by
113 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
120 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
139 int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
149 u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
164 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) in kvm_lapic_set_irr() argument
166 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR); in kvm_lapic_set_irr()
171 apic->irr_pending = true; in kvm_lapic_set_irr()
179 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) in kvm_lapic_get_reg() argument
181 return __kvm_lapic_get_reg(apic->regs, reg_off); in kvm_lapic_get_reg()
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/openbmc/qemu/target/i386/
H A Dcpu-apic.c2 * QEMU x86 CPU <-> APIC
24 const char *apic_type = "apic"; in apic_get_class()
29 error_setg(errp, "KVM does not support userspace APIC"); in apic_get_class()
32 apic_type = "kvm-apic"; in apic_get_class()
34 apic_type = "xen-apic"; in apic_get_class()
36 apic_type = "whpx-apic"; in apic_get_class()
44 APICCommonState *apic; in x86_cpu_apic_create() local
57 apic = APIC_COMMON(cpu->apic_state); in x86_cpu_apic_create()
58 apic->cpu = cpu; in x86_cpu_apic_create()
59 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; in x86_cpu_apic_create()
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/openbmc/linux/arch/x86/kernel/apic/
H A Dinit.c2 #define pr_fmt(fmt) "APIC: " fmt
4 #include <asm/apic.h>
15 DEFINE_STATIC_CALL_NULL(apic_call_##__cb, *apic->__cb)
41 apic->__cb = __x86_apic_override.__cb
62 static_call_update(apic_call_##__cb, *apic->__cb)
85 /* Ensure that the default APIC has native_eoi populated */ in apic_setup_apic_calls()
86 apic->native_eoi = apic->eoi; in apic_setup_apic_calls()
91 void __init apic_install_driver(struct apic *driver) in apic_install_driver()
93 if (apic == driver) in apic_install_driver()
96 apic = driver; in apic_install_driver()
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H A Dapic.c3 * Local APIC handling, local APIC timers
13 * Mikael Pettersson : Power Management for UP-APIC.
52 #include <asm/apic.h>
99 * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID
112 * Map cpu index to physical APIC ID
120 /* Local APIC was disabled by the BIOS and enabled by the kernel */
127 * local APIC. Before entering Symmetric I/O Mode, either
133 /* NMI and 8259 INTR go through APIC */ in imcr_pic_to_apic()
145 * Knob to control our willingness to enable the local APIC.
152 * APIC command line parameters
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H A Dio_apic.c3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
25 * - SiS APIC rmw bug:
67 #include <asm/apic.h>
90 int apic, pin; member
116 /* I/O APIC config */
118 /* IO APIC gsi routing info */
197 /* disable IO-APIC */ in parse_noapic()
209 " IRQ %02x, APIC ID %x, APIC INT %02x\n", in mp_save_irq()
269 static inline void io_apic_eoi(unsigned int apic, unsigned int vector) in io_apic_eoi() argument
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H A Dapic_flat_64.c5 * Flat APIC subarch code.
16 #include <asm/apic.h>
20 static struct apic apic_physflat;
21 static struct apic apic_flat;
23 struct apic *apic __ro_after_init = &apic_flat;
24 EXPORT_SYMBOL_GPL(apic);
79 static struct apic apic_flat __ro_after_init = {
125 * Quirk: some x86_64 machines can only use physical APIC mode in physflat_acpi_madt_oem_check()
131 printk(KERN_DEBUG "system APIC only can use physical flat"); in physflat_acpi_madt_oem_check()
136 printk(KERN_DEBUG "IBM Summit detected, will use apic physical"); in physflat_acpi_madt_oem_check()
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H A Dprobe_32.c3 * Default generic APIC driver. This handles up to 8 CPUs.
7 * Generic x86 APIC driver probe layer.
16 #include <asm/apic.h>
32 static struct apic apic_default __ro_after_init = {
72 struct apic *apic __ro_after_init = &apic_default;
73 EXPORT_SYMBOL_GPL(apic);
78 struct apic **drv; in parse_apic()
94 early_param("apic", parse_apic);
128 struct apic **drv; in x86_32_probe_apic()
138 panic("Didn't find an APIC driver"); in x86_32_probe_apic()
H A Dapic_noop.c3 * NOOP APIC driver.
5 * Does almost nothing and should be substituted by a real apic driver via
8 * Though in case if apic is disabled (for some reason) we try
9 * to not uglify the caller's code and allow to call (some) apic routines
14 * APIC::read/write() have a WARN_ON_ONCE() in them. Sigh...
19 #include <asm/apic.h>
45 struct apic apic_noop __ro_after_init = {
H A Dbigsmp_32.c3 * APIC driver for "bigsmp" xAPIC machines with more than 8 virtual CPUs.
5 * Drives the local APIC in "clustered mode".
11 #include <asm/apic.h>
51 printk(KERN_NOTICE "%s detected: force use of apic=bigsmp\n", d->ident); in hp_ht_bigsmp()
78 static struct apic apic_bigsmp __ro_after_init = {
117 return apic == &apic_bigsmp || !cmdline_override; in apic_bigsmp_possible()
122 if (apic != &apic_bigsmp) in apic_bigsmp_force()
H A Dprobe_64.c5 * Generic APIC sub-arch probe layer.
12 #include <asm/apic.h>
16 /* Select the appropriate APIC driver */
19 struct apic **drv; in x86_64_probe_apic()
33 struct apic **drv; in default_acpi_madt_oem_check()
H A Dvector.c3 * Local APIC related interfaces to support IOAPIC, MSI, etc.
6 * Moved from arch/x86/kernel/apic/io_apic.c.
19 #include <asm/apic.h>
136 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); in apic_update_irq_cfg()
665 return fwname && !strncmp(fwname, "IO-APIC-", 8) && in x86_fwspec_is_ioapic()
691 * if IRQ remapping is enabled. APIC IDs above 15 bits are in x86_vector_select()
756 * If the IO/APIC is disabled via config, kernel command line or in lapic_update_legacy_vectors()
786 * in the IO/APIC code. in lapic_assign_system_vectors()
832 /* Online the local APIC infrastructure and initialize the vectors */
926 .name = "APIC",
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H A DMakefile3 # Makefile for local APIC drivers and for the IO-APIC code
10 obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_common.o apic_noop.o ipi.o vector.o init.o
18 # APIC probe will depend on the listing order here
26 # APIC probe will depend on the listing order here
H A Dapic_numachip.c6 * Numascale NumaConnect-Specific APIC Code
24 static const struct apic apic_numachip1;
25 static const struct apic apic_numachip2;
91 /* Send via local APIC where non-local part matches */ in numachip_send_IPI_one()
151 return apic == &apic_numachip1; in numachip1_probe()
156 return apic == &apic_numachip2; in numachip2_probe()
220 static const struct apic apic_numachip1 __refconst = {
257 static const struct apic apic_numachip2 __refconst = {
/openbmc/openbmc/poky/meta/recipes-devtools/qemu/qemu/
H A D0002-apic-fixup-fallthrough-to-PIC.patch4 Subject: [PATCH] apic: fixup fallthrough to PIC
7 interrupts through the local APIC if the local APIC config says so.]
8 missed a check to ensure the local APIC is enabled. Since if the local
9 APIC is disabled it doesn't matter what the local APIC config says.
11 If this check isn't done and the guest has disabled the local APIC the
19 (with the local APIC disabled apic_get_interrupt() returns -1).
28 hw/intc/apic.c | 2 +-
31 diff --git a/hw/intc/apic.c b/hw/intc/apic.c
33 --- a/hw/intc/apic.c
34 +++ b/hw/intc/apic.c
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/openbmc/qemu/hw/intc/
H A Dapic.c2 * APIC support
23 #include "hw/i386/apic.h"
31 #include "hw/i386/apic-msidef.h"
43 #define TYPE_APIC "apic"
45 DECLARE_INSTANCE_CHECKER(APICCommonState, APIC,
57 /* round up the max apic id to next multiple of words */ in apic_set_max_apic_id()
185 APICCommonState *s = APIC(dev); in apic_deliver_pic_intr()
210 #define foreach_apic(apic, deliver_bitmask, code) \ argument
218 apic = local_apics[__i * 32 + __j];\
219 if (apic) {\
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/openbmc/linux/arch/x86/include/asm/
H A Dapic.h34 * This can be turned up by using apic=verbose for more
35 * information and apic=debug for _lots_ of information.
36 * apic_verbosity is defined in apic.c
70 * With 82489DX we can't rely on apic feature bit
72 * such an apic chip so we assume that SMP configuration
252 * Generic APIC sub-arch data struct.
258 struct apic { struct
288 /* The limit of the APIC ID space. */
331 * Pointer to the local APIC driver in use on this system (there's
335 extern struct apic *apic;
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dintel,ce4100-ioapic.yaml7 title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
16 into the processor itself and an external I/O APIC. Local APIC
18 from internal sources and from an external I/O APIC (ioapic).
26 This schema defines bindings for I/O APIC interrupt controller.
H A Dintel,ce4100-lapic.yaml13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
16 into the processor itself and an external I/O APIC. Local APIC
18 from internal sources and from an external I/O APIC (ioapic).
26 This schema defines bindings for local APIC interrupt controller.
/openbmc/linux/drivers/iommu/
H A Dhyperv-iommu.c17 #include <asm/apic.h>
30 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
31 * Redirection Table. Hyper-V exposes one single IO-APIC and so define
32 * 24 IO APIC remmapping entries.
89 * Hypver-V IO APIC irq affinity should be in the scope of in hyperv_irq_remapping_alloc()
107 /* Claim the only I/O APIC emulated by Hyper-V */ in hyperv_irq_remapping_select()
159 * IO-APIC and so IO-APIC only accepts 8-bit APIC ID. in hyperv_prepare_irq_remapping()
160 * Cpu's APIC ID is read from ACPI MADT table and APIC IDs in hyperv_prepare_irq_remapping()
162 * APIC ID reflects cpu topology. There maybe some APIC ID in hyperv_prepare_irq_remapping()
165 * into ioapic_max_cpumask if its APIC ID is less than 256. in hyperv_prepare_irq_remapping()
/openbmc/u-boot/arch/x86/include/asm/
H A Dacpi_table.h222 /* MADT (Multiple APIC Description Table) */
225 u32 lapic_addr; /* Local APIC address */
226 u32 flags; /* Multiple APIC flags */
229 /* MADT: APIC Structure Type*/
231 ACPI_APIC_LAPIC = 0, /* Processor local APIC */
232 ACPI_APIC_IOAPIC, /* I/O APIC */
235 ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */
236 ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */
244 /* MADT: Processor Local APIC Structure */
252 u8 apic_id; /* Local APIC ID */
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H A Dmpspec.h45 u32 mpc_lapic; /* Local APIC address */
318 * mp_write_ioapic() - Write an I/O APIC entry
320 * This writes an I/O APIC entry to the configuration table.
323 * @id: I/O APIC id
324 * @ver: I/O APIC version
325 * @apicaddr: I/O APIC address
339 * @dstapic: destination I/O APIC id where the interrupt goes to
340 * @dstirq: destination I/O APIC pin where the interrupt goes to
355 * @dstapic: destination I/O APIC id where the interrupt goes to
356 * @dstirq: destination I/O APIC pin where the interrupt goes to
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/openbmc/linux/Documentation/arch/x86/i386/
H A DIO-APIC.rst4 IO-APIC
9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
12 IO-APIC, interrupts from hardware will be delivered only to the
23 If your box boots fine with enabled IO-APIC IRQs, then your
28 0: 1360293 IO-APIC-edge timer
29 1: 4 IO-APIC-edge keyboard
32 14: 1448 IO-APIC-edge ide0
33 16: 28232 IO-APIC-level Intel EtherExpress Pro 10/100 Ethernet
34 17: 51304 IO-APIC-level eth0
97 board does not do default daisy-chaining. (or the IO-APIC has the PIRQ pins
/openbmc/linux/arch/x86/kernel/
H A Dirqinit.c27 #include <asm/apic.h>
34 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
39 * The IO-APIC gives us many more interrupt sources. Most of these
44 * IO-APIC registers.
59 * Try to set up the through-local-APIC virtual wire mode earlier. in init_ISA_irqs()
61 * On some 32-bit UP machines, whose APIC has been disabled by BIOS in init_ISA_irqs()
82 * these IRQs are handled by more modern controllers like IO-APIC, in init_IRQ()
/openbmc/qemu/hw/i386/
H A Dacpi-common.c39 /* Flags – Local APIC Flags */ in pc_madt_cpu_entry()
50 /* Rev 1.0b, Table 5-13 Processor Local APIC Structure */ in pc_madt_cpu_entry()
54 build_append_int_noprefix(entry, apic_id, 1); /* APIC ID */ in pc_madt_cpu_entry()
69 /* Rev 1.0b, 5.2.8.2 IO APIC */ in build_ioapic()
72 build_append_int_noprefix(entry, id, 1); /* IO APIC ID */ in build_ioapic()
74 build_append_int_noprefix(entry, addr, 4); /* IO APIC Address */ in build_ioapic()
93 * 5.2.8 Multiple APIC Description Table
104 AcpiTable table = { .sig = "APIC", .rev = 3, .oem_id = oem_id, in acpi_build_madt()
108 /* Local APIC Address */ in acpi_build_madt()
153 /* Rev 1.0b, 5.2.8.3.3 Local APIC NMI */ in acpi_build_madt()
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