Lines Matching full:apic
4 * Local APIC virtualization
69 static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);
70 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data);
77 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) in kvm_lapic_set_reg() argument
79 __kvm_lapic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
88 static __always_inline u64 kvm_lapic_get_reg64(struct kvm_lapic *apic, int reg) in kvm_lapic_get_reg64() argument
90 return __kvm_lapic_get_reg64(apic->regs, reg); in kvm_lapic_get_reg64()
99 static __always_inline void kvm_lapic_set_reg64(struct kvm_lapic *apic, in kvm_lapic_set_reg64() argument
102 __kvm_lapic_set_reg64(apic->regs, reg, val); in kvm_lapic_set_reg64()
112 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_pending_eoi() local
114 return apic_test_vector(vector, apic->regs + APIC_ISR) || in kvm_apic_pending_eoi()
115 apic_test_vector(vector, apic->regs + APIC_IRR); in kvm_apic_pending_eoi()
131 static inline int apic_enabled(struct kvm_lapic *apic) in apic_enabled() argument
133 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); in apic_enabled()
143 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) in kvm_x2apic_id() argument
145 return apic->vcpu->vcpu_id; in kvm_x2apic_id()
222 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_recalculate_phys_map() local
223 u32 x2apic_id = kvm_x2apic_id(apic); in kvm_recalculate_phys_map()
224 u32 xapic_id = kvm_xapic_id(apic); in kvm_recalculate_phys_map()
236 * Bail if a vCPU was added and/or enabled its APIC between allocating in kvm_recalculate_phys_map()
245 * Deliberately truncate the vCPU ID when detecting a mismatched APIC in kvm_recalculate_phys_map()
250 if (!apic_x2apic_mode(apic) && xapic_id != (u8)vcpu->vcpu_id) in kvm_recalculate_phys_map()
254 * Apply KVM's hotplug hack if userspace has enable 32-bit APIC IDs. in kvm_recalculate_phys_map()
261 * userspace has not enabled 32-bit x2APIC IDs. Each APIC is supposed in kvm_recalculate_phys_map()
263 * effective APIC ID, e.g. due to the x2APIC wrap or because the guest in kvm_recalculate_phys_map()
269 if (apic_x2apic_mode(apic) || x2apic_id > 0xff) in kvm_recalculate_phys_map()
270 new->phys_map[x2apic_id] = apic; in kvm_recalculate_phys_map()
272 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) in kvm_recalculate_phys_map()
273 new->phys_map[xapic_id] = apic; in kvm_recalculate_phys_map()
276 * Disable the optimized map if the physical APIC ID is already in kvm_recalculate_phys_map()
280 if (apic_x2apic_mode(apic)) in kvm_recalculate_phys_map()
288 new->phys_map[physical_id] = apic; in kvm_recalculate_phys_map()
297 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_recalculate_logical_map() local
306 if (!kvm_apic_sw_enabled(apic)) in kvm_recalculate_logical_map()
309 ldr = kvm_lapic_get_reg(apic, APIC_LDR); in kvm_recalculate_logical_map()
313 if (apic_x2apic_mode(apic)) { in kvm_recalculate_logical_map()
317 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) in kvm_recalculate_logical_map()
341 if (apic_x2apic_mode(apic)) in kvm_recalculate_logical_map()
357 cluster[ldr] = apic; in kvm_recalculate_logical_map()
386 "Dirty APIC map without an in-kernel local APIC"); in kvm_recalculate_apic_map()
393 * or the APIC registers (if dirty). Note, on retry the map may have in kvm_recalculate_apic_map()
410 * with the highest x2APIC ID is toggling its APIC on and off. in kvm_recalculate_apic_map()
416 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); in kvm_recalculate_apic_map()
471 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty. in kvm_recalculate_apic_map()
484 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) in apic_set_spiv() argument
488 kvm_lapic_set_reg(apic, APIC_SPIV, val); in apic_set_spiv()
490 if (enabled != apic->sw_enabled) { in apic_set_spiv()
491 apic->sw_enabled = enabled; in apic_set_spiv()
497 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in apic_set_spiv()
502 kvm_make_request(KVM_REQ_APF_READY, apic->vcpu); in apic_set_spiv()
503 kvm_xen_sw_enable_lapic(apic->vcpu); in apic_set_spiv()
507 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id) in kvm_apic_set_xapic_id() argument
509 kvm_lapic_set_reg(apic, APIC_ID, id << 24); in kvm_apic_set_xapic_id()
510 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_xapic_id()
513 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) in kvm_apic_set_ldr() argument
515 kvm_lapic_set_reg(apic, APIC_LDR, id); in kvm_apic_set_ldr()
516 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_ldr()
519 static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val) in kvm_apic_set_dfr() argument
521 kvm_lapic_set_reg(apic, APIC_DFR, val); in kvm_apic_set_dfr()
522 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_dfr()
525 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id) in kvm_apic_set_x2apic_id() argument
529 WARN_ON_ONCE(id != apic->vcpu->vcpu_id); in kvm_apic_set_x2apic_id()
531 kvm_lapic_set_reg(apic, APIC_ID, id); in kvm_apic_set_x2apic_id()
532 kvm_lapic_set_reg(apic, APIC_LDR, ldr); in kvm_apic_set_x2apic_id()
533 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_x2apic_id()
536 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) in apic_lvt_enabled() argument
538 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); in apic_lvt_enabled()
541 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) in apic_lvtt_oneshot() argument
543 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; in apic_lvtt_oneshot()
546 static inline int apic_lvtt_period(struct kvm_lapic *apic) in apic_lvtt_period() argument
548 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; in apic_lvtt_period()
551 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) in apic_lvtt_tscdeadline() argument
553 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; in apic_lvtt_tscdeadline()
561 static inline bool kvm_lapic_lvt_supported(struct kvm_lapic *apic, int lvt_index) in kvm_lapic_lvt_supported() argument
563 return apic->nr_lvt_entries > lvt_index; in kvm_lapic_lvt_supported()
573 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_version() local
579 v = APIC_VERSION | ((apic->nr_lvt_entries - 1) << 16); in kvm_apic_set_version()
591 kvm_lapic_set_reg(apic, APIC_LVR, v); in kvm_apic_set_version()
597 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_after_set_mcg_cap() local
600 if (!lapic_in_kernel(vcpu) || nr_lvt_entries == apic->nr_lvt_entries) in kvm_apic_after_set_mcg_cap()
604 for (i = apic->nr_lvt_entries; i < nr_lvt_entries; i++) in kvm_apic_after_set_mcg_cap()
605 kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED); in kvm_apic_after_set_mcg_cap()
607 apic->nr_lvt_entries = nr_lvt_entries; in kvm_apic_after_set_mcg_cap()
690 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_irr() local
691 bool irr_updated = __kvm_apic_update_irr(pir, apic->regs, max_irr); in kvm_apic_update_irr()
693 if (unlikely(!apic->apicv_active && irr_updated)) in kvm_apic_update_irr()
694 apic->irr_pending = true; in kvm_apic_update_irr()
699 static inline int apic_search_irr(struct kvm_lapic *apic) in apic_search_irr() argument
701 return find_highest_vector(apic->regs + APIC_IRR); in apic_search_irr()
704 static inline int apic_find_highest_irr(struct kvm_lapic *apic) in apic_find_highest_irr() argument
712 if (!apic->irr_pending) in apic_find_highest_irr()
715 result = apic_search_irr(apic); in apic_find_highest_irr()
721 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) in apic_clear_irr() argument
723 if (unlikely(apic->apicv_active)) { in apic_clear_irr()
725 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
726 static_call_cond(kvm_x86_hwapic_irr_update)(apic->vcpu, in apic_clear_irr()
727 apic_find_highest_irr(apic)); in apic_clear_irr()
729 apic->irr_pending = false; in apic_clear_irr()
730 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
731 if (apic_search_irr(apic) != -1) in apic_clear_irr()
732 apic->irr_pending = true; in apic_clear_irr()
738 apic_clear_irr(vec, vcpu->arch.apic); in kvm_apic_clear_irr()
742 static inline void apic_set_isr(int vec, struct kvm_lapic *apic) in apic_set_isr() argument
744 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) in apic_set_isr()
748 * With APIC virtualization enabled, all caching is disabled in apic_set_isr()
752 if (unlikely(apic->apicv_active)) in apic_set_isr()
755 ++apic->isr_count; in apic_set_isr()
756 BUG_ON(apic->isr_count > MAX_APIC_VECTOR); in apic_set_isr()
762 apic->highest_isr_cache = vec; in apic_set_isr()
766 static inline int apic_find_highest_isr(struct kvm_lapic *apic) in apic_find_highest_isr() argument
772 * is always -1, with APIC virtualization enabled. in apic_find_highest_isr()
774 if (!apic->isr_count) in apic_find_highest_isr()
776 if (likely(apic->highest_isr_cache != -1)) in apic_find_highest_isr()
777 return apic->highest_isr_cache; in apic_find_highest_isr()
779 result = find_highest_vector(apic->regs + APIC_ISR); in apic_find_highest_isr()
785 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) in apic_clear_isr() argument
787 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) in apic_clear_isr()
791 * We do get here for APIC virtualization enabled if the guest in apic_clear_isr()
792 * uses the Hyper-V APIC enlightenment. In this case we may need in apic_clear_isr()
797 if (unlikely(apic->apicv_active)) in apic_clear_isr()
798 static_call_cond(kvm_x86_hwapic_isr_update)(apic_find_highest_isr(apic)); in apic_clear_isr()
800 --apic->isr_count; in apic_clear_isr()
801 BUG_ON(apic->isr_count < 0); in apic_clear_isr()
802 apic->highest_isr_cache = -1; in apic_clear_isr()
813 return apic_find_highest_irr(vcpu->arch.apic); in kvm_lapic_find_highest_irr()
817 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
824 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_irq() local
826 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, in kvm_apic_set_irq()
930 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr) in apic_has_interrupt_for_ppr() argument
934 highest_irr = static_call(kvm_x86_sync_pir_to_irr)(apic->vcpu); in apic_has_interrupt_for_ppr()
936 highest_irr = apic_find_highest_irr(apic); in apic_has_interrupt_for_ppr()
942 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr) in __apic_update_ppr() argument
947 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); in __apic_update_ppr()
948 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); in __apic_update_ppr()
949 isr = apic_find_highest_isr(apic); in __apic_update_ppr()
959 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); in __apic_update_ppr()
964 static void apic_update_ppr(struct kvm_lapic *apic) in apic_update_ppr() argument
968 if (__apic_update_ppr(apic, &ppr) && in apic_update_ppr()
969 apic_has_interrupt_for_ppr(apic, ppr) != -1) in apic_update_ppr()
970 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_update_ppr()
975 apic_update_ppr(vcpu->arch.apic); in kvm_apic_update_ppr()
979 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) in apic_set_tpr() argument
981 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); in apic_set_tpr()
982 apic_update_ppr(apic); in apic_set_tpr()
985 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) in kvm_apic_broadcast() argument
987 return mda == (apic_x2apic_mode(apic) ? in kvm_apic_broadcast()
991 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) in kvm_apic_match_physical_addr() argument
993 if (kvm_apic_broadcast(apic, mda)) in kvm_apic_match_physical_addr()
998 * were in x2APIC mode if the target APIC ID can't be encoded as an in kvm_apic_match_physical_addr()
1000 * start in xAPIC mode) with an APIC ID that is unaddressable in xAPIC in kvm_apic_match_physical_addr()
1001 * mode. Match the x2APIC ID if and only if the target APIC ID can't in kvm_apic_match_physical_addr()
1005 if (apic_x2apic_mode(apic) || mda > 0xff) in kvm_apic_match_physical_addr()
1006 return mda == kvm_x2apic_id(apic); in kvm_apic_match_physical_addr()
1008 return mda == kvm_xapic_id(apic); in kvm_apic_match_physical_addr()
1011 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) in kvm_apic_match_logical_addr() argument
1015 if (kvm_apic_broadcast(apic, mda)) in kvm_apic_match_logical_addr()
1018 logical_id = kvm_lapic_get_reg(apic, APIC_LDR); in kvm_apic_match_logical_addr()
1020 if (apic_x2apic_mode(apic)) in kvm_apic_match_logical_addr()
1026 switch (kvm_lapic_get_reg(apic, APIC_DFR)) { in kvm_apic_match_logical_addr()
1037 /* The KVM local APIC implementation has two quirks:
1068 struct kvm_lapic *target = vcpu->arch.apic; in kvm_apic_match_dest()
1289 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, in __apic_accept_irq() argument
1294 struct kvm_vcpu *vcpu = apic->vcpu; in __apic_accept_irq()
1307 if (unlikely(!apic_enabled(apic))) in __apic_accept_irq()
1317 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { in __apic_accept_irq()
1320 apic->regs + APIC_TMR); in __apic_accept_irq()
1323 apic->regs + APIC_TMR); in __apic_accept_irq()
1326 static_call(kvm_x86_deliver_interrupt)(apic, delivery_mode, in __apic_accept_irq()
1354 apic->pending_events = (1UL << KVM_APIC_INIT); in __apic_accept_irq()
1362 apic->sipi_vector = vector; in __apic_accept_irq()
1365 set_bit(KVM_APIC_SIPI, &apic->pending_events); in __apic_accept_irq()
1435 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) in kvm_ioapic_handles_vector() argument
1437 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); in kvm_ioapic_handles_vector()
1440 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) in kvm_ioapic_send_eoi() argument
1445 if (!kvm_ioapic_handles_vector(apic, vector)) in kvm_ioapic_send_eoi()
1449 if (irqchip_split(apic->vcpu->kvm)) { in kvm_ioapic_send_eoi()
1450 apic->vcpu->arch.pending_ioapic_eoi = vector; in kvm_ioapic_send_eoi()
1451 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); in kvm_ioapic_send_eoi()
1455 if (apic_test_vector(vector, apic->regs + APIC_TMR)) in kvm_ioapic_send_eoi()
1460 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); in kvm_ioapic_send_eoi()
1463 static int apic_set_eoi(struct kvm_lapic *apic) in apic_set_eoi() argument
1465 int vector = apic_find_highest_isr(apic); in apic_set_eoi()
1467 trace_kvm_eoi(apic, vector); in apic_set_eoi()
1476 apic_clear_isr(vector, apic); in apic_set_eoi()
1477 apic_update_ppr(apic); in apic_set_eoi()
1479 if (to_hv_vcpu(apic->vcpu) && in apic_set_eoi()
1480 test_bit(vector, to_hv_synic(apic->vcpu)->vec_bitmap)) in apic_set_eoi()
1481 kvm_hv_synic_send_eoi(apic->vcpu, vector); in apic_set_eoi()
1483 kvm_ioapic_send_eoi(apic, vector); in apic_set_eoi()
1484 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_set_eoi()
1494 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_eoi_accelerated() local
1496 trace_kvm_eoi(apic, vector); in kvm_apic_set_eoi_accelerated()
1498 kvm_ioapic_send_eoi(apic, vector); in kvm_apic_set_eoi_accelerated()
1499 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in kvm_apic_set_eoi_accelerated()
1503 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high) in kvm_apic_send_ipi() argument
1517 if (apic_x2apic_mode(apic)) in kvm_apic_send_ipi()
1524 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); in kvm_apic_send_ipi()
1528 static u32 apic_get_tmcct(struct kvm_lapic *apic) in apic_get_tmcct() argument
1533 ASSERT(apic != NULL); in apic_get_tmcct()
1536 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || in apic_get_tmcct()
1537 apic->lapic_timer.period == 0) in apic_get_tmcct()
1541 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in apic_get_tmcct()
1545 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); in apic_get_tmcct()
1546 return div64_u64(ns, (APIC_BUS_CYCLE_NS * apic->divide_count)); in apic_get_tmcct()
1549 static void __report_tpr_access(struct kvm_lapic *apic, bool write) in __report_tpr_access() argument
1551 struct kvm_vcpu *vcpu = apic->vcpu; in __report_tpr_access()
1559 static inline void report_tpr_access(struct kvm_lapic *apic, bool write) in report_tpr_access() argument
1561 if (apic->vcpu->arch.tpr_access_reporting) in report_tpr_access()
1562 __report_tpr_access(apic, write); in report_tpr_access()
1565 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) in __apic_read() argument
1577 if (apic_lvtt_tscdeadline(apic)) in __apic_read()
1580 val = apic_get_tmcct(apic); in __apic_read()
1583 apic_update_ppr(apic); in __apic_read()
1584 val = kvm_lapic_get_reg(apic, offset); in __apic_read()
1587 report_tpr_access(apic, false); in __apic_read()
1590 val = kvm_lapic_get_reg(apic, offset); in __apic_read()
1606 u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic) in kvm_lapic_readable_reg_mask() argument
1631 if (kvm_lapic_lvt_supported(apic, LVT_CMCI)) in kvm_lapic_readable_reg_mask()
1635 if (!apic_x2apic_mode(apic)) in kvm_lapic_readable_reg_mask()
1644 static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, in kvm_lapic_reg_read() argument
1654 WARN_ON_ONCE(apic_x2apic_mode(apic) && offset == APIC_ICR); in kvm_lapic_reg_read()
1660 !(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset))) in kvm_lapic_reg_read()
1663 result = __apic_read(apic, offset & ~0xf); in kvm_lapic_reg_read()
1674 printk(KERN_ERR "Local APIC read with len = %x, " in kvm_lapic_reg_read()
1681 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) in apic_mmio_in_range() argument
1683 return addr >= apic->base_address && in apic_mmio_in_range()
1684 addr < apic->base_address + LAPIC_MMIO_LENGTH; in apic_mmio_in_range()
1690 struct kvm_lapic *apic = to_lapic(this); in apic_mmio_read() local
1691 u32 offset = address - apic->base_address; in apic_mmio_read()
1693 if (!apic_mmio_in_range(apic, address)) in apic_mmio_read()
1696 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { in apic_mmio_read()
1705 kvm_lapic_reg_read(apic, offset, len, data); in apic_mmio_read()
1710 static void update_divide_count(struct kvm_lapic *apic) in update_divide_count() argument
1714 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); in update_divide_count()
1717 apic->divide_count = 0x1 << (tmp2 & 0x7); in update_divide_count()
1720 static void limit_periodic_timer_frequency(struct kvm_lapic *apic) in limit_periodic_timer_frequency() argument
1727 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in limit_periodic_timer_frequency()
1730 if (apic->lapic_timer.period < min_period) { in limit_periodic_timer_frequency()
1734 apic->vcpu->vcpu_id, in limit_periodic_timer_frequency()
1735 apic->lapic_timer.period, min_period); in limit_periodic_timer_frequency()
1736 apic->lapic_timer.period = min_period; in limit_periodic_timer_frequency()
1741 static void cancel_hv_timer(struct kvm_lapic *apic);
1743 static void cancel_apic_timer(struct kvm_lapic *apic) in cancel_apic_timer() argument
1745 hrtimer_cancel(&apic->lapic_timer.timer); in cancel_apic_timer()
1747 if (apic->lapic_timer.hv_timer_in_use) in cancel_apic_timer()
1748 cancel_hv_timer(apic); in cancel_apic_timer()
1750 atomic_set(&apic->lapic_timer.pending, 0); in cancel_apic_timer()
1753 static void apic_update_lvtt(struct kvm_lapic *apic) in apic_update_lvtt() argument
1755 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & in apic_update_lvtt()
1756 apic->lapic_timer.timer_mode_mask; in apic_update_lvtt()
1758 if (apic->lapic_timer.timer_mode != timer_mode) { in apic_update_lvtt()
1759 if (apic_lvtt_tscdeadline(apic) != (timer_mode == in apic_update_lvtt()
1761 cancel_apic_timer(apic); in apic_update_lvtt()
1762 kvm_lapic_set_reg(apic, APIC_TMICT, 0); in apic_update_lvtt()
1763 apic->lapic_timer.period = 0; in apic_update_lvtt()
1764 apic->lapic_timer.tscdeadline = 0; in apic_update_lvtt()
1766 apic->lapic_timer.timer_mode = timer_mode; in apic_update_lvtt()
1767 limit_periodic_timer_frequency(apic); in apic_update_lvtt()
1778 struct kvm_lapic *apic = vcpu->arch.apic; in lapic_timer_int_injected() local
1779 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); in lapic_timer_int_injected()
1781 if (kvm_apic_hw_enabled(apic)) { in lapic_timer_int_injected()
1783 void *bitmap = apic->regs + APIC_ISR; in lapic_timer_int_injected()
1785 if (apic->apicv_active) in lapic_timer_int_injected()
1786 bitmap = apic->regs + APIC_IRR; in lapic_timer_int_injected()
1796 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns; in __wait_lapic_expire()
1817 struct kvm_lapic *apic = vcpu->arch.apic; in adjust_lapic_timer_advance() local
1818 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns; in adjust_lapic_timer_advance()
1840 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in adjust_lapic_timer_advance()
1845 struct kvm_lapic *apic = vcpu->arch.apic; in __kvm_wait_lapic_expire() local
1848 tsc_deadline = apic->lapic_timer.expired_tscdeadline; in __kvm_wait_lapic_expire()
1849 apic->lapic_timer.expired_tscdeadline = 0; in __kvm_wait_lapic_expire()
1871 vcpu->arch.apic->lapic_timer.expired_tscdeadline && in kvm_wait_lapic_expire()
1872 vcpu->arch.apic->lapic_timer.timer_advance_ns && in kvm_wait_lapic_expire()
1878 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic) in kvm_apic_inject_pending_timer_irqs() argument
1880 struct kvm_timer *ktimer = &apic->lapic_timer; in kvm_apic_inject_pending_timer_irqs()
1882 kvm_apic_local_deliver(apic, APIC_LVTT); in kvm_apic_inject_pending_timer_irqs()
1883 if (apic_lvtt_tscdeadline(apic)) { in kvm_apic_inject_pending_timer_irqs()
1885 } else if (apic_lvtt_oneshot(apic)) { in kvm_apic_inject_pending_timer_irqs()
1891 static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn) in apic_timer_expired() argument
1893 struct kvm_vcpu *vcpu = apic->vcpu; in apic_timer_expired()
1894 struct kvm_timer *ktimer = &apic->lapic_timer; in apic_timer_expired()
1896 if (atomic_read(&apic->lapic_timer.pending)) in apic_timer_expired()
1899 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) in apic_timer_expired()
1902 if (!from_timer_fn && apic->apicv_active) { in apic_timer_expired()
1904 kvm_apic_inject_pending_timer_irqs(apic); in apic_timer_expired()
1908 if (kvm_use_posted_timer_interrupt(apic->vcpu)) { in apic_timer_expired()
1916 if (vcpu->arch.apic->lapic_timer.expired_tscdeadline && in apic_timer_expired()
1917 vcpu->arch.apic->lapic_timer.timer_advance_ns) in apic_timer_expired()
1919 kvm_apic_inject_pending_timer_irqs(apic); in apic_timer_expired()
1923 atomic_inc(&apic->lapic_timer.pending); in apic_timer_expired()
1929 static void start_sw_tscdeadline(struct kvm_lapic *apic) in start_sw_tscdeadline() argument
1931 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_tscdeadline()
1935 struct kvm_vcpu *vcpu = apic->vcpu; in start_sw_tscdeadline()
1952 likely(ns > apic->lapic_timer.timer_advance_ns)) { in start_sw_tscdeadline()
1957 apic_timer_expired(apic, false); in start_sw_tscdeadline()
1962 static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict) in tmict_to_ns() argument
1964 return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count; in tmict_to_ns()
1967 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) in update_target_expiration() argument
1972 apic->lapic_timer.period = in update_target_expiration()
1973 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT)); in update_target_expiration()
1974 limit_periodic_timer_frequency(apic); in update_target_expiration()
1977 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in update_target_expiration()
1983 apic->divide_count, old_divisor); in update_target_expiration()
1985 apic->lapic_timer.tscdeadline += in update_target_expiration()
1986 nsec_to_cycles(apic->vcpu, ns_remaining_new) - in update_target_expiration()
1987 nsec_to_cycles(apic->vcpu, ns_remaining_old); in update_target_expiration()
1988 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); in update_target_expiration()
1991 static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg) in set_target_expiration() argument
1998 apic->lapic_timer.period = in set_target_expiration()
1999 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT)); in set_target_expiration()
2001 if (!apic->lapic_timer.period) { in set_target_expiration()
2002 apic->lapic_timer.tscdeadline = 0; in set_target_expiration()
2006 limit_periodic_timer_frequency(apic); in set_target_expiration()
2007 deadline = apic->lapic_timer.period; in set_target_expiration()
2009 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { in set_target_expiration()
2011 deadline = tmict_to_ns(apic, in set_target_expiration()
2012 kvm_lapic_get_reg(apic, count_reg)); in set_target_expiration()
2014 if (apic_lvtt_period(apic)) in set_target_expiration()
2015 deadline = apic->lapic_timer.period; in set_target_expiration()
2019 else if (unlikely(deadline > apic->lapic_timer.period)) { in set_target_expiration()
2024 apic->vcpu->vcpu_id, in set_target_expiration()
2026 kvm_lapic_get_reg(apic, count_reg), in set_target_expiration()
2027 deadline, apic->lapic_timer.period); in set_target_expiration()
2028 kvm_lapic_set_reg(apic, count_reg, 0); in set_target_expiration()
2029 deadline = apic->lapic_timer.period; in set_target_expiration()
2034 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in set_target_expiration()
2035 nsec_to_cycles(apic->vcpu, deadline); in set_target_expiration()
2036 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline); in set_target_expiration()
2041 static void advance_periodic_target_expiration(struct kvm_lapic *apic) in advance_periodic_target_expiration() argument
2054 apic->lapic_timer.target_expiration = in advance_periodic_target_expiration()
2055 ktime_add_ns(apic->lapic_timer.target_expiration, in advance_periodic_target_expiration()
2056 apic->lapic_timer.period); in advance_periodic_target_expiration()
2057 delta = ktime_sub(apic->lapic_timer.target_expiration, now); in advance_periodic_target_expiration()
2058 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in advance_periodic_target_expiration()
2059 nsec_to_cycles(apic->vcpu, delta); in advance_periodic_target_expiration()
2062 static void start_sw_period(struct kvm_lapic *apic) in start_sw_period() argument
2064 if (!apic->lapic_timer.period) in start_sw_period()
2068 apic->lapic_timer.target_expiration)) { in start_sw_period()
2069 apic_timer_expired(apic, false); in start_sw_period()
2071 if (apic_lvtt_oneshot(apic)) in start_sw_period()
2074 advance_periodic_target_expiration(apic); in start_sw_period()
2077 hrtimer_start(&apic->lapic_timer.timer, in start_sw_period()
2078 apic->lapic_timer.target_expiration, in start_sw_period()
2087 return vcpu->arch.apic->lapic_timer.hv_timer_in_use; in kvm_lapic_hv_timer_in_use()
2090 static void cancel_hv_timer(struct kvm_lapic *apic) in cancel_hv_timer() argument
2093 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in cancel_hv_timer()
2094 static_call(kvm_x86_cancel_hv_timer)(apic->vcpu); in cancel_hv_timer()
2095 apic->lapic_timer.hv_timer_in_use = false; in cancel_hv_timer()
2098 static bool start_hv_timer(struct kvm_lapic *apic) in start_hv_timer() argument
2100 struct kvm_timer *ktimer = &apic->lapic_timer; in start_hv_timer()
2101 struct kvm_vcpu *vcpu = apic->vcpu; in start_hv_timer()
2122 if (!apic_lvtt_period(apic)) { in start_hv_timer()
2128 cancel_hv_timer(apic); in start_hv_timer()
2130 apic_timer_expired(apic, false); in start_hv_timer()
2131 cancel_hv_timer(apic); in start_hv_timer()
2140 static void start_sw_timer(struct kvm_lapic *apic) in start_sw_timer() argument
2142 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_timer()
2145 if (apic->lapic_timer.hv_timer_in_use) in start_sw_timer()
2146 cancel_hv_timer(apic); in start_sw_timer()
2147 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) in start_sw_timer()
2150 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) in start_sw_timer()
2151 start_sw_period(apic); in start_sw_timer()
2152 else if (apic_lvtt_tscdeadline(apic)) in start_sw_timer()
2153 start_sw_tscdeadline(apic); in start_sw_timer()
2154 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); in start_sw_timer()
2157 static void restart_apic_timer(struct kvm_lapic *apic) in restart_apic_timer() argument
2161 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending)) in restart_apic_timer()
2164 if (!start_hv_timer(apic)) in restart_apic_timer()
2165 start_sw_timer(apic); in restart_apic_timer()
2172 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_expired_hv_timer() local
2176 if (!apic->lapic_timer.hv_timer_in_use) in kvm_lapic_expired_hv_timer()
2179 apic_timer_expired(apic, false); in kvm_lapic_expired_hv_timer()
2180 cancel_hv_timer(apic); in kvm_lapic_expired_hv_timer()
2182 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in kvm_lapic_expired_hv_timer()
2183 advance_periodic_target_expiration(apic); in kvm_lapic_expired_hv_timer()
2184 restart_apic_timer(apic); in kvm_lapic_expired_hv_timer()
2193 restart_apic_timer(vcpu->arch.apic); in kvm_lapic_switch_to_hv_timer()
2198 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_switch_to_sw_timer() local
2202 if (apic->lapic_timer.hv_timer_in_use) in kvm_lapic_switch_to_sw_timer()
2203 start_sw_timer(apic); in kvm_lapic_switch_to_sw_timer()
2209 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_restart_hv_timer() local
2211 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in kvm_lapic_restart_hv_timer()
2212 restart_apic_timer(apic); in kvm_lapic_restart_hv_timer()
2215 static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg) in __start_apic_timer() argument
2217 atomic_set(&apic->lapic_timer.pending, 0); in __start_apic_timer()
2219 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) in __start_apic_timer()
2220 && !set_target_expiration(apic, count_reg)) in __start_apic_timer()
2223 restart_apic_timer(apic); in __start_apic_timer()
2226 static void start_apic_timer(struct kvm_lapic *apic) in start_apic_timer() argument
2228 __start_apic_timer(apic, APIC_TMICT); in start_apic_timer()
2231 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) in apic_manage_nmi_watchdog() argument
2235 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { in apic_manage_nmi_watchdog()
2236 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; in apic_manage_nmi_watchdog()
2238 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
2240 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
2254 static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) in kvm_lapic_reg_write() argument
2261 case APIC_ID: /* Local APIC ID */ in kvm_lapic_reg_write()
2262 if (!apic_x2apic_mode(apic)) { in kvm_lapic_reg_write()
2263 kvm_apic_set_xapic_id(apic, val >> 24); in kvm_lapic_reg_write()
2270 report_tpr_access(apic, true); in kvm_lapic_reg_write()
2271 apic_set_tpr(apic, val & 0xff); in kvm_lapic_reg_write()
2275 apic_set_eoi(apic); in kvm_lapic_reg_write()
2279 if (!apic_x2apic_mode(apic)) in kvm_lapic_reg_write()
2280 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); in kvm_lapic_reg_write()
2286 if (!apic_x2apic_mode(apic)) in kvm_lapic_reg_write()
2287 kvm_apic_set_dfr(apic, val | 0x0FFFFFFF); in kvm_lapic_reg_write()
2294 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) in kvm_lapic_reg_write()
2296 apic_set_spiv(apic, val & mask); in kvm_lapic_reg_write()
2300 for (i = 0; i < apic->nr_lvt_entries; i++) { in kvm_lapic_reg_write()
2301 kvm_lapic_set_reg(apic, APIC_LVTx(i), in kvm_lapic_reg_write()
2302 kvm_lapic_get_reg(apic, APIC_LVTx(i)) | APIC_LVT_MASKED); in kvm_lapic_reg_write()
2304 apic_update_lvtt(apic); in kvm_lapic_reg_write()
2305 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reg_write()
2311 WARN_ON_ONCE(apic_x2apic_mode(apic)); in kvm_lapic_reg_write()
2315 kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2)); in kvm_lapic_reg_write()
2316 kvm_lapic_set_reg(apic, APIC_ICR, val); in kvm_lapic_reg_write()
2319 if (apic_x2apic_mode(apic)) in kvm_lapic_reg_write()
2322 kvm_lapic_set_reg(apic, APIC_ICR2, val & 0xff000000); in kvm_lapic_reg_write()
2326 apic_manage_nmi_watchdog(apic, val); in kvm_lapic_reg_write()
2334 if (!kvm_lapic_lvt_supported(apic, index)) { in kvm_lapic_reg_write()
2338 if (!kvm_apic_sw_enabled(apic)) in kvm_lapic_reg_write()
2341 kvm_lapic_set_reg(apic, reg, val); in kvm_lapic_reg_write()
2346 if (!kvm_apic_sw_enabled(apic)) in kvm_lapic_reg_write()
2348 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); in kvm_lapic_reg_write()
2349 kvm_lapic_set_reg(apic, APIC_LVTT, val); in kvm_lapic_reg_write()
2350 apic_update_lvtt(apic); in kvm_lapic_reg_write()
2354 if (apic_lvtt_tscdeadline(apic)) in kvm_lapic_reg_write()
2357 cancel_apic_timer(apic); in kvm_lapic_reg_write()
2358 kvm_lapic_set_reg(apic, APIC_TMICT, val); in kvm_lapic_reg_write()
2359 start_apic_timer(apic); in kvm_lapic_reg_write()
2363 uint32_t old_divisor = apic->divide_count; in kvm_lapic_reg_write()
2365 kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); in kvm_lapic_reg_write()
2366 update_divide_count(apic); in kvm_lapic_reg_write()
2367 if (apic->divide_count != old_divisor && in kvm_lapic_reg_write()
2368 apic->lapic_timer.period) { in kvm_lapic_reg_write()
2369 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reg_write()
2370 update_target_expiration(apic, old_divisor); in kvm_lapic_reg_write()
2371 restart_apic_timer(apic); in kvm_lapic_reg_write()
2376 if (apic_x2apic_mode(apic) && val != 0) in kvm_lapic_reg_write()
2385 if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK)) in kvm_lapic_reg_write()
2388 kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0); in kvm_lapic_reg_write()
2396 * Recalculate APIC maps if necessary, e.g. if the software enable bit in kvm_lapic_reg_write()
2397 * was toggled, the APIC ID changed, etc... The maps are marked dirty in kvm_lapic_reg_write()
2400 kvm_recalculate_apic_map(apic->vcpu->kvm); in kvm_lapic_reg_write()
2408 struct kvm_lapic *apic = to_lapic(this); in apic_mmio_write() local
2409 unsigned int offset = address - apic->base_address; in apic_mmio_write()
2412 if (!apic_mmio_in_range(apic, address)) in apic_mmio_write()
2415 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { in apic_mmio_write()
2424 * APIC register must be aligned on 128-bits boundary. in apic_mmio_write()
2433 kvm_lapic_reg_write(apic, offset & 0xff0, val); in apic_mmio_write()
2440 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); in kvm_lapic_set_eoi()
2446 int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data) in kvm_x2apic_icr_write() argument
2461 kvm_apic_send_ipi(apic, (u32)data, (u32)(data >> 32)); in kvm_x2apic_icr_write()
2463 kvm_lapic_set_reg(apic, APIC_ICR, data); in kvm_x2apic_icr_write()
2464 kvm_lapic_set_reg(apic, APIC_ICR2, data >> 32); in kvm_x2apic_icr_write()
2466 kvm_lapic_set_reg64(apic, APIC_ICR, data); in kvm_x2apic_icr_write()
2472 static u64 kvm_x2apic_icr_read(struct kvm_lapic *apic) in kvm_x2apic_icr_read() argument
2475 return (u64)kvm_lapic_get_reg(apic, APIC_ICR) | in kvm_x2apic_icr_read()
2476 (u64)kvm_lapic_get_reg(apic, APIC_ICR2) << 32; in kvm_x2apic_icr_read()
2478 return kvm_lapic_get_reg64(apic, APIC_ICR); in kvm_x2apic_icr_read()
2481 /* emulate APIC access in a trap manner */
2484 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_write_nodecode() local
2492 * virtual APIC state, but KVM needs to conditionally modify the value in kvm_apic_write_nodecode()
2497 if (apic_x2apic_mode(apic) && offset == APIC_ICR) in kvm_apic_write_nodecode()
2498 WARN_ON_ONCE(kvm_x2apic_icr_write(apic, kvm_x2apic_icr_read(apic))); in kvm_apic_write_nodecode()
2500 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); in kvm_apic_write_nodecode()
2506 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_free_lapic() local
2508 if (!vcpu->arch.apic) in kvm_free_lapic()
2511 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_free_lapic()
2516 if (!apic->sw_enabled) in kvm_free_lapic()
2519 if (apic->regs) in kvm_free_lapic()
2520 free_page((unsigned long)apic->regs); in kvm_free_lapic()
2522 kfree(apic); in kvm_free_lapic()
2532 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_lapic_tscdeadline_msr() local
2534 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic)) in kvm_get_lapic_tscdeadline_msr()
2537 return apic->lapic_timer.tscdeadline; in kvm_get_lapic_tscdeadline_msr()
2542 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_set_lapic_tscdeadline_msr() local
2544 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic)) in kvm_set_lapic_tscdeadline_msr()
2547 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_set_lapic_tscdeadline_msr()
2548 apic->lapic_timer.tscdeadline = data; in kvm_set_lapic_tscdeadline_msr()
2549 start_apic_timer(apic); in kvm_set_lapic_tscdeadline_msr()
2554 apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4); in kvm_lapic_set_tpr()
2561 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); in kvm_lapic_get_cr8()
2569 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_set_base() local
2576 if (!apic) in kvm_lapic_set_base()
2582 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2588 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_lapic_set_base()
2594 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2596 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2604 apic->base_address = apic->vcpu->arch.apic_base & in kvm_lapic_set_base()
2608 apic->base_address != APIC_DEFAULT_PHYS_BASE) { in kvm_lapic_set_base()
2609 kvm_set_apicv_inhibit(apic->vcpu->kvm, in kvm_lapic_set_base()
2616 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_apicv() local
2631 apic->irr_pending = true; in kvm_apic_update_apicv()
2633 if (apic->apicv_active) in kvm_apic_update_apicv()
2634 apic->isr_count = 1; in kvm_apic_update_apicv()
2636 apic->isr_count = count_vectors(apic->regs + APIC_ISR); in kvm_apic_update_apicv()
2638 apic->highest_isr_cache = -1; in kvm_apic_update_apicv()
2714 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_reset() local
2727 if (!apic) in kvm_lapic_reset()
2730 /* Stop the timer in case it's a reset to an active apic */ in kvm_lapic_reset()
2731 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reset()
2733 /* The xAPIC ID is set at RESET even if the APIC was already enabled. */ in kvm_lapic_reset()
2735 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_reset()
2736 kvm_apic_set_version(apic->vcpu); in kvm_lapic_reset()
2738 for (i = 0; i < apic->nr_lvt_entries; i++) in kvm_lapic_reset()
2739 kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED); in kvm_lapic_reset()
2740 apic_update_lvtt(apic); in kvm_lapic_reset()
2743 kvm_lapic_set_reg(apic, APIC_LVT0, in kvm_lapic_reset()
2745 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); in kvm_lapic_reset()
2747 kvm_apic_set_dfr(apic, 0xffffffffU); in kvm_lapic_reset()
2748 apic_set_spiv(apic, 0xff); in kvm_lapic_reset()
2749 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); in kvm_lapic_reset()
2750 if (!apic_x2apic_mode(apic)) in kvm_lapic_reset()
2751 kvm_apic_set_ldr(apic, 0); in kvm_lapic_reset()
2752 kvm_lapic_set_reg(apic, APIC_ESR, 0); in kvm_lapic_reset()
2753 if (!apic_x2apic_mode(apic)) { in kvm_lapic_reset()
2754 kvm_lapic_set_reg(apic, APIC_ICR, 0); in kvm_lapic_reset()
2755 kvm_lapic_set_reg(apic, APIC_ICR2, 0); in kvm_lapic_reset()
2757 kvm_lapic_set_reg64(apic, APIC_ICR, 0); in kvm_lapic_reset()
2759 kvm_lapic_set_reg(apic, APIC_TDCR, 0); in kvm_lapic_reset()
2760 kvm_lapic_set_reg(apic, APIC_TMICT, 0); in kvm_lapic_reset()
2762 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); in kvm_lapic_reset()
2763 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); in kvm_lapic_reset()
2764 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); in kvm_lapic_reset()
2767 update_divide_count(apic); in kvm_lapic_reset()
2768 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reset()
2771 apic_update_ppr(apic); in kvm_lapic_reset()
2772 if (apic->apicv_active) { in kvm_lapic_reset()
2790 static bool lapic_is_periodic(struct kvm_lapic *apic) in lapic_is_periodic() argument
2792 return apic_lvtt_period(apic); in lapic_is_periodic()
2797 struct kvm_lapic *apic = vcpu->arch.apic; in apic_has_pending_timer() local
2799 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) in apic_has_pending_timer()
2800 return atomic_read(&apic->lapic_timer.pending); in apic_has_pending_timer()
2805 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) in kvm_apic_local_deliver() argument
2807 u32 reg = kvm_lapic_get_reg(apic, lvt_type); in kvm_apic_local_deliver()
2811 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { in kvm_apic_local_deliver()
2816 r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL); in kvm_apic_local_deliver()
2818 guest_cpuid_is_intel_compatible(apic->vcpu)) in kvm_apic_local_deliver()
2819 kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED); in kvm_apic_local_deliver()
2827 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_nmi_wd_deliver() local
2829 if (apic) in kvm_apic_nmi_wd_deliver()
2830 kvm_apic_local_deliver(apic, APIC_LVT0); in kvm_apic_nmi_wd_deliver()
2841 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); in apic_timer_fn() local
2843 apic_timer_expired(apic, true); in apic_timer_fn()
2845 if (lapic_is_periodic(apic)) { in apic_timer_fn()
2846 advance_periodic_target_expiration(apic); in apic_timer_fn()
2855 struct kvm_lapic *apic; in kvm_create_lapic() local
2859 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT); in kvm_create_lapic()
2860 if (!apic) in kvm_create_lapic()
2863 vcpu->arch.apic = apic; in kvm_create_lapic()
2865 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); in kvm_create_lapic()
2866 if (!apic->regs) { in kvm_create_lapic()
2867 printk(KERN_ERR "malloc apic regs error for vcpu %x\n", in kvm_create_lapic()
2871 apic->vcpu = vcpu; in kvm_create_lapic()
2873 apic->nr_lvt_entries = kvm_apic_calc_nr_lvt_entries(vcpu); in kvm_create_lapic()
2875 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, in kvm_create_lapic()
2877 apic->lapic_timer.timer.function = apic_timer_fn; in kvm_create_lapic()
2879 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; in kvm_create_lapic()
2882 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in kvm_create_lapic()
2887 * Stuff the APIC ENABLE bit in lieu of temporarily incrementing in kvm_create_lapic()
2892 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); in kvm_create_lapic()
2896 kfree(apic); in kvm_create_lapic()
2897 vcpu->arch.apic = NULL; in kvm_create_lapic()
2904 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_has_interrupt() local
2910 __apic_update_ppr(apic, &ppr); in kvm_apic_has_interrupt()
2911 return apic_has_interrupt_for_ppr(apic, ppr); in kvm_apic_has_interrupt()
2917 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); in kvm_apic_accept_pic_intr()
2919 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) in kvm_apic_accept_pic_intr()
2929 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_inject_apic_timer_irqs() local
2931 if (atomic_read(&apic->lapic_timer.pending) > 0) { in kvm_inject_apic_timer_irqs()
2932 kvm_apic_inject_pending_timer_irqs(apic); in kvm_inject_apic_timer_irqs()
2933 atomic_set(&apic->lapic_timer.pending, 0); in kvm_inject_apic_timer_irqs()
2940 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_apic_interrupt() local
2947 * We get here even with APIC virtualization enabled, if doing in kvm_get_apic_interrupt()
2953 apic_clear_irr(vector, apic); in kvm_get_apic_interrupt()
2960 apic_update_ppr(apic); in kvm_get_apic_interrupt()
2968 apic_set_isr(vector, apic); in kvm_get_apic_interrupt()
2969 __apic_update_ppr(apic, &ppr); in kvm_get_apic_interrupt()
2978 if (apic_x2apic_mode(vcpu->arch.apic)) { in kvm_apic_state_fixup()
2979 u32 x2apic_id = kvm_x2apic_id(vcpu->arch.apic); in kvm_apic_state_fixup()
2989 * Ignore the userspace value when setting APIC state. in kvm_apic_state_fixup()
3029 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); in kvm_apic_get_state()
3036 __apic_read(vcpu->arch.apic, APIC_TMCCT)); in kvm_apic_get_state()
3043 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_state() local
3050 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); in kvm_apic_set_state()
3057 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); in kvm_apic_set_state()
3059 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_state()
3063 apic_update_ppr(apic); in kvm_apic_set_state()
3064 cancel_apic_timer(apic); in kvm_apic_set_state()
3065 apic->lapic_timer.expired_tscdeadline = 0; in kvm_apic_set_state()
3066 apic_update_lvtt(apic); in kvm_apic_set_state()
3067 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); in kvm_apic_set_state()
3068 update_divide_count(apic); in kvm_apic_set_state()
3069 __start_apic_timer(apic, APIC_TMCCT); in kvm_apic_set_state()
3070 kvm_lapic_set_reg(apic, APIC_TMCCT, 0); in kvm_apic_set_state()
3072 if (apic->apicv_active) { in kvm_apic_set_state()
3074 static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, apic_find_highest_irr(apic)); in kvm_apic_set_state()
3075 static_call_cond(kvm_x86_hwapic_isr_update)(apic_find_highest_isr(apic)); in kvm_apic_set_state()
3094 timer = &vcpu->arch.apic->lapic_timer.timer; in __kvm_migrate_apic_timer()
3107 struct kvm_lapic *apic) in apic_sync_pv_eoi_from_guest() argument
3125 vector = apic_set_eoi(apic); in apic_sync_pv_eoi_from_guest()
3126 trace_kvm_pv_eoi(apic, vector); in apic_sync_pv_eoi_from_guest()
3134 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); in kvm_lapic_sync_from_vapic()
3139 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_from_vapic()
3143 apic_set_tpr(vcpu->arch.apic, data & 0xff); in kvm_lapic_sync_from_vapic()
3153 struct kvm_lapic *apic) in apic_sync_pv_eoi_to_guest() argument
3157 apic->irr_pending || in apic_sync_pv_eoi_to_guest()
3159 apic->highest_isr_cache == -1 || in apic_sync_pv_eoi_to_guest()
3161 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { in apic_sync_pv_eoi_to_guest()
3169 pv_eoi_set_pending(apic->vcpu); in apic_sync_pv_eoi_to_guest()
3176 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_sync_to_vapic() local
3178 apic_sync_pv_eoi_to_guest(vcpu, apic); in kvm_lapic_sync_to_vapic()
3183 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; in kvm_lapic_sync_to_vapic()
3184 max_irr = apic_find_highest_irr(apic); in kvm_lapic_sync_to_vapic()
3187 max_isr = apic_find_highest_isr(apic); in kvm_lapic_sync_to_vapic()
3192 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_to_vapic()
3200 &vcpu->arch.apic->vapic_cache, in kvm_lapic_set_vapic_addr()
3208 vcpu->arch.apic->vapic_addr = vapic_addr; in kvm_lapic_set_vapic_addr()
3212 static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data) in kvm_lapic_msr_read() argument
3217 *data = kvm_x2apic_icr_read(apic); in kvm_lapic_msr_read()
3221 if (kvm_lapic_reg_read(apic, reg, 4, &low)) in kvm_lapic_msr_read()
3229 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data) in kvm_lapic_msr_write() argument
3237 return kvm_x2apic_icr_write(apic, data); in kvm_lapic_msr_write()
3243 return kvm_lapic_reg_write(apic, reg, (u32)data); in kvm_lapic_msr_write()
3248 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_write() local
3251 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) in kvm_x2apic_msr_write()
3254 return kvm_lapic_msr_write(apic, reg, data); in kvm_x2apic_msr_write()
3259 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_read() local
3262 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) in kvm_x2apic_msr_read()
3265 return kvm_lapic_msr_read(apic, reg, data); in kvm_x2apic_msr_read()
3273 return kvm_lapic_msr_write(vcpu->arch.apic, reg, data); in kvm_hv_vapic_msr_write()
3281 return kvm_lapic_msr_read(vcpu->arch.apic, reg, data); in kvm_hv_vapic_msr_read()
3312 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_accept_events() local
3337 clear_bit(KVM_APIC_SIPI, &apic->pending_events); in kvm_apic_accept_events()
3341 if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) { in kvm_apic_accept_events()
3343 if (kvm_vcpu_is_bsp(apic->vcpu)) in kvm_apic_accept_events()
3348 if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events)) { in kvm_apic_accept_events()
3352 sipi_vector = apic->sipi_vector; in kvm_apic_accept_events()