Lines Matching full:apic
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
25 * - SiS APIC rmw bug:
67 #include <asm/apic.h>
90 int apic, pin; member
116 /* I/O APIC config */
118 /* IO APIC gsi routing info */
197 /* disable IO-APIC */ in parse_noapic()
209 " IRQ %02x, APIC ID %x, APIC INT %02x\n", in mp_save_irq()
269 static inline void io_apic_eoi(unsigned int apic, unsigned int vector) in io_apic_eoi() argument
271 struct io_apic __iomem *io_apic = io_apic_base(apic); in io_apic_eoi()
275 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) in native_io_apic_read() argument
277 struct io_apic __iomem *io_apic = io_apic_base(apic); in native_io_apic_read()
282 static void io_apic_write(unsigned int apic, unsigned int reg, in io_apic_write() argument
285 struct io_apic __iomem *io_apic = io_apic_base(apic); in io_apic_write()
291 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) in __ioapic_read_entry() argument
295 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin); in __ioapic_read_entry()
296 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin); in __ioapic_read_entry()
301 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) in ioapic_read_entry() argument
307 entry = __ioapic_read_entry(apic, pin); in ioapic_read_entry()
314 * When we write a new IO APIC routing entry, we need to write the high
319 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) in __ioapic_write_entry() argument
321 io_apic_write(apic, 0x11 + 2*pin, e.w2); in __ioapic_write_entry()
322 io_apic_write(apic, 0x10 + 2*pin, e.w1); in __ioapic_write_entry()
325 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) in ioapic_write_entry() argument
330 __ioapic_write_entry(apic, pin, e); in ioapic_write_entry()
335 * When we mask an IO APIC routing entry, we need to write the low
339 static void ioapic_mask_entry(int apic, int pin) in ioapic_mask_entry() argument
345 io_apic_write(apic, 0x10 + 2*pin, e.w1); in ioapic_mask_entry()
346 io_apic_write(apic, 0x11 + 2*pin, e.w2); in ioapic_mask_entry()
355 static bool add_pin_to_irq_node(struct mp_chip_data *data, int node, int apic, int pin) in add_pin_to_irq_node() argument
361 if (entry->apic == apic && entry->pin == pin) in add_pin_to_irq_node()
367 pr_err("Cannot allocate irq_pin_list (%d,%d,%d)\n", node, apic, pin); in add_pin_to_irq_node()
371 entry->apic = apic; in add_pin_to_irq_node()
377 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) in __remove_pin_from_irq() argument
382 if (entry->apic == apic && entry->pin == pin) { in __remove_pin_from_irq()
399 if (entry->apic == oldapic && entry->pin == oldpin) { in replace_pin_at_irq_node()
400 entry->apic = newapic; in replace_pin_at_irq_node()
407 /* old apic/pin didn't exist, so just add new ones */ in replace_pin_at_irq_node()
419 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1); in io_apic_modify_irq()
428 * Synchronize the IO-APIC and the CPU by doing in io_apic_sync()
429 * a dummy read from the IO-APIC in io_apic_sync()
433 io_apic = io_apic_base(entry->apic); in io_apic_sync()
463 * IO-APIC versions below 0x20 don't support EOI register.
466 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
467 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
470 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
472 * use io-apic's of version 0x20.
474 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
478 static void __eoi_ioapic_pin(int apic, int pin, int vector) in __eoi_ioapic_pin() argument
480 if (mpc_ioapic_ver(apic) >= 0x20) { in __eoi_ioapic_pin()
481 io_apic_eoi(apic, vector); in __eoi_ioapic_pin()
485 entry = entry1 = __ioapic_read_entry(apic, pin); in __eoi_ioapic_pin()
493 __ioapic_write_entry(apic, pin, entry1); in __eoi_ioapic_pin()
498 __ioapic_write_entry(apic, pin, entry); in __eoi_ioapic_pin()
509 __eoi_ioapic_pin(entry->apic, entry->pin, vector); in eoi_ioapic_pin()
513 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) in clear_IO_APIC_pin() argument
518 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
528 ioapic_write_entry(apic, pin, entry); in clear_IO_APIC_pin()
529 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
542 ioapic_write_entry(apic, pin, entry); in clear_IO_APIC_pin()
545 __eoi_ioapic_pin(apic, pin, entry.vector); in clear_IO_APIC_pin()
550 * Clear the rest of the bits in the IO-APIC RTE except for the mask in clear_IO_APIC_pin()
553 ioapic_mask_entry(apic, pin); in clear_IO_APIC_pin()
554 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
556 pr_err("Unable to reset IRR for apic: %d, pin :%d\n", in clear_IO_APIC_pin()
557 mpc_ioapic_id(apic), pin); in clear_IO_APIC_pin()
562 int apic, pin; in clear_IO_APIC() local
564 for_each_ioapic_pin(apic, pin) in clear_IO_APIC()
565 clear_IO_APIC_pin(apic, pin); in clear_IO_APIC()
607 * Saves all the IO-APIC RTE's
611 int apic, pin; in save_ioapic_entries() local
614 for_each_ioapic(apic) { in save_ioapic_entries()
615 if (!ioapics[apic].saved_registers) { in save_ioapic_entries()
620 for_each_pin(apic, pin) in save_ioapic_entries()
621 ioapics[apic].saved_registers[pin] = in save_ioapic_entries()
622 ioapic_read_entry(apic, pin); in save_ioapic_entries()
629 * Mask all IO APIC entries.
633 int apic, pin; in mask_ioapic_entries() local
635 for_each_ioapic(apic) { in mask_ioapic_entries()
636 if (!ioapics[apic].saved_registers) in mask_ioapic_entries()
639 for_each_pin(apic, pin) { in mask_ioapic_entries()
642 entry = ioapics[apic].saved_registers[pin]; in mask_ioapic_entries()
645 ioapic_write_entry(apic, pin, entry); in mask_ioapic_entries()
652 * Restore IO APIC entries which was saved in the ioapic structure.
656 int apic, pin; in restore_ioapic_entries() local
658 for_each_ioapic(apic) { in restore_ioapic_entries()
659 if (!ioapics[apic].saved_registers) in restore_ioapic_entries()
662 for_each_pin(apic, pin) in restore_ioapic_entries()
663 ioapic_write_entry(apic, pin, in restore_ioapic_entries()
664 ioapics[apic].saved_registers[pin]); in restore_ioapic_entries()
1209 KERN_DEBUG " apic %d pin %d not connected\n", in setup_IO_APIC_irqs()
1222 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries) in io_apic_print_entries() argument
1228 printk(KERN_DEBUG "IOAPIC %d:\n", apic); in io_apic_print_entries()
1230 entry = ioapic_read_entry(apic, i); in io_apic_print_entries()
1269 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); in print_IO_APIC()
1271 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); in print_IO_APIC()
1280 printk(KERN_DEBUG "....... : IO APIC version: %02X\n", in print_IO_APIC()
1284 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, in print_IO_APIC()
1294 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 in print_IO_APIC()
1315 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", in print_IO_APICs()
1323 printk(KERN_INFO "testing the IO APIC.......................\n"); in print_IO_APICs()
1345 pr_cont("-> %d:%d", entry->apic, entry->pin); in print_IO_APICs()
1353 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; member
1358 int apic, pin; in enable_IO_APIC() local
1366 for_each_ioapic_pin(apic, pin) { in enable_IO_APIC()
1368 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); in enable_IO_APIC()
1375 ioapic_i8259.apic = apic; in enable_IO_APIC()
1392 ioapic_i8259.apic = i8259_apic; in enable_IO_APIC()
1395 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && in enable_IO_APIC()
1402 * Do not trust the IO-APIC being empty at bootup in enable_IO_APIC()
1428 * Add it to the IO-APIC irq-routing table: in native_restore_boot_irq_mode()
1430 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); in native_restore_boot_irq_mode()
1447 * function to set the IO-APIC physical IDs based on the
1465 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); in setup_ioapic_ids_from_mpc_nocheck()
1479 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", in setup_ioapic_ids_from_mpc_nocheck()
1487 * Sanity check, is the ID really free? Every APIC in a in setup_ioapic_ids_from_mpc_nocheck()
1491 if (apic->check_apicid_used(&phys_id_present_map, in setup_ioapic_ids_from_mpc_nocheck()
1493 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", in setup_ioapic_ids_from_mpc_nocheck()
1499 panic("Max APIC ID exceeded!\n"); in setup_ioapic_ids_from_mpc_nocheck()
1528 "...changing IO-APIC physical APIC ID to %d ...", in setup_ioapic_ids_from_mpc_nocheck()
1555 * Don't check I/O APIC IDs for xAPIC systems. They have in setup_ioapic_ids_from_mpc()
1556 * no meaning without the serial APIC bus. in setup_ioapic_ids_from_mpc()
1615 * - timer IRQ defaults to IO-APIC IRQ
1635 * ticks in a non-ExtINT mode. Also the local APIC in timer_irq_works()
1660 * Starting up a edge-triggered IO-APIC interrupt is
1699 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2); in io_apic_level_ack_pending()
1780 * of I/O APIC (that's the 82093AA and cores integrated into various in ioapic_ack_level()
1792 * trigger mode gets detected in the TMR of a local APIC for a in ioapic_ack_level()
1801 * level-triggered io-apic interrupt will be seen as an edge in ioapic_ack_level()
1803 * to be broadcasted to the IO-APIC's which will clear the remoteIRR in ioapic_ack_level()
1804 * corresponding to the level-triggered interrupt. Hence on IO-APIC's in ioapic_ack_level()
1806 * remote IRR and on IO-APIC's which don't have an EOI register, in ioapic_ack_level()
1821 * message via io-apic EOI register write or simulating it using in ioapic_ack_level()
1841 * intr-remapping table entry. Hence for the io-apic in ioapic_ir_ack_level()
1905 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry); in ioapic_configure_entry()
1952 rentry = __ioapic_read_entry(p->apic, p->pin); in ioapic_irq_get_chip_state()
1956 * irrelevant because the IO-APIC treats them as fire and in ioapic_irq_get_chip_state()
1969 .name = "IO-APIC",
1983 .name = "IR-IO-APIC",
2019 * The local APIC irq-chip implementation:
2044 .name = "local-APIC",
2066 int apic, pin, i; in unlock_ExtINT_logic() local
2076 apic = find_isa_irq_apic(8, mp_INT); in unlock_ExtINT_logic()
2077 if (apic == -1) { in unlock_ExtINT_logic()
2082 entry0 = ioapic_read_entry(apic, pin); in unlock_ExtINT_logic()
2083 clear_IO_APIC_pin(apic, pin); in unlock_ExtINT_logic()
2097 ioapic_write_entry(apic, pin, entry1); in unlock_ExtINT_logic()
2114 clear_IO_APIC_pin(apic, pin); in unlock_ExtINT_logic()
2116 ioapic_write_entry(apic, pin, entry0); in unlock_ExtINT_logic()
2176 * wire has to be disabled in the local APIC. Also in check_timer()
2179 * watchdog as that APIC treats NMIs as level-triggered. in check_timer()
2189 apic2 = ioapic_i8259.apic; in check_timer()
2197 * I/O APIC input from the cascaded 8259A as the timer in check_timer()
2203 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); in check_timer()
2234 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); in check_timer()
2238 "8254 timer not connected to IO-APIC\n"); in check_timer()
2243 "..... (found apic %d pin %d) ...\n", apic2, pin2); in check_timer()
2245 * legacy devices should be connected to IO APIC #0 in check_timer()
2297 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " in check_timer()
2305 * to devices. However there may be an I/O APIC pin available for
2311 * of an override it would be treated as an ordinary ISA I/O APIC
2315 * the same ExtINT cascade interrupt to drive the local APIC of the
2317 * the I/O APIC in all cases now. No actual device should request
2339 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic)); in mp_irqdomain_create()
2394 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); in setup_IO_APIC()
2399 * Set up IO-APIC IRQ routing. in setup_IO_APIC()
2478 * always 0. gsi_top can be 0 if there is no IO/APIC registered. in arch_dynirq_lower_bound()
2495 * The P4 platform supports up to 256 APIC IDs on two separate APIC in io_apic_get_unique_id()
2497 * supports up to 16 on one shared APIC bus. in io_apic_get_unique_id()
2500 * advantage of new APIC bus architecture. in io_apic_get_unique_id()
2504 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); in io_apic_get_unique_id()
2517 * Every APIC in a system must have a unique ID or we get lots of nice in io_apic_get_unique_id()
2520 if (apic->check_apicid_used(&apic_id_map, apic_id)) { in io_apic_get_unique_id()
2523 if (!apic->check_apicid_used(&apic_id_map, i)) in io_apic_get_unique_id()
2675 * Ensure fixmaps for IO-APIC MMIO respect memory encryption pgprot in io_apic_set_fixmap()
2701 "WARNING: bogus zero IO-APIC " in io_apic_init_mappings()
2703 "disabling IO/APIC support!\n"); in io_apic_init_mappings()
2740 "IO APIC resources couldn't be allocated.\n"); in ioapic_insert_resources()
2793 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", in bad_ioapic_register()
2828 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); in mp_register_ioapic()
2981 * Configure the I/O-APIC specific fields in the routing entry.
2983 * This is important to setup the I/O-APIC specific bits (is_level,
2985 * provide the routing information and is oblivious of the I/O-APIC